03/19/2008  by Katherine Derbyshire, Contributing Editor, Solid State Technology
Conferences like the recent SPIE focus on the leading edge (e.g., EUV, double patterning, immersion lithography), yet process technologies remain commercially important long after the leading edge has moved on. Case in point: KrF-based litho, currently used in >30% of 65nm DRAMs and poised to increase substantially. Here's what resist suppliers like Fujifilm Electronic Materials are doing to support this trend.

03/13/2008  Mar. 13, 2008 - Ten outperforming suppliers have been honored with awards by Singapore chipmaker Chartered Semiconductor, for their efforts providing equipment, materials, and service. Dainippon Screen Singapore Pte. Ltd., Sumco Techxiv, and IBM Singapore Pte Ltd were named top suppliers for 2007 in their respective categories.

03/13/2008  Mar. 13, 2008 - JSR says it has achieved 32nm line and space patterns for 22nm node semiconductor devices with a new "freezing material" used in double patterning. Results were presented at last month's SPIE Advanced Lithography conference.

03/12/2008  by M. David Levenson, Editor-in-Chief, Microlithography World
Since high-volume EUV lithography is delayed, the first 32nm generation chips will have to be printed with double patterning technology (DPT) for critical layers and much of the conference focused on the various options, none of which seemed fully developed. (First in a four-part series)

03/12/2008  by M. David Levenson, Editor-in-Chief, Microlithography World
Progress continued in EUV lithography, but at a rate well below that needed for insertion at 32nm. AMD described the patterning of an entire metal-1 layer for a full exposure field chip and the integration of EUVL into the process flow. Sources remain an issue, though some think solid state lasers could help improve efficiency. Others are thinking ahead to 22nm. (Second in a four-part series)

03/12/2008  by M. David Levenson, Editor-in-Chief, Microlithography World
Intel chose this SPIE conference to present five papers on pixelated masks, an apparently abandoned program on pixelated masks that had pre-occupied litho engineers for several years. Elsewhere, prospects for high-index immersion technology seem to be dimming, and progress remains sluggish on a promising medium-throughput e-beam direct write for imprint litho. (Third in a four-part series)

03/12/2008  by M. David Levenson, Editor-in-Chief, Microlithography World
Avoiding unprintable structures will be essential for manufacturing 45nm and smaller circuits, and that was reflected in a series of papers on design for manufacturing and design rule restrictions, some of them quite aggressive. (Fourth in a four-part series)

03/12/2008  EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology, and semiconductor markets, announced that Austrian technology-research company NanoTecCenter Weiz Forschungsgesellschaft mbH (NTC Weiz) has purchased an EVG620 precision alignment system for installation in its new R&D facility focused on organic/plastic electronics.

03/11/2008  March 11, 2008 -- /PRNewswire/ -- ST. FLORIAN, AUSTRIA -- EV Group announces that Austrian technology research company NanoTecCenter Weiz Forschungsgesellschaft mbH (NTC Weiz) has purchased an EVG620 precision alignment system for installation in its new R&D facility focused on organic/plastic electronics.

03/11/2008  by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5). Here, Gregory Denbeaux, assistant professor of nanotechnology at the U. of Albany, gave an overview of progress needed in EUV to make it suitable for high volume manufacturing.

03/07/2008  SUSS MicroTec has launched an "advanced nanotechnology" tool set for its mask aligners. The new nanoimprint lithography (NIL) add-on enables MA6 aligners to print resist thicknesses from less than 100 nanometers to a few hundred microns, with a printing resolution of a few nanometers.

03/06/2008  by M. David Levenson, Editor-in-Chief, Microlithography World
Friday (Feb. 29) sessions at the SPIE Advanced Lithography conference featured detailed presentations by Canon, Nikon, and ASML, all talking about improvements in lens aberration control, defectivity, and throughput. Their water immersion optical lithography equipment seems fully capable of producing 45nm devices, and should be OK with some double patterning at 32nm -- but none of it as shown will jump to the 22nm node.

03/04/2008  March 4, 2008 -- Kurt Ronse, IMEC's director of lithography, reviews that group's progress on EUV (first results on the alpha tool) and double patterning with Solid State Technology's Senior Technical Editor Debra Vogler.

03/04/2008  Semiconductor chipmaker AMD, working together with its research partner IBM, says it has produced a working test chip utilizing extreme ultraviolet (EUV) lithography for the critical first layer of metal connections across the entire chip.

03/04/2008  by Griff Resor, Resor Associates
Mar. 4, 2008 - With 38nm half-pitch seemingly the limit for single image 193nm immersion lithography, how the industry will reach the 32nm and 22nm nodes was the focus of last week's SPIE Advanced Lithography conference. Optics with double patterning, EUV, and e-beam direct write -- which will it be for 22nm? After a decade as a doubting Thomas, here's why I think the biggest IC companies will use EUV for the most difficult layers at the 22nm node.

03/03/2008  March 3, 2008 -- Stefan Wurm, program manager, EUV strategy at SEMATECH, updates Solid State Technology's Senior Technical Editor Debra Vogler on that group's progress in immersion lithography and EUV. Highlighted is progress on EUV mask defectivity and the first integrated chip with a layer made using EUV lithography. He also discusses the nanocomposite approach to high-index immersion lithography and the consortium's efforts to monitor non-optical lithography methods (e.g., NIL).

02/29/2008  Feb, 29, 2008 - In this exclusive video interview, IBM's Lars Liebmann talks about his papers presented at this week's SPIE, including persistent misconceptions about restricted design rules, and the need for designers to react to systematic and stable effects with broad, coarse layout adjustments vs. minor movements based on a specific moment. He also discusses the opportunities at 22nm with "soft" and "hard" DFM, and how these concepts will be required to keep the scaling path profitable.

02/28/2008  SEMATECH, an association of semiconductor technology developers, has purchased Molecular Imprints' new Imprio nanoimprint lithography (NIL) tool, announced this week. SEMATECH will use the Imprio 300 to demonstrate the feasibility of for semiconductor production at 32nm and below.

02/28/2008  by M. David Levenson, Editor-in-Chief, Microlithography World
At about the 90nm node, circuit features so much smaller than the exposure wavelength led to increased circuit variability, lithography hotspots, and limited yields (and applying restrictive design rules had limited success). Now, startup Tela Innovations is proposing a radical step to solve the industry's layout problems: employing pre-defined linear topologies, workable with 32nm and double-patterning and down to 22nm.

02/27/2008  Feb. 27, 2008 - Eight new Fellows have been added to SPIE's roster to honor their scientific and technical contributions in optics/photonics/imaging, and to the group in particular. Also, receiving awards at this year's SPIE Advanced Lithography symposium were researchers from ASML, IBM, KLA-Tencor, and the U. of Wisconsin/Madison.