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WEBCASTS
 Environment, Safety & Health Date and time TBD The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.
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Wafer Processing Date and time TBD As the industry moves to 10nm and 7nm nodes, advances in wafer processing etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.
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Researchers at Oregon State University have the successful loading of biological molecules onto “nanosprings” -- a type of nanostructure that has gained significant interest in recent years for its ability to maximize surface area in microreactors.
A pre-competitive iNEMI R&D project plan, currently under development, will identify approaches capable of meeting wiring density needs for future generations of organic semiconductor packaging substrates. Meeting these future needs will require radical improvements and innovations in all aspects of organic packaging substrate technology.
The IC community has been searching for a manufacturable low-k dielectric which could scale to below K = 2.0, says Dr. Phil Garrou. Microindent photos of uLK 124, released by SBA Materials show a clean ductile indent. SBA reports that their uLK materials can be integrated into existing fab lines using equipment and process flows already in place.
Solid-state, fiber-based, and ultrafast lasers continue to make inroads in microelectronics processing applications, specifically for silicon wafer dicing. While most of these laser-based cutting methods rely on linear movement of the laser beam along a substrate, ESI developed a laser-based "zero-overlap" technique for dicing ultrathin (less than 50 μm thick) Si wafers. 
In August 2010, the Semico IPI index experienced its first drop since December 2009. The Semico IPI Index signals changes in the direction of semiconductor sales growth one year in advance.
Continental Corporation applied economic conveyor and handling modules from IPTE’s EasyLine product portfolio to link its gold and aluminum wire bonding, mounting, and AOI areas.