03/03/2010 

Intel has given its nod to two dozen key partners from its roster of thousands of supply-chain contributors as the 2009 winners of its annual supply chain awards -- and within the listings is a interesting nugget about the chipmaker's lithography strategy.

03/02/2010 

Barclays Capital's CJ Muse came away from SPIE with the message that litho demand is strong, with a "heightened focus on EUV" due to increased costs associated with double patterning -- and why rumors about a delay in EUV adoption may not be accurate after all.

03/02/2010 

Several discussions and presentations at last week's SPIE Advanced Lithography Conference deserve special note -- from work with e-beam EUV mask inspection, to nanoimprint achievements (11nm!), an EUV tool platform roadmap, mask productivity and cost issues at 22nm, and more on SMO and tunable DOEs.

03/01/2010 

Given the advantages and technical feasibility of through-silicon vias (TSV), the major focus now is on the manufacturability and integration of all the different building blocks for TSVs and 3D interconnects. EV Group's Thorsten Matthias et al. review advances in lithography, thin wafer processing, and wafer bonding, and the integration of all these process steps.

03/01/2010 

January semiconductor sales numbers are hot off the press, and already analysts are saying the trendline is being reset for a better-than-predicted 2010, with growth approaching or even exceeding 20%.

03/01/2010  B₂H₆ PLAD and B₁₈H₂₂ molecular implants demonstrate the best R_s-x_j and abruptness characteristics, while beam-line BF₂ implants as well as cluster B implants show worse R_s-x_j characteristics.Shu Qin, Y. Jeff Hu, Allen McTeer, Micron Technology, Inc., Boise, ID USA

03/01/2010 

For low power applications, gate-first is arguably the most appropriate choice, but for high performance applications, complex solutions (e.g., SiGe channel for pMOS) need to be considered in order to meet the performance requirements with a gate-first process.

03/01/2010  Results so far are highly encouraging for III-V MOSFETs to be used for ultra high speed, and ultra low power applications. Richard J.W. Hill, Jeff Huang, Joel Barnett, Paul Kirsch, Raj Jammy, SEMATECH, Austin TX USA

02/26/2010 

The Burn-in & Test Socket (BiTS) Workshop will take place March 7–10, 2010 at the Hilton Phoenix East/Mesa Hotel in Mesa, AZ. More than 30 papers and posters will be presented; participants include end users and suppliers of sockets, boards, burn-in systems, handlers, and packages; and other related equipment, materials, and services. The TechTalk session on PCB design, fabrication and assembly is booked full, as is the tutorial on RF socket characterization by Gert Hohenwarter, Ph.D. of Gatewave Northern Inc. Here are some of the show highlights.

02/26/2010 

Electro Scientific Industries Inc. (Nasdaq: ESIO), a provider of photonic and laser systems for micro-engineering applications, appointed a new member, David Nierenberg, to its Board of Directors. Nierenberg, with professional experience in investing and management consulting, comes to ESI with significant expertise in strategic planning and corporate governance matters.

02/23/2010 

Demand for semiconductor manufacturing equipment continues to surge as the industry emerges from its slumber, with some measurements showing strength not seen in several years, according to the latest monthly data from SEMI and SEAJ.

02/22/2010 

Sanjay Kapasi from KLA-Tencor tells SST how the latest-generation PROLITH virtual lithography tool, PROLITH X3.1, takes aim at the skyrocketing R&D expenses being incurred at the 1X and 2Xnm nodes, by leveraging simulations rather than printed test wafers.

02/22/2010 

The SPIE Advanced Lithography Conference is where experts come to tell their advances in lithography, resists, metrology and design, and this week it appears to be heating up as a battle between optical and surging EUV, with other litho technologies offering a "sanity check," writes Griff Resor.

02/19/2010 

Keithley exec Lee Stauffer explains how adding ultra-fast voltage waveform generation and current/voltage measurement capabilities to the company's Model 4200-SCS semiconductor characterization system benefits a range of applications, from flash memory to CMOS and MEMS.

02/19/2010 

Tessera Technologies Inc. (Nasdaq:TSRA) semiconductor packaging subsidiary, Tessera Inc., signed a technology licensing agreement with Nanium S.A. Nanium, formerly known as Qimonda Portugal, previously was the largest semiconductor packaging assembly and test operation within Qimonda. Nanium has now reorganized as an independent company and will focus on providing assembly and test services for the DRAM memory market and other semiconductor products. Products manufactured by Nanium will be incorporated into computers, servers and various electronic devices such as MP3 players, mobile phones, cameras, and game consoles. The initial term of the license agreement runs through the end of 2017.

02/17/2010 

Vincent Renard and Vincent Jousseaume from CEA-Leti discuss a key new achievement in silicon nanowire synthesis that could open the doors for industrial-scale use offering new functionalities for ICs approaching atomic-scale limitations.

02/17/2010 

System Plus Consulting released its new reverse costing analysis of the enhanced Wafer Level BGA (eWLB) packaging used in the X-GOLD 213 circuit from Infineon. eWLB is a ball grid array (BGA) package based on the emerging fan-out wafer-level package (FO-WLP) concept. All the packaging operations are done at the wafer level, and a fan-out area is provided to extend the package size beyond the IC surface area to allow for higher ball counts. The ball pitch is 0.5mm and only one redistribution layer is used for this 217 balls, 8 × 8mm package.

02/16/2010 

After two months of punishing declines, worldwide silicon wafer shipments rebounded through most of 2010, though in terms of sales there's still a lot of ground to make up, according to new numbers from SEMI.

02/16/2010 

The VectorGuard stencil portfolio from DEK now includes the double layer Platinum stencil, a stencil technology that is said to offer performance benefits over conventional screens. VectorGuard Double Layer Platinum stencils suit semiconductor applications and component manufacture, solar cell manufacture, low-temperature co-fired ceramic (LTCC) manufacture, as well as other production challenges requiring fine line or mixed feature sizes.

02/16/2010 

Last week's IEEE International Solid-State Circuits Conference 2010 (ISSCC, Feb. 7-11, San Francisco, CA), offered many talks and papers on topics ranging from 3D integration to circuit design and memories. Here are just a few examples.