05/28/2008  May 28, 2008 - Qcept Technologies and European R&D organization CEA-Leti have inked a deal to investigate techniques for characterizing leading-edge semiconductor materials and processes, including high-/low-k dielectrics, atomic layer deposition (ALD), fully silicided (FUSI) metal gates, and advanced cleaning technologies.

05/27/2008  May 27, 2008 - Japan's top seven chip companies -- Toshiba, Elpida, Sony, Renesas, NEC Electronics, Matsushita, and Fujitsu Microelectronics -- plan to cut their combined capex by 21.8% in fiscal 2008 to ¥806.7B (US $7.81B), mainly due to a shift away from the weak memory market, notes the Nikkei Business Daily.

05/27/2008  May 27, 2008 - Taiwan electronics congolomerate Tatung reportedly plans to add a high-margin photovoltaics segment to its arsenal by year's end.

05/27/2008  May 27, 2008 - Worldwide semiconductor utilization held steady at around 90% in 1Q08, though a closer look at the numbers shows a surge of leading-edge capacity coming online at the start of the year, according to the latest quarterly statistics from Semiconductor International Capacity Statistics (SICAS).

05/27/2008  Barry Industries has introduced a line of semiconductor packaging featuring high temperature cofired ceramic (HTCC) technology for aerospace, RF/microwave, semiconductor, and optoelectronic devices.

05/27/2008  May 27, 2008 -- The Micromachined Diamond Device Initiative (MIDDI), led by UK researchers at Element Six Ltd in collaboration with the Institute of Photonics at The University of Strathclyde has concluded, and its "successful outcomes have already underpinned the formation of a new subsidiary by Element Six. Diamond Microwave Devices Ltd is aiming to develop the world's first commercial high frequency, high power diamond transistors," the partners say.

05/23/2008  by Katherine Derbyshire, contributing editor, Solid State Technology
May 23, 2008 - Controlling the interface between the metal gate and the hafnium-based dielectric has been one of the most difficult issues for high-k integration schemes. ASM now says it has ALD processes for both LaOx and AlOx, and that its Polygon platform and Pulsar process modules offer a reliable platform for sequential deposition of dielectric and cap layers in a gate-first process.

05/23/2008  by Fran

05/22/2008  by James Montgomery, News Editor, Solid State Technology
May 22, 2008 - A new report published in the journal Nature Nanotechnologies is raising alarms about apparent health risks associated with carbon nanotubes (CNT), similar to those seen with asbestos. But efforts are already underway to look more closely at potential issues, according to Walt Trybula, former SEMATECH immersion lithography guru and now at Texas State U., in an email exchange with WaferNEWS.

05/22/2008  by Ed Korczynski, senior technical editor, Solid State Technology
May 22, 2008 - Philips arguably pioneered the fab-lite business model 20 years ago, and was one of the earliest investors and customers of TSMC. Its chip spinoff NXP Semiconductor continues the relationship with R&D and arguably most-favored customer status at the world's leading foundry. Peter Yates, SVP at NXP, talked at this week's Confab about his company's strategy to navigate troubled-waters in many nimble ships.

05/22/2008  by Pete Singer, Editor-in-Chief, Solid State Technology
May 22, 2008 - For a 450mm wafer-size transition to happen, suppliers need to be convinced that their initial investments will translate into sales and won't eat into their 300mm business. But speaking at the Confab, SEMI standards VP John Ellis indicated that suppliers still think there's no benefit to them -- and he presented new data showing that the cost modeling is flawed, and that investments are better used elsewhere.

05/22/2008  by Debra Vogler, senior technical editor, Solid State Technology
May 22, 2008 - In the final ConFab 2008 session, amid the verbal volleying about whether 450mm manufacturing is needed and how would it be financed, ISMI's associate director Joe Draina reported on the progress being made in a number of areas, including the silicon wafer readiness project, wafer manufacturing infrastructure readiness, and a 450mm factory integration testbed.

05/21/2008  by Ed Korczynski, senior technical editor, Solid State Technology
May 21, 2008 - Masaaki Kinugawa, GM of Toshiba's Oita operations, discussed the tough challenges faced by fabs developing advanced processes today in his Confab talk, including increasing complexity of process and device technologies (and proportionally rising costs) -- and an ugly truth waiting around the corner at the 32nm node.

05/21/2008  by Ed Korczynski, senior technical editor, Solid State Technology
May 21, 2008 - While manufacturing of 3D ICs is today limited mostly to memory chip stacks and cell-phone camera modules, the next huge application seems to be the embedded memory in microprocessors. Subramanian Iyer, distinguished engineer and chief technologist of IBM's systems and technology group, explained the economic considerations behind 3D microprocessors at the ConFab in Las Vegas.

05/21/2008  by Bob Haavind, Editorial Director, Solid State Technology
May 21, 2008 - The future of lithography from the viewpoint of a major foundry was presented at ConFab by Chartered Semiconductor 's K.K. Lin. Concurrent advances across a trilogy of disciplines (physical and computational lithography, including OPC/RET, and DFM) will be required to keep scaling alive, he said, and litho tool contenders face some significant challenges -- but with key advantages too.

05/21/2008  by Ed Korczynski, Senior Technical Editor, Solid State Technology
May 21, 2008 - In a session discussing the economic implications of 3D ICs, Qualcomm VP Tom Gregorich noted that 3D and through-silicon vias promise better performance and potentially greater freedom for chipmakers to customize functionality -- but warned that cost of integration remains an issue, and the technology still has challenges to overcome.

05/21/2008  by Bob Haavind, Editorial Director, Solid State Technology
May 21, 2008 - Beyond today's stacked chips in a package may come higher performance 3D stacked ICs using through-silicon vias to interconnect layers, according to Sitaram Arkalgud, who spoke on the economic implications of 3D at the ConFab in Las Vegas.

05/21/2008  by Debra Vogler, senior technical editor, Solid State Technology
May 21, 2008 - This year's SPIE Advanced Lithography Conference saw glimmers of hope that EUV might be ready in time for 22nm hp. Speaking at the ConFab event, Kazuo Ushida, president of Nikon Precision Equipment Co., agreed that EUV was still the most promising solution for 22nm, and the only one that would keep the industry on track to meet cost/bit reductions needed to stay within historical guidelines.

05/21/2008  by Bob Haavind, Editorial Director, Solid State Technology
May 21, 2008 - There's a tough road ahead for lithography, with double patterning and complex computation as well as requirements for more litho-friendly design, explained ASML's Martin van den Brink, EVP of marketing & technology, speaking at the Next Generation Lithography session at The ConFab.

05/21/2008  by Debra Vogler, Senior Technical Editor, Solid State Technology
Having essentially crossed EUV off its 22nm plans, Intel is looking forward to getting it ready for the 16nm node -- but also is wary of addressing mask infrastructure needs as well, notes Janice Golda, the chipmaker's director of litho capital equipment development, in her presentation at the Confab.