Issue

Peter Singer, Editor-in-Chief

Jeff Desroches, ATMI, Inc. , Tempe, AZ USA

More than a hundred attendees gathered at a Suss MicroTec workshop at this year's SEMICON West ("3D Integration: Are we there yet?") to hear technical experts from around the globe to present updates on the status of 3D IC packaging.

Applied Materials debuted three systems at SEMICON West for next-generation DRAM chip manufacturing: the Centura DPN HDTM system to improve the gate insulator scaling, the Endura HAR Cobalt PVD system for high-aspect-ratio (HAR) contact structures, and the Endura Versa XLR W PVD system for reduced gate stack resistance.

Korean semiconductor giant Samsung Electronics has acquired Grandis, a maker of spin-transfer torque random access memory (STT-RAM), a flavor of magnetic random-access memory (MRAM).

Measuring CD Data show that a new generation SCD tool has good sensitivity and measurement repeatability for the 28mn HKMG ADI process. Y.H. Huang, et al., United Microelectronics Corporation, Tainan Science Park, Taiwan, C.H. Lin, KLA-Tencor Corp., Milpitas, CA

Double-patterning, spin-on silicon hard masks, and topcoat-less resists are enabling immersion lithography to meet todays's advanced technology node requirements. Mark Slezak, Brain Osborn, JSR Micro, Inc., Sunnyvale, CA.

EUV OPC flows can be optimized to meet stringent production turn-around-time and accuracy requirements of future nodes. Kevin Lucas, Jonathan Cobb, Johnny Yeap, Munhoe Do, Synopsys inc., Mountain View, CA, USA

Because no single method is delivering the needed reduction in LER, combining the benefits of an assist layer material during EUV lithography and a smoothing process after lithography might be the dual-prong solution that is needed. Carlton Washburn, Brewer Science, Inc., Rolla, MO USA