Issue

Intel has taken the wraps off its next chip technology, a 22nm process utilizing a new 3D trigate architecture promising faster speeds and big power savings, which will ramp to volume manufacturing later this year.

SST caught up with two presenters from this year's IITC conference in Dresden to get more details about their interconnect technology research.

Utilizing a high-productivity combinatorial technique, the best formulation and process window for post-via etch residue removers was determined. Rekha Rajaram, et al., Intermolecular Inc.; Barry Chen, et al.,ATMI, Inc., Danbury, CT and Round Rock, TX

As the global supply chain deals with wafer size transition, pre-competitive collaboration will continue to be the best path towards economic efficiency and industry rationality, and Standards play a major role. Jonathan Davis, SEMI, San Jose, CA.

Silicon interposers seem set to stay as a valid alternative implementation to full 3D-IC designs. Matthew Hogan, Mentor Graphics, Wilsonville, OR

Using complementary metrology techniques, the authors determined the thickness, composition and relaxation of SiGe and Si:C layers. Paul Ryan, et al., Jordan Valley Semiconductors, Durham, UK

The capabilities of advanced motion controllers enable OEMs to achieve high-performance requirements. Cameron Sheikholeslami, ACS Motion Control, Eden Prairie, MN