Tag Archives: Podcasts

wafer revenues decreaseWorldwide silicon wafer revenues declined by 12 percent in 2012 compared to 2011, according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry. Worldwide silicon wafer area shipments declined 0.1 percent in 2012 when compared to 2011 area shipments.

In 2012, silicon wafer area shipments totaled 9,031 million square inches (MSI), down from the 9,043 million square inches shipped during 2011. Revenues totaled $8.7 billion down from $9.9 billion posted in 2011.

"Much like semiconductor unit shipments, semiconductor silicon shipments started out the year strong; however, shipments weakened during the second half of the year,” said Byungseop Hong, chairman of SEMI SMG and director of Global Marketing at LG Siltron. “Despite challenges in the market, 300 mm volume shipments reached record levels.”

Read more: When will the semiconductor industry recover?

Annual Silicon* Industry Trends








Area Shipments (MSI)







Revenues ($B)







*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or "chips" are fabricated.

This report was compiled and released by the the Silicon Manufacturers Group, which acts as an independent special interest group within the SEMI association. The group’s purpose is to facilitate collective efforts on issues related to the silicon industry, including the development of market information and statistics about the silicon industry and the semiconductor market.

SEMI is the global industry association with over 2,000 members, serving the nano- and microelectronics manufacturing supply chains. 

PARC, a Xerox Company, is a pioneer in the development and commercialization of thin film transistors, circuits, and sensors. With a 40 year history of commercial innovation, PARC scientists have a deep knowledge of printing technology applied in domains such as displays, image sensors, and medical sensors, PARC’s technical expertise and facility support printed dielectrics, nanoparticle metals, organic, oxide, and silicon (amorphous, polycrystalline, printed nanowire) semiconductors.

Solid State Technology editor Pete Singer caught up with Janos Veres, area manager for printed electronics in the electronic materials and devices laboratory at PARC. Veres’ current interests are in combining disruptive material, process, and device technologies — for printed, flexible circuits; sensor and memory arrays; batteries and display devices — all with a focus on early commercialization opportunities. Janos has experience in components such as novel printed circuits, organic transistors, and printable semiconductors; applications such as OLEDs, displays, and RFID; as well as printing/coating technologies including electrophotography, flexography, and offset printing.

Before joining PARC, Veres was the CTO at PolyPhotonix, where he developed radically new process technologies for OLED devices. Prior to that, he worked at Eastman Kodak as their Program Manager of Printed Electronics, and was a Business Research Associate at Merck Chemicals (formerly Avecia) where he led several of the world’s first demonstrators built using novel electronic materials. Janos also set up unique pilot production lines for solution coating when he was responsible for Organic Photoreceptor development at Gestetner Byfleet. Dr. Veres holds a Ph.D. in Solid State Electronics from Imperial College in London and an MSc in Physical Electronics with distinction from Lviv Technical University in Ukraine.

Veres said described printed electronics as a relatively new field, with the “early years” being only 10-12 years ago. The focus is on materials that can be formulated as inks and deposited over large areas. This is quite useful for applications such as flexible displays, which was the original focus of the work, and more recently on smart cards and printed tags.  Recent progress has printed electronic transistors inching closer to those produced in polysilicon.

“We never believed that they might one day compete with amorphous silicon,” Veres notes. “That’s happened and probably 4-5 years ago, we saw that barrier broken. That means we can now take organic materials and achieve the same kind of performance that you see in displays. That progress is carrying on and at the lab level, you can build devices that are now performing better than what amorphous silicon offers. The progress will not stop there. We might see a significant improvement in mobilities at which point devices we build might be competing with polysilicon.”

This kind of progress could disrupt conventional microelectronics manufacturing. “A factory might look very different than the conventional microelectronics factory. It might look more like a printing press than a microelectronics fab,” Veres said.

Listen to the podcast interview with Veres below:


December 14, 2011 — Marc Heyns, fellow at research consortium imec, discusses the group’s work on chip fab materials beyond silicon, namely, germanium (Ge) and III-V, presented in paper 13.1, "Advancing CMOS beyond the silicon roadmap with germanium and III-V devices," at IEEE’s International Electron Devices Meeting (IEDM) this month.

imec has been working for several years on CMOS devices with high-mobility channel substrates. Initially imec used germanium for pMOS devices and III-V for nMOS devices. This had led to a whole new series of technologies, advancing "what you can do with CMOS beyond what you can do with silicon," Heyns says.

To implement these materials, the first step is to get them onto a 300mm or — in the future — 450mm silicon wafer for production. imec does this with aspect-ratio trapping, where Ge and III-V are regrown in trenches etched in the silicon. This yields a high-quality material, but is not without challenges. imec developed a double-step technique — etching a hole into the silicon, depositing Ge in it, and reflowing the Ge — to take care of anti-phase boundaries.

Another problem is materials passivation. imec tried ultra-thin Si layers, atomic layer deposition (ALD), and sulfur passivation, which Heyns says has yielded very good results (details in the podcast below). With ALD, Heyns says the precursor type is very important.

Also read: imec claims RRAM is smallest based on HfO2

imec also has been studying defects in the high-k layer. Sulfur passivation has been shown to lower the defect count in the high-k layer.

Then imec moved to making devices with these materials, and has been working on that for the last few years with good results, especially in SiGe. What’s next? Introducing strain. imec showed results at IEDM on how it introduced a Ge Fin to make a strain in germanium, as well as other methods.

Finally, Heyns says, once the FinFET is developed, you must look to making other novel devices, using nanowires and other advanced materials like gallium and arsenide. Heyns covers the use and benefits of these novel materials in the latter half of the podcast below.

When will Ge and III-V be seen commonly in chips? FinFETs are being introduced today, and as the industry goes to more advanced production nodes, these materials will be useful options. But, Heyns points out, this is all speculation for the moment.

Listen to Heyns’ full interview about the paper with contributor Debra Vogler below:


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More from IEDM:

Self-powered electronics: Achievements and challenges

imec presents MEMS energy harvester at IEDM

SuVolta’s DDC transistor technology @ IEDM


December 12, 2011 — Dennis Buss, a visiting scientist at the Massachusetts Institute of Technology (MIT) and consultant at Texas Instruments (TI), presented "Research in self-powered electronic systems (#10.4)" at IEEE’s International Electron Devices Meeting (IEDM) recently. He shares key results here.

Ultra-low-power systems operate in the range of a 100microWatt to a few milliVolts; one way to do this is to go to ultra-low voltage — around 0.5volt is typical. Medical monitoring/health monitoring electronics can become self-powered systems that would preclude the use of wires or batteries that need to be removed and replaced. Also, wireless sensor networks (WSN) can be used for such applications as smart buildings that do not require a permanent source of energy.

One key result in Buss’ IEDM paper was an MSP430 chip designed to operate below threshold: a VDD of around 0.3V. Compared to the commercial product, the chip achieved an energy/operation reduction of a factor of >10x. The chip had on-chip SRAM, on-chip DC/DC converter and a fair amount of logic.

Another result: an ultra-low-power medical DSP fabricated in a 130nm low-leakage process. This chip operated down to 05.V and surprisingly used accelerators. (e.g. FIR and FFT filters, and other algorithms commonly used in medical monitoring).

Two technical challenges exist. Random dopant fluctuation-induced local variations occur. When you operate at very low voltage, the variations in threshold have a huge — exponential — effect on logic timing. "There is no way to make a corner model that comprehends accurately the effect of local variations," says Buss. What his team shows is that, at low voltage, the 3-sigma stochastic delay resulting from local variations can exceed the corner delay, so it must be accurately understood. When we design chips today, Buss says, the predominant process variation is global — affecting all logic gates on the chip in the same way. For example, if the gate length is a little on the long side, it’s probably long for all the devices on a chip. "If we’re interested in the slow corner, we can generate a set of models that will comprehend the 3-sigma worst-case global delay for these variations. We don’t simulate the nominal models, we simulate to the worst-case slow and worst-case fast models. In the case of random dopant fluctuations, the transistors are not all affected in the same way; in fact, they are all different. When you combine the stochastic effects of different transistors, you have to add them in quadrature (like the square root of the sum of the squares) and this requires a new methodology for timing."

Another technical challenge is systems aspect. In some sense, we’ve demonstrated all the pieces — logic, AFE, A/D converter, ultra-low-power radios, energy management, switch capacitor DC/DC converters, and energy harvesting devices — but we still don’t have a system that responds to real needs, Buss says. Two system aspects are particularly demanding: the needs of computation vary dramatically (throughput) and unreliable energy sources that require battery back-up.

Listen to Buss discuss the paper:

See more paper summaries from IEEE’s IEDM:

November 29, 2011 — Applied Materials (AMAT) released a new film treatment called Applied Producer Onyx that reduces the power consumption in semiconductor chips while increasing mechanical strength. The product targets the challenges associated with 3D packaging applications and technologies such as copper pillar, 3D stacking, and lead-free soldering.

The solution decreases the dielectric constant value by up to 20%, thereby reducing chip power consumption. After treatment, the sidewalls of the film have been restored to the original bulk state. According to Russ Perry, global product manager, Dielectric Deposition Group, at Applied, the product is available for shipping and multiple pilot production lines are already running.

Figure 1. Illustration of how Onyx treatment strengthens the chip. *Normalized Young’s Modulus. SOURCE: Applied Materials

Perry discussed the treatment that drives carbon and silicon into the porous dielectric film to reinforce the insulating material at the atomic level (Fig. 1) in a podcast interview with SST.  
In the podcast, Perry explained how multiple applications of the treatment enable scaling as the treatment is applied to the interconnect structure after etch and after CMP (Fig. 2). The process of integrating low-k films into the interconnect requires that they be subjected to many harsh chemistries and processes noted Perry.

November 28, 2011 — AKHAN Technologies has developed a shallow n-type diamond material over silicon that has characteristics such as a shallow ionization energy (250meV), high carrier mobility (>1000cm2/Vs in nanocrystalline diamond thin films), and no graphitic phases. The latter is important because graphitic films translate to low mobility (because of scattering sites). The material also provides for a 900A/mm2 current density at +2V forward bias in low voltage high current diode device applications.

In a detailed discussion about the technology in a podcast interview with ElectroIQ.com (below), Adam Khan, president of AKHAN Technologies, said that the bottleneck in development of diamond films has always been the fabrication of n-type diamond,

September 27, 2011 — Ziptronix announced just before SEMICON Taiwan that its low-temperature direct oxide bonding technology — Zibond, used for constructing backside-illuminated (BSI) structures in image sensors — was licensed by Sony. In a podcast interview with ElectroIQ.com, Ziptronix president & CEO, Daniel Donabedian, and company CTO, Paul Enquist, discussed both the wafer bonding technology and what the Sony deal means in the podcast below.


Because adhesives do not have high bonding energy at low temperatures, the result is high distortion, therefore, these materials are not usable for scaling smaller pixel sizes, said Enquist. Conversely, the company

September 20, 2011 — D2S announced a mask-wafer double simulation accelerated workstation, TrueMask DS, for R&D exploration, bit-cell design, hot-spot analysis and mask defect categorization at the SPIE Photomask Technology conference (i.e., BACUS, 9/19-9/22/11, Monterey, CA).

Mask shops and wafer fabs can use the new tool for qualifying and optimizing 20nm node and below semiconductor designs. At these nodes, the assist features on the photomasks are smaller than 80nm and can no longer be reliably produced. The purpose of the new simulation tool is to enable the efficient exploration of the various trade-offs including complex optical proximity correction (OPC), inverse lithography technology (ILT), source mask optimization (SMO), and the cost and turnaround time of masks for critical circuits.

"It’s an exploration platform that allows designers to explore shapes that can be efficiently written on mask writers and is also best for wafer yield," said Aki Fujimura, CEO, D2S (and managing company sponsor of the eBeam Initiative). "In 20nm and below nodes, unlike previous nodes, mask shapes, mask write times, and wafer yields are becoming trade-offs against each other." The new platform allows exploration of the trade-offs.

Figure 1. Sub-80nm discontinuity in semiconductor manufacturing.

Fujimura explains in the podcast interview below that accuracy inherent in mask writers is impacted at 20nm and below. "For mask writing, which is based on 50keV e-beams, discontinuity occurs below 80nm sizes," he said (Fig. 1). He further notes that above 80nm mask dimensions, one could count on the shot size being faithfully reproduced on the mask surface. Going below 80nm, one is no longer is able to get the same shape nor will the size be reproduced every time, nor will the printed feature be reliable in size, he added. Therefore, "lithography simulation is no longer enough." Also, the lithography simulation methodology the industry has been for over 10 years — known as the bundled model — counts on a mask being accurate enough, which as just explained, is no longer true. By using a separated mask model instead of the typical bundled model, the new workstation modeling includes the mask effects. An independent validation of the mask-wafer double simulation approach is shown in the table.

Table. Independent validation of mask-wafer double simulation approach. In this example, the D2S MB-MDP of ILT mask shapes is the best choice for better wafer quality (lower PV band) and faster mask write time (lower shot count). Courtesy Globalfoundries, BACUS 2011 paper #8166-110, Gek Soon Chua, et al.

Conventional mask shapes

ILT Manhattanized mask shapes D2S MB-MDP of ILT mask shapes Ideal OPC data
Worst PV band 2.18X 2.15X 1.75X 1.64X
Shot count increase 1X 5X 3X 8

Fujimura also noted that the new platform is important for cost reduction (Fig.2). A typical cycle for doing mask simulation followed by lithography simulation might be hours of work. Because the new system uses a graphics processing unit (GPU) accelerator, the amount of work will be reduced to tens of seconds. Being able to get the feedback on the impact of changing mask shapes in such a short period of time enables substantial time savings on the trade-off evaluation.

Figure 2. Bending the mask cost curve. SOURCE: IBS Inc.

Other features of the platform include: 0.1nm resolution mask simulation up to 300 x 300

September 20, 2011 – Bill McClean, president of IC Insights, issued his fall forecast update in Sunnyvale, CA (9/15). He expects electronic system sales (in US dollars) to grow by 6% in 2011 and 7% in 2012. He also projects that a slightly above average 2012 worldwide GDP growth should drive a 10% growth in the IC market. Long-term, McClean believes the 9%-10% CAGR for IC unit shipments will remain intact. Additionally, ASPs are forecast to stabilize in the long term, leading to IC market CAGRs of 8%-9%. Figures 1 and 2 provide details of the IC unit volume shipment trend and the various IC market growth rate scenarios, respectively. McClean forecasts the US GDP growth in 2H11 to increase by 2.7%; for 2012, 2.8% growth is expected. Long-term, the US GDP is expected to grow by 3%-3.5%.

Figure 1: 2000-2011 quarterly IC unit volume shipment trends. (Source: WSTS, IC Insights)

Figure 2: Quarterly 2011 IC market ($) growth rate scenarios. (Source: IC Insights)

In an interview with SST, McClean discussed the impact that the stimulus funding provided by various world governments has had on worldwide GDP growth vs. what that growth might have been if stimulus funding had not taken place (Figure 3).

From 2009 through early 2011, about $2T was put into the world economy, but the withdrawal of stimulus funding and even some governments implementing austerity programs, has resulted in a shaky economy, impacting worldwide GDP growth. "The stimulus helped us get through that period…going forward, the worldwide economy will stabilize, but right now, there are a lot of issues that make it uncertain," said McClean.

Figure 3: 2006-2011F worldwide GDP growth with and without stimulus. (Source: IC Insights)

McClean pointed out that China was one of the first countries to implement stimulus funding, beginning in late 2008. As a result, that country’s economy grew in 2009 and has come through the downturn, picking up steam in 2010, he said. China is the largest consumer of PCs, cell phones, autos, and digital TVs, which is of great importance to the semiconductor industry because of the semiconductor content in those products.

Projecting even further ahead, McClean projects soft single-digit growth for the industry in 2013 because most of the stimulus or other measures that might still be in place in 2012 (an election year in the US) will be taken out of the equation by 2013.

For more forecast details, listen to the podcast interview, which includes McClean discussing how unique events are causing an atypical recovery.