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November 29, 2012 – Despite graphene’s promise as a material in future electronics with excellent properties in almost all applications, it still faces difficulties in market acceptance, according to a report from IDTechEx.

The firm calculates a $100M market for graphene in 2018, as the material seems to be reaching the peak of its hype cycle: prototypes and first-generation products have been launched; a mushrooming of start-up formations has occurred; and the industry has seen a flurry of seed and early-stage funding. Several companies are already within the second or third round of financing, and the second generation of products are being launched with more realistic assessment of the near- to medium-term market opportunity, according to Khasha Ghaffarzadeh, technology analyst at IDTechEx, and co-author of the report "Graphene: Analysis of Technology, Markets and Players 2013-2018."

Figure 1: The hype cycle of graphene. Graphene is hyped but it is moving past the peak of inflated expectations.
(Source: IDTechEx)

Depending on the number of layers, purity, oxygen content, crystallinity, and form (powder or sheet), the quality of the graphene can vary, and each can be placed on a quasi-empirical chart, in which the limiting cases are graphite, graphite oxide, graphene oxide, and graphene.

Figure 2: The many different graphene types can be categorized between the limiting cases of graphene oxide, graphene, graphite oxide, and graphite. The properties will different depending on where the graphene sits within this space.
(Source: IDTechEx)

Different manufacturing techniques are used, including micro-cleavage, chemical vapor deposition, liquid-phase exfoliation, and oxidization-reduction and plasma, with a trade-off between cost and scalability vs. graphene quality, says IDTechEx. Certain techniques may be better suited for high-volume applications with relaxed performance requirements, while others serve applications demanding high performance levels.

In many cases, the main strategy for graphene acceptance is as a replacement for existing materials in products such as carbon black, carbon fiber, graphite, carbon nanotubes, silver nanowires, ITO, silver flakes, copper nanoparticles, aluminum, silicon, GaAs, and ZnO.

Figure 3: Scalability, cost and graphene quality trends for different manufacturing techniques. (Source: IDTechEx)

The industry is now gearing up to move beyond research activities, and other applications are being developed, including RFID, smart packaging, supercapacitors, composites, ITO replacement, sensors, logic, and memory. The largest near-term market opportunity for graphene beyond R&D is in composites and energy storage applications, IDTechEx says. Graphene’s adoption in transparent conduction applications will be limited because it falls short both on cost and performance compared to other options, the firm says. Similarly graphene won’t find easy inroads into transistors due to its lack of bandgap and the high level of standards set by existing materials

November 28, 2012 – NPD DisplaySearch analyst Paul Gagnon took the pulse of consumer shoppers on Black Friday and came away with three observations: bargains are a priority, consumers want bigger upgrades, and Walmart flexed its muscles. He bases them on what apparently was firsthand experience standing in line like everyone else, plus "reports from colleagues in the industry."

— Consumers love bargains… Customers seemed to have their Black Friday TV-deal priorities in order thusly: price, size, brand, and little interest in any other feature. Gagnon noted Emerson 32-in. LCD TVs vanished at a $148 price point, but same-sized Samsung versions stood stacked on the floor largely untouched later on Friday even at $100 off. At a Best Buy later in the day he reports customers sought out a "shockingly low" priced ($179) Toshiba 40-in. TV, but upon learning they were sold out they resigned to next year’s Black Friday rather than seek a replacement. That suggests the motivation was far more on finding a good deal vs. really wanting a new TV — "which should be a wake-up call to the to the industry to not focus so much on promoting shocking prices to drive traffic," he writes.

— …but not "step-up" features. At the same time, Gagnon noted that there was little "chatter" and activity surrounding "step-up models" of TVs featuring improvements such as Smart TV, 3D, or LED technology. Over 90% of Chinese LCD TV shipments were LED backlit in 3Q12, but North America isn’t even at 50% yet and ranks near last in the world in terms of unit shipment share, he points out. " Do US consumers understand the feature, and just not care? Are retailers not doing an effective job of educating customers about the technology? Are the prices too high? Probably some combination of all of these factors is at play."

— Confirmed: Bigger is believed better. While consumers flocked to promotions of sub-$200 32-in. TVs, a lot of them also sought out bigger models (≥40-in.). Gagnon lists a number of notable Black Friday promotions this year for bigger-sized panels, in some cases with 50-in. models at the same price point as last year’s 40-in. models; some of that is just natural price erosion, he acknowledges. But consumers are also eager to replace 32-in. TVs with significantly bigger models — and that’s particularly good news for panel makers who sell by the square meter.

— The power of Walmart compels them! Even in the face of a labor dispute, Walmart heavily promoted its Black Friday deals and it seems to have paid off as waves of promotions kept shopper traffic spread out and lines flowing smoothly, Gagnon writes. "It seemed Walmart was more effective at pulling shoppers looking for TVs this Black Friday, reporting today that it sold more than 1.3 million televisions since 8PM on Thursday," he notes, showing a photo of shoppers "Starbucks and Smartphones in hand" at 5am lined up for a $299 Panasonic 50-in plasma TV. He also notes that Funai "moved a lot of boxes during Black Friday" — the firm climbed to #1 in LCD TV shipments in 3Q12 and nearly 20% share, with many of those units destined for Walmart’s Black Friday push, with whom it has partnered for years, he notes.

November 27, 2012 – LEDs have struggled to gain a foothold in the marketplace for indoor lighting applications, but technology improvements and supportive legislation are gathering momentum to help push LED adoption for residential buildings — the largest lighting application sector.

Global sales of LEDs for lighting applications totaled $3.57B in 2011, and should surge to $23.24B by 2018, calculates Frost & Sullivan. Behind that swell is "legislation that will essentially phase out incandescent lighting and other inefficient lighting technologies," as well as declining prices for LEDs that will boost demand and penetration of LED technology across multiple lighting applications, explains Frost & Sullivan industry analyst Hammam Ahmed.

The European Union has been an early adopter of legislation supporting a shift away from both manufacturing and sales of incandescent lighting; this legislation, though coming in multiple phases, has been echoed with similar policies sprouting up and implemented in various other countries (US, Switzerland, Canada, Australia). In Asia, Japan, China, Taiwan, and Korea are adopting LED-supportive legislation including financial incentives for both consumers and manufacturers.

Total global LED lighting market (2011), percent LED revenue by region (left)
and application (right). All figures are rounded. (Source: Frost & Sullivan)

Key factors limiting LED penetration into general lighting applications are pricing and technology improvements, but sharp and continued price declines should speed up the tipping point of price parity with other lighting technologies by the end of this decade, Frost & Sullivan says.

On the other side of that coin, manufacturers continue to improve lumens/dollar by pushing R&D and improvements in brightness, design, and quality of components, Hammam notes — though he admits "it remains to be seen how customers receive these new product developments." Additionally, those same relentless price declines are forcing manufacturers to come up with sustainable, long-term growth plans. "Participants from Eastern Asia, who have the ability to compete on prices, need to address quality issues to expand into the more developed markets of North America and Europe," he noted, while current market leaders "need to offer high-quality products and explore avenues for reducing cost of production."

Many of the world’s 3D IC elite met last week at the 2nd annual Georgia Tech 2.5D Interposer Conference which focused on the technology and performance of silicon and glass interposers.

Matt Nowak of Qualcomm, long a 3D advocate, reported that Qualcomm has now built "thousands of parts" and does not see anything stopping high-volume manufacturing (HVM) except cost. Nowak indicates that Qualcomm will require a price of ~ $2 for a 200mm2 silicon interposer. The former is just out of the reach of those proposing "coarse" interposer fabrication, and the latter is significantly out of the pricing structure for dual damascene foundry-based fine interposers

Nagesh Vordharalli of Altera quoted an IMEC study which shows that the sweet spot for maximum bandwidth will come from interposers with RDL lines/spaces ~ 3

November 16, 2012 – The latest monthly numbers are in for semiconductor manufacturing equipment demand, and they’re not pretty: lows in both orders and sales not seen since the last major downcycle three years ago, and the short-term comparisons continue to widen.

North America-based manufacturers of semiconductor manufacturing equipment reported bookings (orders) of just $743.2M in October, down -18% from September and roughly -20% from a year ago. Billings (sales) came in at $986.5M, off by -15% M/M and nearly -22% Y/Y. (Both are three-month moving averages.) SEMI also revised downward its September data: Bookings lowered to $912.8M (they had been $952.9M), and billings down to $1164.4M (vs. $1177.4M). The book-to-bill (B:B) came in at an anemic 0.75, meaning that $75 worth of orders came in for every $100 shipped out. (A B:B above 1.0 would indicate a good sign of more business coming in; a number below 1.0 means the opposite, and a number substantially below 1.0 and sinking for a while, well…)

Here are some chilling metrics to illustrate just how sour the market for chip tools has become as we head to the finish line of 2012. (All data is compiled from SEMI’s historical tallies dating from Jan. 1991)

  • Bookings are at their lowest point since October 2009. Billings haven’t been this low since January 2010. Since peaking in May, equipment bookings have been slashed by half (-54%) and sales are off by more than a third (-36%).

  • For the ten months through October, equipment orders were tracking down -8.5% from the same period in 2011 to $12.6B, and sales were down -15.7% at $13.3B.

  • Bookings have declined by double-digits for five consecutive months (-11% to -18%), which hasn’t happened since the grand old days of December 2000-April 2001. Except for a single month of mathematically zero growth (April), bookings have declined Y/Y for 16 out of the past 17 months. (This might say more about the industry’s reliably brutal cyclicality than current malaise; May 2011 was the end of a 19-month period in the black, which was preceded by a 29-month trip through the doldrums.)

  • The B:B ratio has been in freefall since April when it was well above the parity level (1.12) — that’s six straight months of decline, which according to SEMI’s data hasn’t happened since late 2010. (We’ve had several five-month slides in the past two years.)

Denny McGuirk, president and CEO of SEMI, labeled the environment for semiconductor industry investments as "muted" entering the final quarter of 2012, though he stated that "investments in leading-edge technologies will continue to drive spending in the near-term." The outlook for 2013 will clear up shortly as chipmakers crystallize their 2013 capex plans, he added. (Note that with about six weeks remaining, any lack of clarity into 2013 planning doesn’t exactly inspire confidence.)

SEMI will present its updated consensus forecast in conjunction with SEMICON Japan on Tuesday Dec 4 (technically it’ll be 11am local time, which is the wee hours late Monday/early Tuesday morning here in the US). One can reasonably expect some drastically different numbers from its current official forecast, issued at SEMICON West in July, which predicted an overall -2.6% decline for the year in global frontend + backend equipment. Hopefully there will be some improved clarity in these coming weeks.

by Paul Feeney, Axus Technology

The International Conference on Planarization/CMP Technology (ICPT) was held Oct 15-17 in Grenoble in southern France. This international event is the world’s largest conference covering chemical mechanical planarization (CMP) and related topics, over a 2.5 day period. Over time, the CMP users groups from around the world that come together to form this event are acting increasingly as one body, and the quality of the information has risen.

ICPT oral and poster presentations can be grouped into a handful of major themes:

  • Integration of new device structures, and the CMP processes and slurries needed to support them;
  • Advances in equipment and in endpoint and control methods;
  • Advanced copper interconnects, and the extension of this to 3D and MEMS technologies;
  • Consumables, with a keen focus on mechanistic understanding; and
  • Alternative planarization methods and the application of CMP to new materials.

CMP and new device structures

Leading off the discussion of the application of CMP for new devices was a plenary talk by Daniel-Camille Bensahel from CEA-Leti. He stressed the parallel paths that exist today for 14nm technology and beyond between fully depleted silicon-on-insulator (FD-SOI) and multi-gate or FinFET devices. As technology goes beyond these two architectures, the future will lie in making the transition from silicon channels to some combination of germanium, nanowires, and graphene. All of this bolsters the effect we have already seen putting more focus on the use of planarization in creating devices rather than solely in making interconnects.

Invited talks from IMEC and GlobalFoundries nicely covered the complexity of CMP steps now being employed to fabricate leading-edge devices. In years past, shallow trench isolation (STI) CMP was the only set of CMP steps in the front-end-of-line (FEOL) process flow. Now, many new CMP applications are being added and each calls for multiple process steps. The special dielectric fill for FinFET’s creates the need for steps very similar to those used for STI, but drives the need for stopping on the extremely small nitride features that cover the fins. The ILD 0 or pre-metal dielectric or poly-open-polish (POP) CMP that exposes the tops of the dummy silicon for metal gates also has similarities to these two. The metal gate CMP that follows was discussed as being implemented with either aluminum (Al) or tungsten (W) as the bulk material. There was also coverage of techniques similar to those of replacement gates for formation of replacement channel materials made from germanium (Ge), indium phosphide (InP), or indium gallium arsenide (InGaAs).

Papers that delved into a portion of these new CMP applications pointed out some of the unique challenges. Catherine Euvrard from CEA-Leti pointed out that POP CMP must not only retain tight control over remaining film thickness, but must do so while simultaneous removing nitride and oxide materials deposited at slightly different heights due to the non-planarity remaining after STI. Another difficulty is that the pattern removal rates of nitride and oxide do not follow what might be expected from blanket rates on each of the films when polished separately. Patrick Ong from IMEC went into the development of a 2-step process for replacement Ge channels. The epitaxial overgrowth of Ge is polished back to oxide and then buffed to produce roughness in the range of 2Å. Ulrich Kuenzelmann from TU Dresden showed results from their implementation of Al CMP. These papers were all geared towards advanced logic. Hynix also contributed with talks on new ceria particles for lower defectivity in STI and CMP for buried gates or wordlines for advanced memory. For buried wordline CMP, the bulk metal includes W and must stop on a nitride layer.

CMP equipment, materials, and methods

On the second theme of equipment, a variety of new hardware and control options were highlighted. Len Borucki from Araca pointed out the slurry flow reduction or oxide removal rate gain with a “slurry injector” apparatus. A second talk from Araca described similarities and differences seen in doing CMP of 300mm vs. 450mm wafers. Polishing of 450mm wafers can generate temperatures a few &degC higher, which is likely to have a noticeable effect on temperature sensitive steps such as Cu CMP. Pusan National University and G&P Technology showed that they were able to achieve a radial non-uniformity (NU) of 3% at 2mm edge exclusion with their wafer carrier that contains an “edge profile ring” between the wafer and the retaining ring.

A number of papers described ideas for metrology. Applied Materials and a few customers covered the application of white light illumination for endpoint control across a range of FEOL CMP applications. Improved results were presented for STI thickness, POP thickness with closed loop control of both profile and polishing time, as well as establishment of endpoint control of a process for replacement SiGe channels. Silvio Del Monaco from STMicroelectronics displayed a technique for in-situ measurement of pad groove depth that could be used in characterizing the pad cutting rate of conditioner disks. Florent Dettoni from CEA-Leti described a technique they developed to stitch together interferometric scans to create accurate maps of topography both for whole dies as well as across wafers. Those results were correlated to profilometer scan data, but measurements can be done much quicker. Chandar Palamadai laid out the process that KLA-Tencor has created for quantification of scratching through analysis of blanket wafer haze maps.

CMP and Cu interconnects

The next major theme regarding copper (Cu) included advanced interconnects both for wafers as well as quite a bit on 3D interconnects. Olivier Robin from STMicroelectronics taught us how sheet resistance control mean and variation can be improved by switching to a barrier process with higher selectivity between the dual hardmask and the dense ultralow-k material just below them. Jie Lin from Fujimi described work to develop a slurry for Cu that can get good planarization efficiency despite being used with a pad of moderate hardness. Contributors from Fudan University and from DuPont covered work studying the corrosion and removal rate behavior of the cobalt and molybdenum materials being investigated as part of new barrier material stacks.

ICPT has given increased attention to 3D interconnects and the formation of through-silicon-vias (TSVs) over the last few years. This year included an overview by Viorel Balan from CEA-Leti of some of the issues that need to be addressed in order to do Cu-to-Cu direct bonding. A key to success was identifying and improving topography across several length scales. Both he and Benjamin Steible from ISIT gave evidence that new generations of abrasive-free slurries provide a nice advantage in controlling the dishing of especially larger structures. Jinhai Xu talked about his work at SMIC demonstrating that rings of corrosion at the edges of vias can be seen as a recessed area when there is still about a micron of bulk copper left on the wafer. Rob Rhoades showed two different processes for the TSV nail expose process depending on whether it is an active wafer or an interposer. Catharina Rudolph from Fraunhofer presented a story showing that the combination of high-density TSVs and a higher-temperature anneal actually leads to enough stress that the wafer can explode.

CMP consumables

Over time, consumables for CMP have become more specialized to fit the needs of individual process steps for each application. Consumable topics have always been a popular topic at ICPT and this year was no exception. In the area of pad conditioning, there were two topics that received the most attention. One was applying conditioning techniques to the double-sided polishers used in wafer polishing. Jorn Kanzow from Peter Wolters reported that conditioning provided edge control for the double-sided polishing that is now necessary for achieving flatness for 300mm wafers. The second was the study of pad debris that is generated during pad conditioning and how it leads to an increase in scratch defects. Scratching was shown to be best when doing excitu conditioning or when vacuuming the debris off the pad. A relatively recent style of conditioner uses diamond coating over an engineered surface. 3M presented a summary of their efforts to do that utilizing some of their micro-replication methods.

Keiichi Kimura from Kyushu Institute of Technology presented some very exciting concepts surrounding research done to identify individual removal events during CMP. Through the use of evanescent light, where laser light is bounced off a prism surface, individual slurry particles that come in contact with the prism are illuminated. Their findings put forth the idea that pad asperities and the fluid around them cause adhered particles to be pulled off the polished surface. This happens at velocities much slower than what the pad achieves across the wafer — which rebukes a standard theory that removal is from 3-body contact of a pad asperity pushing a slurry particle into the film being polished. Greg Gaudet from Cabot Microelectronics provided an argument for removal rate with softer pads being driven more by the number of contact points between the pad and wafer rather than the total area of contact. This data seems to back up the concepts presented by Kimura.

For slurries, Intel together with Bradley University and MIT had a few talks outlining the outcome of fundamental studies. Alex Tregub made the point that the characterization of particle size is often overly simplified into a mono-modal distribution. Those tests also often use highly diluted slurry that may not be behaving as it would in its normal state. Mansour Moinpour went over results showing how desorption of additives from particle surfaces can be characterized. Joy Johnson from MIT reviewed a collection of literature surrounding particle agglomeration and added some work showing the role additives can play in agglomerate formation. Along somewhat similar lines, Pall got together with Lewis University to characterize the interaction that slurry particles have with the fibers inside of slurry filters, which may lead someday to the use of novel fibers.

New and improved CMP materials, processes

The remaining major theme is the extension of CMP to new materials and other types of removal processes besides CMP that are also being improved upon. Talks covered new materials such as carbon nanotubes with titanium (Ti) for vias, potassium dihydrogen phosphate (KDP) crystals for optics, GST for phase change memory, SiC for hardmask removal, and Ti and Ti02 for biomedical applications. It turns out that lowering surface roughness of Ti02 improves the biocompatibility of surgically implanted materials.

Though there does not appear to be any technology that is threatening the continued adoption of CMP for many applications, there are also other types of processes that have their place. Hyuk-Min Kim from Hanyang University taught us how lapping results could be improved by switching to a fixed abrasive system. Chuljin Park from KIIT showed a multistep process where diamond mechanical polishing was useful followed by CMP for sapphire substrates. Paul Feeney from Axus Technology demonstrated that improvements in grinding technology can make the CMP of Si after grinding much easier and produce better results. Grinding of Si can be done two-orders-of-magnitude faster than CMP and with within wafer non-uniformity unheard of in CMP. Adding CMP afterwards then produces the best possible surface.

Overall, the technical content of this event was very good. Clearly a lot of energy is being applied around the world to make advances on a wide variety of planarization applications. A high bar has been set for next year’s ICPT in Taiwan!

Paul Feeney ([email protected]) is director of process technology at polishing and thinning company Axus Technology. He started his involvement in CMP at IBM in 1989, holding both process and equipment responsibilities there, including doing pioneering module process and integration work on copper and barrier CMP for the world’s first commercial copper chips. He spent many years at Cabot Microelectronics; as a CMP Fellow there, he led development of a wide range of materials for leading-edge CMP applications. He is also a co-leader for planarization topics for the ITRS.

by Paula Doe, SEMI Emerging Markets

Materials experts from across the supply chain who gathered at the Strategic Materials Conference 2012 in San Jose in October discussed key materials needs for micromanufacturing outside the CMOS mainstream, as OLEDs and GaN-on-silicon power semiconductors come to market, and alternatives like graphene, CNTs, and self-assembling polymers get closer to commercial application.

Large OLED displays are coming, and counting on materials breakthroughs

OLED adoption in larger displays is surely coming, driven by business necessity, argued James Dietz of Plextronics. Most of the major display makers are seeing operating losses from their LCD business, and OLEDs look like the best option for higher-value, differentiated products to improve margins. The OLED displays look significantly better, and they may potentially open new markets for lighter or flexible or more rugged displays, or for dual-view products. OLEDs’ ultra-fast switching speeds could allow different viewers with different glasses to watch different programs at the same time on the same screen. Moreover, though OLEDs are more expensive now, the variable costs for a 55-in. OLED TV made on an 8G line will be quite comparable to those for a similar LCD. And the OLED costs have far more potential to come down further, by developments like simplifying the layer stack and introducing wet processes that use lower cost equipment with higher utilization of the expensive materials.

But the nature of the market also means new challenges for suppliers. Anxious to avoid another experience like the commoditization of the LCD sector, display makers intend to keep their processes and complex OLEDs materials stacks to themselves this time, which makes process integration of different materials and equipment difficult. The device makers are investing in developing their own materials, making exclusive contracts with equipment and materials suppliers, and doing their own process integration. Integration is also being driven by some materials suppliers like DuPont Displays. But the familiar semiconductor model of the material and tool supplier working together to deliver a process to the customer is not the rule. "We see a gradual transition from all vapor to more solution layers," says Dietz. "OLEDs will enter the TV market in the next three years, and will have solution process steps by 2015."

The 55-in. OLED TVs announced for 2012 now look more likely to come out in only very small volume — a few thousand units in 2012 — and initial prices of ~$9000 will limit sales. But OLED TVs will start to see real growth by 2014-2015, helping to push OLED displays to a $25 billion market by 2017, reports Jennifer Colegrove, VP of emerging display technology at NPD DisplaySearch. She says ten new AMOLED fabs are planned to be built or updated in the next three years. OLED materials, now about a ~$350 million market (include the OLED organic materials but not substrates), should grow at close to the same 40% CAGR of the overall market, to reach $1-2 billion in 2014. But breakthroughs are still needed in oxide and amorphous silicon backplanes, color patterning technology, lifetime of blue materials, encapsulation materials, reduction of materials usage, and of course integration, uniformity and yields of all these things.

OLED display revenues will grow to about $35B in 2019, up from $4B in 2011, with CAGR ~40%. (Source: NPD DisplaySearch, Q3’12 Quarterly OLED Shipment and Forecast Report)

Solution processing is critically important to bringing down the cost of large screen OLEDs, argued John Richard, president, DuPont Displays, as the current production methods which rely on thermal evaporation with fine metal masks are proving costly to scale to 8G substrates. "We developed an alternative process using soluable materials to bring down cost," he notes. Wet processes reduce capital needs and cut material waste to reduce costs significantly, but still need ever better lifetimes and efficiencies of the OLED materials, particularly for blue. A major Asian display maker has licensed the DuPont technology, and plans to scale it up to 8G. The process uses largely pre-existing tools to slot coat the hole injection and transport layers, and pattern the surface with wetting and non-wetting lanes, before nozzle printing stripes of red, green and blue emitters using custom tool developed with Dai Nippon Screen.

The rest of the stack — the electron transfer layer, the electron injection layer, and the metal cathode — is then deposited by thermal evaporation. Richard says coating and printing processes can use significantly less material than vapor deposition, as it avoids losses in the chamber, on the mask, and during alignment and idling. DuPont reports printed blue emitter lifetime is up to 30,000 hours — or 8 hours a day of video for 15 years — before degrading to half brightness. Next issues include optimizing the cost of synthesis and starting materials, and reducing operating voltage for better device efficiency.

Graphene and carbon nanotubes get closer to commercial applications

Next-generation energy storage presents materials opportunities as well. One key enabler for improving both supercapacitors and batteries could be graphene, especially with better sources for consistent quality material at reasonable cost. Bor Jang, CEO of Angstron Materials, reported that his company has engaged a contract manufacturer in Asia to start volume production of as much as 30 tons of graphene next year, using Angstron’s technology that claims good control of structure and properties. "That will bring down costs by an order of magnitude," says Jang. First application will likely be performance enhancers for lithium-ion battery electrode materials, and then for improved electrodes for supercapacitors. Angstron has announced demonstration of a graphene-based supercapacitor with energy density comparable to a nickel hydride battery.

"We think supercapacitors is a market to invest in," said Chris Erickson, general partner at Pangaea Ventures, a somewhat unusual venture fund that invests particularly in materials and green technologies. "We think it will reach $1 billion in the near future." Erickson is also enthusiastic about the potential for dynamic window glazing using vapor-deposited coatings and ITO to adjust to control the shading on windows, for dramatic energy savings of up to 30% in energy consumption in a building, according to NREL — and buildings reportedly use 49% of total energy in the US.

Nantero reported major progress from its long effort in controlled processing and performance for its carbon nanotube thin film, targeting low-cost, low-power non-volatile memory. CTO and co-founder Thomas Reuckes said the company is now lithographically patterning films of its spin-coated aqueous solution of carbon nanotubes, as roughness, adhesion and defectivity are now suitable for semiconductor processing. Metal impurities are down to <1ppb in liquid form, wafer-level trace metals to <1E11 atoms/cm2 . Reuckes reported production of working and yielding 4Mbit CNT memory arrays, and showed results of reliability data. The company just announced a joint development program with imec to manufacture, test, and characterize the CNT memory arrays in imec’s facilities for applications in next generation <20nm memories.

GaN for power semiconductors needs higher purities than LED market

Power semiconductors made on GaN on silicon are being released to the market now, and, given time, could potentially address some 90% of the what IMS Research projects will be a $25 billion (silicon-based) power semiconductor market for MOSFET and IBGTs by 2016, suggested Tim McDonald, VP for emerging technologies at International Rectifier Corp. GaN theoretically offers much better specific on-resistance to breakdown voltage tradeoff than Si or SiC. The key to wide adoption is for GaN on Si based solutions to achieve 2-4× performance/cost compared to silicon.

To achieve the necessary low costs, IR uses compositionally graded layers of AlyGaxN grown on the silicon to ease the thermal and lattice mismatch of the GaN film to the silicon wafer. IR claims 80% yields, with warp and bow controlled enough to run on a standard 150mm CMOS line. GaN on silicon is moving more quickly to market for power semiconductors than for LEDs, as it brings better performance, not just potentially lower prices. It also helps that threading defects do not have the same impact on performance–plus IR has been developing the technology for six or seven years already.

The power market needs higher purity materials and cleaner tools for better yields on its larger die, compared to the LED market. It also prefers larger diameter wafers for lower costs. Demand for gas sources and MOCVD tools should scale with volume, and the tools need to be optimized for larger wafers and become more automated, with perhaps some 2,000-3,000 tools needed for the whole market over the next two decades. Packaging may move from wire bonding to soldered or sintered contacts, and will adopt other means of reducing stray packaging-related inductance and resistance.

The LED market will see only a few more years of significant growth, argued Jamie Fox, lighting and LEDs manager for IMS Research-IHS. Revenues from displays including TVs are leveling off from their fast ramp, as the markets mature, and as LEDs get both brighter and cheaper, driving down both units needed and cost per unit. The LED lighting market will continue its fast climb to near ~$6 billion over the next several years, but then as more lamp sockets are replaced by the longer lasting LEDs (and CFLs), there will be less need for replacements, and the market will slow. Slower adoption near term, however, would mean less saturation later.

Cree’s Mike Watson, senior director of marketing and product applications, countered by pointing out the potential for innovation that solid state technology brings to lighting, noting how digital technology has transformed markets like telephones and cameras into new industries for digital communications and digital imaging. "Semiconductor technology keeps changing industries by innovation," he noted. "Why do we keep thinking of it as just replacement?

Directed self-assembly for higher resolution lines and holes

Another of the more innovative materials alternatives on the CMOS side is directed self-assembly for next-generation patterning, which seems to be making rapid progress. AZ Electronic Materials CTO Ralph Dammel reported that block copolymers, with similar molecules together in blocks instead of randomly dispersed, tended to arrange themselves with the similar chain sections together, conveniently lining up into cylinders that look similar to lithographic contact holes, or into lines similar to lithographic lines and spaces. Wafer surface patterning with topography or chemicals can control the placement of these self-assembled patterns, on top of standard 193nm immersion lithography. Work with IBM Almaden suggests the process can provide better CD uniformity for quadruple patterning at lower cost than the spacer pitch division process. Other work shrinks contact holes, while improving the CD variation compared to the resist prepatterns. The company is now providing large-scale samples for in-fab process learning, with implementation perhaps as early as 2014, though design for self-assembly needs further development work.

November 8, 2012 – Researchers from IBM and Georgia Tech have disclosed significant progress in manipulating carbon nanotubes in transistors and interconnects, in ways compatible with traditional fabrication techniques, advancing toward using the materials for next-generation devices.

Connecting nanotubes to semiconducting substrate

Researchers from Georgia Tech say they have achieved a first: connecting multiple shells of a multiwalled carbon nanotube (MWCNT) to a semiconducting substrate without the high interface resistance produced by traditional fabrication technique — showing a way, they say, to facilitate integration of CNTs as interconnects in next-generation circuitry using both silicon and carbon components.

The work, reported online by the journal IEEE Transactions on Nanotechnology, uses electron beam-induced deposition (EBID), develops graphitic nanojoints on both ends of the MWCNTs, yielding a 10-fold decrease in resistivity in the connection to metal junctions. The technique "is amenable to integration with conventional integrated circuit microfabrication processes," explained prof. Andrei Fedorov. "Connecting to multiple shells allows us to dramatically reduce the resistance and move to the next level of device performance."

The low-temperature EBID process takes place in a scanning electron microscope (SEM) modified for material deposition — the vacuum chamber is altered to introduce materials precursors and the electron gun generates low-energy secondary electrons when the high-energy primary electrons impinge on the substrate at specific locations. When the secondary electrons interact with hydrocarbon precursor molecules, carbon is deposited with a strong, chemically-bonded connection to the ends of the carbon nanotubes, unlike the weakly-coupled physical interface made in traditional techniques based on metal evaporation, the researchers say. Prior to deposition, the ends of the nanotubes are etched opened so the deposited carbon grows into the open end of the nanotube to electronically connect multiple shells. Thermal annealing of the carbon after deposition converts it to a crystalline graphitic form that significantly improves electrical conductivity.

"Atom-by-atom, we can build the connection where the electron beam strikes right near the open end of the carbon nanotubes," Fedorov explained. "The highest rate of deposition occurs where the concentration of precursor is high and there are a lot of secondary electrons. This provides a nanoscale sculpturing tool with three-dimensional control for connecting the open ends of carbon nanotubes on any desired substrate."

The technique produces record low resistivity at the connection between the carbon nanotube and the metal pad — the researchers have measured resistance as low as ~100 Ohms, a factor of ten lower than the best that had been measured with other connection techniques.

This is still very early work, though. The researchers don’t know exactly how many of the CNT shells are connected (they think at least 10 out of 30 "are contributing to electrical conduction). And converting the birds’ nest of tangled CNTs of different lengths, properties and defectivity into a pattern for reliable interconnects is a challenge. The team says it has developed a method to align the MWCNTs across electrical contacts using focused electrical fields in combination with a substrate template created through electron beam lithography, which has "significantly improved yield of properly aligned carbon nanotubes." But much work needs to be done to improve CNT alignment, and perfect EBID systems to deposit connectors on multiple devices simultaneously (parallel electron beam systems might help here).

"A major amount of work remains to be done in this area, but we believe this is possible if industry becomes interested," Federov said. "This is really a critical step for making many different kinds of devices using carbon nanotubes or graphene."

 


Two SEM images showing a carbon nanotube interconnect done with the EBID process.
(Source: Georgia Tech)

Precisely placed, high-density CNT transistors

IBM, meanwhile, says it’s made a leap toward viability of carbon nanotube (CNT) transistors, by precisely placing and testing thousands of CNTs in a single chip using standard semiconductor processes.

The ability to isolate semiconducting nanotubes and precisely place them in high density on predetermined positions on a wafer is critical to assessing their suitability. So far scientists have only placed a few hundred CNT devices at a time, not enough to assess key issues for commercial application — and far below the millions or even billions of transistors eventually needed for future chips.

Earlier this year IBM showed a sub-10 nm CNT transistor showing 5-10× better performance than silicon circuits. The group’s newest work, detailed in the journal Nature Nanotechnology, describes an ion-exchange chemistry that allows precise, controlled placement of aligned carbon nanotubes on a substrate, with a high density (109/cm2) that’s 2 orders-of-magnitude greater than previous experiments.

The process involves mixing the CNTs with a surfactant to make them soluble in water. A substrate with trenches of chemically-modified HfO2 (and SiO2 everywhere else) is immersed in the solution, and the CNTs attach via chemical bond to the HfO2 regions; the rest of the surface remains clean. The new placement technique can be readily implemented since it involves common chemicals and existing semiconductor fabrication, IBM says, and compatibility with standard commercial processes also means rapid testing with high-volume characterization tools.

Carbon nanotubes "have largely been laboratory curiosities as far as microelectronic applications are concerned," acknowledged Supratik Guha, director of physical sciences at IBM Research. This new IBM work makes "significant strides" in solving two key challenges of ultrahigh-purity CNTs and their deliberate nanoscale placement, and thus represents "the first steps towards a technology by fabricating carbon nanotube transistors within a conventional wafer fabrication infrastructure."

SEM image of carbon nanotubes deposited on a trench coated in hafnium oxide (HfO2) showing extremely high density and excellent selectivity. Scale bar: 2μm. (Credit: IBM)

November 6, 2012 – Concern over a worrisome trend of underinvestment in semiconductor startups has prompted the Global Semiconductor Alliance (GSA) to form a new working group. Its inaugural mission: identify various alternatives to encourage startups to innovate, woo investors, generate returns, and keep generating sustainable industry M&A.

Investors are getting spooked from injecting capital into emerging semiconductor companies where the rate of return is becoming a longer-shot target. Complex digital IC products can require $100 million or more to develop and a decade or more to ramp-up with revenues; the GSA quotes analyst Andy Rappaport suggesting a semiconductor startup needs to hit $1B in a 5-10 year window off a $100M investment. Meanwhile, the semiconductor sector leads all industries in terms of R&D as a percentage of sales (24% for the 12 months 1Q11-1Q12), says the GSA. Besides the design and mask costs, there’s another $20M-$30M needed just for embedded software to make the design work, "an investment that is not easily recovered in the semiconductor business model where the price is often expected by the market to reflect silicon size," the GSA notes.

As a result, seed/Series A fundings have plummeted over the past decade, from several dozen annually averaging $9M-$10M in the 2000s to now just a handful averaging around $6M-$7M (and just $4.7M in 2011). That’s creating a major "innovation gap" in which there are fewer high-growth startup opportunities available, to be harvested by larger semiconductor firms seeking to bolster their position, leading to a longer-term move away from M&A as a viable strategy to achieve innovation and growth.

Total semiconductor Series A/seed funding, 2000-2011. (Source: GSA)

To address this widening gulf, the GSA has initiated a new "Capital Lite" working group populated with leaders from VCs, fabless firms and IDMs, semiconductor suppliers, and execs from finance, banking, and M&A interests. The group’s first official act is a white paper, "A Startup’s Guide to Surviving an Investment Drought," aimed to help inform and "invigorate" investment activity around semiconductor startups. Assisting this effort is a new resource portal in conjunction with IPextreme as a centralized location for tools and services from the entire semiconductor supply chain.

In the white paper, the group advocates for a "capital-lite" approach: a semiconductor startup sources services (e.g. IP, sales/marketing, SG&A, engineering, shuttle runs, etc.) from a larger semiconductor partner, which in turn reaps the benefits of another revenue source. The group puts out three types of hybrid financing models emphasizing different areas: low ASPs and high-volume markets i.e. consumer; higher ASPs/mid-volume markets i.e. enterprise; and IP-sharing/joint R&D. The group also advocates for a recently formed VC fund, "Silicon Ventures," which proposes to balance the risks between the startup, strategic partner/acquirer, and investors. It also points to the "Lean Startup" approach championed by entrepreneur Eric Ries, visualized as a "distributed startup" ecosystem here third-party technical activities are parceled out. (Adapteva is listed as a success story for this model.)

"We are looking to reverse the current decline in venture capital investment in the industry by re-balancing the risks associated with semiconductor start-ups," stated Silicon Ventures co-founder Ken Lawler. "Our model does this through active collaboration from inception between a start-up, a strategic partner/acquirer, and the investors, which will reduce product development costs, speed time to market, and provide compelling acquisition opportunities for the strategic partners."

November 5, 2012 – In early January of this year, both Samsung and LG showed off 55-in. versions of their organic light-emitting diode (OLED) TVs at the Consumer Electronics Show (CES) in Las Vegas. Commercial volumes were expected on shelves by the time of the 2012 Summer Olympics (which didn’t happen); they were again showed this fall at IFA in Germany.

Unfortunately, still struggling with low manufacturing yields and high prices, the two giants recently admitted the delivery of those technologies will be pushed out into 2013. NPD DisplaySearch now projects only 500 OLED TVs will ship in 2012.

Still, one must crawl before taking first steps and eventually running with the pack. Actually getting products out into the market is an important move, even as LCD TVs continue to get bigger and with higher resolutions. "4K × 2K LCD TVs have has become a focus and are currently available, and OLED TV needs to demonstrate its technical superiority," points out David Hsieh, VP at NPD DisplaySearch. "If we do see OLED TVs hit the market within 2012, the shipments will be used primarily for retail demonstrations in developed regions like North America and Europe."

OLED TV technology still has to overcome a number of obstacles, explained by the research firm:

  • Technical challenges: Making and scaling up large OLED panels (e.g. 55-in.) is a different animal vs. the smaller ones (e.g. 5-in.) now at high-volume output for smart phones.

  • Manufacturing limitations: Only two Gen-8 OLED lines are in place for TV panels, still in pilot mode and with low manufacturing yields which is keeping costs high and limiting the ability to address demand.

  • High price: Initial retail price for a 55-in. OLED will be around $10,000 — that’s not going to cut it when 60-in. LCD TVs sell for under $1000.

  • New high-definition competition: While the two Korean suppliers focus on OLEDs TVs, competitors in Taiwan, China, and Japan are developing LCD TVs with ultrahigh definition (4K × 2K).

  • Market timing: How much advantage do Samsung and LG have from their early adoption of OLED; will competitors quickly close that gap?

NPD DisplaySearch is still bullish on OLED’s longer-term competitiveness, though, expecting that suppliers in Taiwan, China, and Japan will indeed pick up the mantle of AMOLED TV panel production. The firm projects over one million unit shipments in 2014, and a 3% market penetration by 2016.

Forecasted shipments (in millions) and penetration rates for OLED TVs. (Source: NPD DisplaySearch)