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November 1, 2012 – X-Fab Silicon Foundries says it has become the majority shareholder in German MEMS Foundry Itzehoe GmbH (MFI), the latest in a series of recent moves to raise its profile as a top MEMS foundry.

The MFI business, renamed X-Fab MEMS Foundry Itzehoe, complements X-Fab’s capabilities in its MEMS foundry in Erfurt, adding technologies for microsensors, actuators, micro-optical structures and hermetic wafer-level packaging processes. X-Fab originally signed MFI as a contract MEMS manufacturing partner in Feb. 2011, a deal that expanded its capabilities across a range of 200mm MEMS technologies. Its ownership stake in MFI is now 51%, up from 25.5%.

X-Fab MEMS Foundry Itzehoe will continue its long-term cooperation with the Frauhofer Institute for Silicon Technology‘s (ISIT) MEMS Group. MFI was spun out of ISIT in 2009 and is located within the same wafer fabrication facility in Itzehoe/Germany.

"Our customers will benefit from both an even wider spectrum of available MEMS technologies and from direct access to X-Fab’s manufacturing facilities for CMOS-compatible MEMS processes," stated Thomas Hartung, VP of marketing at X-Fab Group. "X-Fab MEMS Foundry Itzehoe will play an important role in the implementation of our MEMS strategy, and brings us closer to our goal of becoming one of the top three pure-play MEMS foundry providers."

"The rich combination of the versatile MEMS-specific technology portfolio at the Itzehoe-based MEMS foundry and the development expertise of Fraunhofer ISIT greatly expands the capabilities of X-Fab’s technology offering," added Peter Merz, managing director of X-Fab MEMS Foundry Itzehoe. "We are delighted to provide the full bandwidth of MEMS technologies including vacuum and optical wafer-level packaging or TSV backed by X-Fab’s existing and well-proven foundry services. This integration brings X-Fab customers bundled and accelerated product development and manufacturing cycles for micro-machined devices such as inertial sensors, micro-mirrors, and piezoelectric transducers."

Barely a month ago X-Fab pledged to invest $50M over the next three years to support projected growth and a goal of "becoming one of the top three worldwide suppliers of MEMS foundry services." (X-Fab placed 10th in Yole Développement’s 2011 MEMS foundry rankings, surging 33% to roughly $16M in revenues, about $31M shy of No.3 Silex Microsystems.) Among X-Fab‘s other recent MEMS accomplishments:

 

October 30, 2012 – This year is shaping up to be a historically lousy year for makers of flat-panel display (FPD) manufacturing equipment, but expectations are looking up that demand will catch up to supply in 2013 and balance the market, according to NPD DisplaySearch projections. Spending on FPD equipment is projected to plummet -69% in 2012 to $3.8 billion, making it the worst year in the sector’s history. But even with slow demand growth in maturing markets (TVs and PCs), the firm sees "significantly improved conditions" in 2013, more than doubling to $8.3B.

Most of that spending will be for new low-temperature polysilicon (LTPS) fabs or converting existing amorphous silicon (a-Si) capacity to LTPS, both for use in TFT-LCD and active-matrix OLED (AMOLED) production, explains Charles Annis, VP of manufacturing research at NPD DisplaySearch. "One reason spending is increasing so much is because LTPS fabs cost substantially more than a-Si fabs to build. There are extra process necessitate more than 10 mask steps." LTPS fabs also require higher-priced equipment, particularly high-resolution photolithography tools, he added, but having those technologies does enable production of high-value displays used in smartphones and tablets.



FPD equipment spending forecast. (Source: NPD DisplaySearch)

Such dramatic cutbacks in investment will more quickly rebalance supplies with demand and raise fab utilization rates. Meanwhile, new manufacturing technologies (oxide semiconductors, in-cell touch, flexible AMOLEDs and AMOLED TVs) promise lower costs and higher-value applications. Together that spells improve profitability for panel makers, notes Annis. Even with the cautionary disclaimer that new investments (e.g. AMOLED capacity) can be pushed out or cancelled if performance and cost targets don’t materialize, most of the firm’s indicators project 2013 "to be a much better year than 2012."

October 24, 2012 – Semiconductor manufacturers can expect equipment costs to increase about 15% for each new process node, but all the advantages of moving to smaller feature sizes are no longer offsetting those costs — even with the promised advantages of a 450mm wafer transition, say Gartner analysts in a new report.

A 450mm manufacturing transition — which the industry seems to have finally embraced and is pushing ahead on multiple fronts — promises 30% cost reductions vs. 300mm wafer processing, even with the inherent extra challenges in processing the bigger wafers. (Caveat: Gartner’s bearish on the 450mm benefits, saying it might only give 10% savings, or even none at all.) New semiconductor technologies (materials, equipment, architectures) being developed could also slow the rate of cost increases.

Unfortunately, that 30% reduction from a 450mm wafer-size transition "represents about only three or four years of increasing equipment costs, and consequently, delays the inevitable," the analysts say. And even if new advanced technologies pan out as promised and reduce costs — and that’s a big "if," getting semiconductors down through the teens and into the single-digit nodes — that too will be only a temporary reprieve: "The reality is that rising costs are a permanent part of the industry, and the fundamental economics of the industry may start changing sooner rather than later."

Here’s more data they use to back up their case:

  • Equipment costs for leading-edge semiconductor manufacturing are increasing 7%-10% per year, depending on the basic process;

  • By 2016, the minumum capex budget needed to justify building a new fab will be $8B-10B for loic, $3.5B-$4.5B for DRAM, and $6B-$7B for NAND flash;

  • By 2020, current cost trends will push the pricetag for a leading-edge fab investment to a budget-melting $15B-$20B;

  • At current spending rates, only eight chipmakmers will have the financial capability to build new fabs in the next few years.

For all but those chosen few leading-edge chipmakers, here is the Gartner analysts’ advice:

  • To big chip consumers: firmly attach your supply chain to one of those few leading-edge fabs, and make sure any fabless partners link themselves to one of the few foundries remaining on the leading edge.

  • Fabless semiconductor companies: get long-standing contractual arrangements with leading-edge foundries to guarantee access.

  • For the biggest fabless companies: Even if you’re seeing short-term wafer shortages, don’t jump into manufacturing yourself — explore a joint venture with leading foundries to ensure supply.

300mm average wafer fab equipment cost projections. (Source: Gartner)

The real kicker here? Lower costs per transistor aren’t even the real driving factor for semiconductor manufacturers, it’s reducing power consumption while maintaining performance, the Gartner analysts note. That’s the key functionality driving semiconductor content in mobile devices, and that’s what is driving the market now. (It’s a little different for memory which does rely on lower unit/production costs even if it’s a slight improvement.) "Overall, the semiconductor and electronics industry will have to come to grips with the fact that traditional cost reductions with each new node are in jeopardy, and in the future, higher performance may very well come at a higher price," the analysts note.

And one more factor to consider: semiconductor average selling prices (ASPs) have benefitted from the relentless node-shrink cost reductions, but semiconductor manufacturers are unlikely to (nor should they) swallow all these cost increases by themselves for the good of the rest of the supply chain. "What is more likely is that ASP trends will reverse after years of decline, and that reversal will change the supply-and-demand economics of the industry in ways that we don’t really understand today," the Gartner analysts admit.

Keeping it Cool

Back in 2008 we addressed 3D cooling activities [see PFTLE 43, "Keeping it cool in the dog days of summer"] looking a the activities at IBM Zurich, GaTech, and CALCE (U Md) as the groups especially active in this area.

Since then we have looked further at the liquid cooling activities of Bakir at GaTech [see IFTLE 83, "Orange County IEEE CPMT 3DIC Workshop"] and Brunschwiler at IBM Zurich [see "IBM to use water cooling for future 3D IC processors"] and the fact that one of the drivers for 2.5D is that it offers better thermal performance that current 3D stack solutions [ see IFTLE 97, "DATE in Dresden, Synopsys 3D EDA solution"]. For the most part, though, IFTLE has taken the position that thermal would not be the roadblock for 3DIC and that initial products would be ones where the thermal solution was not driving the technology.

Now that we are quickly approaching full commercial production of a number of products, it’s probably a good time to focus more on proposed thermal solutions for the future. To update yourself on where things stand, I suggest Herman Oprins’ article "Modeling and experimental characterization of hot spot dissipation in 3D stacks." He concludes that thermal management issues in these 3D stacks are one of the main challenges for 3D integration since the use of polymer adhesives with low thermal conductivity, the presence of interconnection structures, back end of line (BEOL), redistribution layers (RDL), and through-Si vias (TSVs) increases the complexity of the conductive heat transfer paths in a 3D stack.

Oprins concludes that hot spot power dissipation results in significantly higher temperatures in 3D stacked chips compared to the same power dissipation in single 2D chips. This temperature increase is mainly due to the reduced thermal spreading in the thinned dies on the one hand, and to the use of adhesives with low thermal conductivity for the vertical integration of the chips on the other hand. To limit the temperature increase in 3D-ICs, "too thin chips should be avoided" because the thinner the silicon substrate, the higher the thermal spreading resistance is in the case of hot spots. Simulations show that a minimum die thickness of 50

by Tom Morrow, executive vice president, Emerging Markets Group, SEMI

European government representatives, consortia and suppliers discussed programs to support and participate in the anticipated conversion of leading-edge wafer manufacturing to 450mm wafers at SEMICON Europa in Dresden. Possibly signaling a major change in the 450mm planning framework, representatives from G450C, imec, Fraunhofer IISB, and others discussed mechanisms for greater European participation, and emerging research initiatives, related to 450mm development. In addition, in probably the first major public discussion of the 450mm lithography system schedules following investments from TCMC, Intel and Samsung last summer, ASML provided a comprehensive presentation on their roadmap for 450mm EUV platforms.

Michael Liehr, newly promoted to executive Vice President of Innovation and Technology at the College of Nanoscale Science and Engineering (former IBM veteran, Paul Ferrar has been appointed General Manager, Vice President and coordinator of G450C project), provided an update on the consortium’s pilot fab, tool roadmap, wafer development, and wafer availability plans. Newly announced at Europa was G450C’s welcome of global collaboration efforts with regional consortia and government agencies. As a new consortium on the crowded stage of collaborative research development, G450C’s working relationship with other consortia in the industry has been an ongoing question for manufacturers, suppliers, and key stakeholders. G450C’s role in prequalifying tools for 450 wafer manufacturing places them in a powerful, central role in the future of the industry. With the industry consolidating and global R&D dollars needing increasing focus and efficiency, the roles, core competencies, and optimal distribution of research initiatives across the world is undergoing significant transformation.

"We’re looking forward to working with any regional organizations including wafer pool and adjunct tool demos," said Liehr during the session. While G450C priority remains on the specific program deliverables, Liehr spoke to the need to recognize and value the contributions of other players in global industry. He said that G450C selection, validation, evaluation of projects would proceed with criteria emphasizing technical and commercial transition value and that "G450C understands that public funding must be applied within the taxpayer region."

Liehr’s comments were welcome news to European consortia with a high stake in the semiconductor industry. The Fraunhofer-Gesellschaft network in Germany, for example, has 60 institutes, more than 1800 employees and an annual research volume of 1.65 billion euros (2010), of which 1.4 billion euros is generated through contract research. Lothan Pfitzner, head of department at Fraunhofer IISB provided an overview of his organization’s existing and planned activities in 450mm manufacturing process development. Pfitzner said Fraunhofer Group will support 450mm R&D&I activities based upon their strong expertise and experience in equipment assessment, manufacturing science (e. g. process control, automation, wafer handling, etc.), flying wafer concepts, green aspects, modeling and testing.

For reasons of cost optimization, Fraunhofer is also willing to reclaim 450mm wafers. In addition, Fraunhofer hopes to contribute in the area BEOL and of TSV in optimization of processes as well as in the area of metrology and defect detection and characterization. Part of these activities will take place at the Fraunhofer IISB Erlangen facilities.

Fraunhofer plays a key role in many current and planned public-funded research efforts related to 450mm manufacturing. The ENIAC EEMI450 is currently developing and evaluating wafer material, metrology tools, process equipment, and handling systems. The CATRENE NGC450 program is providing analysis and optimization of cluster platform performance. Planned programs under Framework 7 include SEA450 involving equipment assessment of cleaning and hot processing equipment and corresponding metrology tools. Another planned program is ENIAC 450EDL project involving virtual metrology and predictive maintenance models for 450mm metrology tools.

Imec, headquartered in Leuven, Belgium, has nearly 2000 researchers including more than 600 industry residents and guests, is also planning a 450mm pilot line to begin construction in 2013 and scheduled for completion in 2015. Phase one of the program is anticipating funding from the Flemish government, EU ENIAC FP7, and industry sources. Imec expects to play a key role in the acceleration of 450mm equipment development through installation of alpha and beta tools for early learning in an "industry-relevant technology flow." The organization’s track record of support for advanced process and lithography development is expected to be a key factor in securing a strong role in 450mm manufacturing programs.

Other European initiatives include those by Israeli "Metro450" Consortium comprised of five key companies: AMIL (metrology division of Applied Materials), Nova, Jordan Valley, Nanomotion, and Intel. University support comes from four institutions and public funding comes from the Israeli Chief Scientist budget. The regional interest in 450mm manufacturing stems from Israel’s strong success in wafer fab metrology, now accounting for over 30% of world’s share and approximately $1.3 billion in sales. Menachim Shoval, Metro450 Board Chair, said the transition of current 300 mm metrology solutions to 450mm manufacturing is not trivial and threatens their current world position.

Other regional interests expressed during the forum include those from the state of Saxony in Germany. Silicon Saxony, the organization representing the interests of the substantial semiconductor cluster, has a vision that by 2018 it "will be seen as a trendsetter for innovative semiconductor manufacturing technologies for 450mm and may plan to install its 1st 450mm manufacturing site in the Dresden region."

The scale and diversity of interests in 450mm is impressive, but a realistic forecast for European pilot lines and public funding is hard to gauge. Currently G450C plans to qualify "one or two…maybe three" tools per process, limiting broad supplier participation in future 450mm manufacturing. European efforts to supplement the G450C qualifying process may help open the participation opportunities for other companies in 450mm manufacturing, especially for European companies hoping to benefit from public funding. But significant EU and country funding of 450mm R&D is not yet assured. With the current European debt crisis and emphasis on austerity, significant funding for semiconductor R&D may be limited. Furthermore, there remains significant debate over research priorities with many in the European semiconductor community, including leading European device makers, favoring R&D emphasis on "More than Moore" programs.

Opening up the qualifying process for 450mm high volume production tools to European consortia would seem to benefit 450mm device makers, tool makers and the overall industry move towards 450mm wafers. In addition to expanding the number of qualifying tools and public R&D funding sources, European consortia can be expected to link important process development efforts in 3D transistors, 3DIC, and other areas with 450mm production requirements. Many of the current EEMI450 programs also feature unique approaches to metrology and material handling, adding an important "innovation" element to 450mm development efforts. At this stage of the 450mm transition, however, it is uncertain how likely G450C will move to open up their primary tool qualification role to organizations they may perceive as competitors. According to Liehr, "The same consolidation forces affecting device makers and suppliers are affecting R&D facilities. Specialization will need to be furthered so there is minimal overlap."

ASML begins 450mm development

Another noteworthy discussion in the European 450mm session was ASML’s plans for large wafer lithography systems to support high volume 450mm production. ASML successfully negotiated billions of dollars in capital investment by Intel, TSMC and Samsung this summer to support accelerated development of extreme ultraviolet (EUV) systems for 450mm manufacturing. Until a 450mm EUV lithography system is developed, 450mm pilot line development will utilize nano imprint technology, a significant R&D limitation according to many observers.

In perhaps the first public discussion of the company’s 450mm plans, ASML’s Frank Bornebroek discussed the product strategy and technology challenges for 450mm EUV systems. He described how ASML will now simultaneously develop four tools on two platforms to accommodate 450mm production. He said the initial versions will provide 30 wafers per hour in 2016-2017, extended to 60 WPH for EUV in 2018-2019. For immersion systems, ASML is targeting 50 WPH in 2016 and high volume systems in 2018.

While the company is committed to the G450C schedule for high volume production, significant technical barriers will need to be overcome. "It’s not just a scale up, but significant overlay improvements will be required…overlay drives patterning" said Bornebroek. "The larger the wafer, the more difficult it will be to improve productivity. We will need to accelerate 3-times more mass at 2-times more accuracy."

ASML is in process of hiring an additional 200 employees to meet the aggressive delivery goals. 450mm systems will require a "full base frame redesign" with major changes to chucks, mirror blocks, stages, tables and handlers, with adaptations to sensor and metrology systems. Bornebroek indicated that "450mm wafers will provide limited cost benefit for scanning systems."

October 17, 2012 – Industry watchers have been awaiting the worst after Intel lowered its 3Q12 expectations a month ago. In the end, the chipmaking bellwether produced better-than-feared results even with concerns about end demand.

Revenues for 3Q12 were $13.5B, at the cap of Intel’s reduced outlook, and gross margins were a notch better than warned (63.3% vs. 62%). Both were flat sequentially. Net income actually improved about 7% to $3.0B. Intel sees sales picking up a bit in 4Q12, to $13.1-$14.1B, though gross margins will slip to 55%-59% due to charges relating to excess capacity, what Intel CFO Stacy Smith characterized as "aggressive tactical actions." Those charges will be mostly restricted to 4Q and not beyond 1Q13.

"The enterprise PC market has gone relatively flat now," a reflection of cautious business end-demand, and this has "spilled over from the client side of the enterprise [to] data center server part of the enterprise," acknowledged Paul Otellini, Intel president and CEO, during the results conference call. Overall PC business growth was about half what is seasonal normal in 3Q12, and will be again in 4Q12 — the real question is whether that’s due to macroeconomic factors, or due to end demand awaiting Windows 8 and new PC/tablet/ultrabook refreshes in the coming months.

To that end, Otellini expressed optimism over demand in the near-term 4Q and beyond. "The world of computing is in the midst of a period of breakthrough innovation and creativity," he said, citing more than 140 core-based ultrabooks in the pipeline, a third of which will have tablet-like touch capabilities and many at or below the $699 price point.

In response to end-demand softness, Intel as expected is reducing its 2012 capex "pretty significantly" to $11.0B-$11.6B, a full billion dollars below its trajectory a month ago. CFO Stacy Smith reiterated the reasoning: reign in utilization to clear out inventory until demand recovers, and keep reusing existing equipment in its 14nm node efforts. "We are taking down utilization in the factories down to sub 50% again to take inventory out and free up the opportunity to move both space and equipment and redirect that to 14nm," noted Smith. He specifically declined to issue a forecast for 2013 capex, saying it will depend on unit growth and visibility into 2014 — but "right now we want to fight through a Q4 where we don’t have a lot of visibility before we lock in on a 2013 number."

We’ll be updating this story with analysts’ feedback about Intel’s results and its impact mainly on the semiconductor manufacturing ecosystem — but generally speaking, cutting over a billion dollars and capex, and acknowledging little visibility to even formulate (publicly) 2013 expectations, is likely to reverberate across the landscape.

October 15, 2012 – Researchers at the National Institute of Advanced Industrial Science and Technology (AIST) and the Chemical Materials Evaluation and Research Base (CEREBA) say they have evaluated molecules within a sealed organic light-emitting diode (OLED) in operation using laser spectroscopy, measuring both selectively and nondestructively

Their work, published in August in Applied Physics Letters, involves a method improving upon a laser spectroscopic technique to measure molecular vibrations at the interface of an organic layer inside the OLED device — specifically, evaluating a signal enhancement phenomenon that occurs at the interface with a concentrated electric field.

The problem with evaluating OLED devices, as with many other types of sensitive electronics components: the method itself often involves destroying the device or impacting its performance (e.g. introducing contaminants). Measuring OLED device degradation, particularly in devices with multiple and overlapping internal layers, is particularly difficult — yet much more needs to be known about the inner workings of OLED layer degradation to learn how to extend the device’s lifetimes for application in displays or lighting.

Key to AIST’s work is using "sum frequency generation" (SFG) spectroscopy, which employs wavelength-tunable lasers to collect information on specific interfaces of organic substances in complex organic devices. Specifically it has pursued two-color SFG spectroscopy to measure vibrational changes at the surface and interfaces in a solid; one tunable visible laser would still collect signals from multiple organic lasers, but implementing two lasers creates a "double resonance" that can be used to enhance and isolate signals from a targeted organic layer. They also tweaked the SFG spectrometer to maintain measurement resolution even at 1/100 laser power of conventional SFG spectrometers.

"By investigating in detail the ‘fingerprints’ of organic layers in an OLED device, the alteration and degradation of molecules in the operating device as well as the change in the electric field inside the device can be elucidated," AIST explains. Their goal is to determine, at the molecular level, the driving mechanisms of OLED devices and their degradation — and also seek ways to apply the work to other organic electronics fields, such as solar cells and transistors.

CERERA was established at AIST specifically to establish design and manufacturing technologies for OLED materials and devices, including evaluation and analysis techniques.

Top: Schematic drawing of the structure of the multilayered OLED device and the directions of the incident and emitted lights used for SFG spectroscopy. Bottom: Spectral changes in an operating multilayered OLED device, with +8 V application (light emission), no voltage application, and –5 V application. (Source: AIST)

October 12, 2012 – The advent of leading-edge semiconductor packaging technologies dictates efficient use of capital, and only the top-tier companies will have the financial wherewithal to develop required expertise and capacity. That means consolidation needs to happen in the semiconductor assembly and test services (SATS), according to a recent report from Gartner.

IDMs started moving packaging plants into the Asia-Pacific region in the 1980s, and by the early 1990s outsourced packaging had bloomed, and gained speed with the emergence of the fabless/foundry model, explains Gartner analyst Jim Walker in a recent report ("Competitive Pressures Will Bring Consolidation to the SATS Market"). Over the past 10 years outsourcing has accelerated with proliferation of customized, application-specific packaging demand, and today the market has quintupled since 1997 to $25B, with nearly all the 130 SATS companies still in the greater Asia-Pacific region (including Japan).

Right now the SATS market is on a 8% CAGR trajectory from 2011-2016, but growth on an annual basis is slowing, Walker notes. The top five SATS companies currently comprise 50% of the market and will expand to nearly 60% by 2012 — that’s five out of more than 130 suppliers. The top 20 SATS companies comprise more than three-fourths of the market.

Top 10 SATS companies in 2011, sales as a percentage of total market. (Source: Gartner)

Consolidation is not only inevitable, it is sorely needed. Several factors will push these firms together:

  • Slower growth, due to market saturation. Crossing the 50% outsourcing saturation mark in 2011 implies that the total market available for packaging services from IDM, OEM, and fabless companies is shrinking, and will be more tied to industry unit growth and new business sectors.

  • Increasing competition at leading-edge technology nodes, and in niche markets. The process node migration continues (28nm, 20nm, 14nm, eventually 10nm and below), as does increased demand for mobile devices, which together necessitate more packaging technology and capacity for capabilities including WLP, flip-chip, through-silicon via (TSV), and redistribution layers. Those who can stomach the capital requirements for these, will stay on top — and those who cannot will find themselves on the losing end.

    Similarly, as the outsourcing sector aligns to industry unit growth, SATS companies focusing on specific markets (e.g. memory) are more exposed to narrow, commodity-like and price-sensitive market forces. Such companies need to expand on their own into other markets, or consolidate with bigger and broader SATS companies. See recent expansion/divestment news from PTI, Power ASE, SPIL, and ChipMOS. (In fact this trend could spell the end of memory-specific packaging and test services market, Walker notes.)

  • Continued efforts by IDMs and OEMs to outsource backend processes. Technology investments and capacity additions are a hard sell when utilization rates are low (or aren’t at full strength). The proliferation of packaging options (Gartner cites >2000 unique packages) is forcing OEMs/IDMs to rethink sharing capital investments, deciding to leave it to the outsourced "experts."

  • Increasing importance of a China market strategy. Most top 10 SATS companies have at least one Chinese manufacturing facility, initially taking advantage of cost savings and incentives. But now, recognizing China’s swelling appetite for electronics components and systems, SATS firms want and need those domestic capabilities to satisfy demand. ASE, for example, has led the way in defining a strategy that straddles operations in both Taiwan and China, including $1.2B to build up operations in Shanghai and Pudong.

Continued emergence and development of wafer-based packaging process technologies requires both wafer fabrication and semiconductor packaging manufacturing equipment, processes, and expertise — meaning foundries can do some of them too, such as wafer bumping and underbump metallization. Similarly, 3D package stacking, embedded components, and system-in-package (SiP) devices require both processes and technologies for packaging and printed circuit board assembly — and technologies such as system-on-package will further blur these roles. SATS firms should expect to see increased competition from the foundry market, Walker notes. They also need to expand their services to include test capabilities, package design, and module offerings. And perhaps most importantly, they need to get virtual or vertical — develop an acquisition plan or partnerships/joint ventures with foundries, EMS/ODM firms, and/or materials and equipment companies, he advises.

October 9, 2012 – Multiple reports summarizing this year’s International Symposium on Extreme Ultraviolet Lithography noted a mixed bag of results and updates: a few slippages in technology performance and roadmaps, some key improvements, and overall progress that’s still slow but in a generally forward direction.

It’s increasingly clear that EUV volume production is a matter of when and not if. "It is clear to us that the entire supply chain is beginning to support the technology," notes CJ Muse from Barclays. "EUV remains potentially the biggest product cycle in the history of semiconductor capital equipment," echoes Satya Kumar from Credit Suisse. (It’s a small supplier group poised to take advantage of that, though; ASML and Cymer, with other source firms making noise.) At the same time, for devicemakers, "EUV at high throughput is the best thing that can happen to leading-edge chip makers to counter rising capital intensity."

EUV source productivity remains the top concern, with a consensus at the symposium that EUV source productivity needs to "increase dramatically over the next 1-2 years" to push EUV lithography into high-volume manufacturing by the latest target date of 2014, reports imec which hosted this year’s EUV Symposium in Brussels in cooperation with SEMATECH and Japanese consortium EIDEC. Specifically, a reliable 200W source is needed by 2014 for initial cost-effective production — and followed by a push toward 500-1000W to keep the technology cost-effective down the long-term path of continued IC scaling. Reliability of sources has improved, though, and researchers are demonstrating ways to increase conversion efficiency to 4%-5%.

Progress is reported in another key hurdle, EUV mask handling, but imec acknowledges that availability of yielding masks to support pilot lines and later high-volume production "remains a serious concern." As a result, imec acknowledges that the EUV pellicle solutions are once again being explored to help mitigate the defect challenge.

Elsewhere, symposium presenters reported incremental improvements in resists to meet requirements of resolution, linewidth roughness, and sensitivity simultaneously. One identified issue is that best-performing resist materials sometimes show a lower photo speed that does not align with sensitivity assumed in the exposure tool suppliers’ productivity roadmap, imec notes. Another area of improvement, noted Kumar, is in line-edge roughness (LER) and line-width roughness (LWR), and how etch can play a role here. At 22nm half-pitch, <2nm LER/LWR is required; the NXE3100 shows around 4.7nm, an improvement from the alpha demo tool’s 5.9nm. Imec and Lam Research have developed a hydrogen passivation-based process to smooth and lower the LER/LWR down to 3nm, and see further room for improvement.

ASML

Source power improvements are tracking slower than expected, but more significant advancements are expected once the new ASML NXE3300B ships out in coming months, containing Cymer’s 2nd-gen HVM-II source, noted Kumar. ASML has tripled its EUV source manufacturing capacity to 23 "cabins" and is currently building seven systems of its anticipated 11 shipments in 2013. "We expect to see reports of substantial progress by SPIE in Feb. ’13" he writes. Specific anticipated improvements to the new ASML NXE3300B system include:

  • Higher transmission: The light enters the scanner at a steeper angle, resulting in lower energy loss as it reflects off the mirrors;

  • Better optics: Zeiss has "substantially improved the roughness and tolerance specs" to reduce aberration and flare (Barclays’ Muse pegs it as a 3× improvement in lens aberration). And a new mirror design allows a higher numerical aperture (NA) of 0.33, vs. 0.25 in the 3100 tool, enabling lower resolution — and Zeiss has a roadmap to get EUV NA to 0.6;

  • Better illumination: A new capability in the 3300B is "off-axis illumination" with no energy loss — yet another knob for lithographers to improve uniformity and resolution of printed features;

  • Wafer handling: Tighter overlay, faster speeds, and better matching between tools; and

  • A better source: The NXE3300B will incorporate Cymer’s new HVM-II source, which includes a pre-pulse option to improve power.

Cymer

Cymer’s source progress is "a mixed bag," with improvements on some metrics but missed targets on others, and some data not appreciably improved from SPIE in February, Kumar reports. Specifically, the throughput timeline to upgrade sources in the field has slipped by about six months from February targets (i.e. 50W sources in 3Q12), though better power performance is being seen on R&D sources. Similarly, Cymer reports improvements to the droplet generator (a new steering mechanism has improved tin droplet stability, points out Muse), but improvements to collector mirror lifetime are below targets.

Kumar cited comments from Intel’s IDF last month indicated that 50-70 wafers/hour throughput would make EUV acceptable for some applications. Samsung, meanwhile, wants to use EUV for some 20nm DRAM layers at throughputs barely half that (30 wph). Both Toshiba and Hynix said at the EUV Symposium that NAND throughputs need to be much higher (at least 125wph). Hynix added that doses have to be doubled to 22-24 mJ/cm2 to achieve necessary CD uniformity.

General consensus is that an ASML EUV litho system shipping in 2013 with Cymer’s HVM-II source at 80W power, 100% duty cycle, and a new four-amplifier configuration would support 40 wph throughput if it works as planned. 250W of power will be needed to reach 125 wph.

Cymer currently has 10 HVM-I sources, five of which are at customer sites, running 9-13W at 60% duty cycle and 0.5% dose stability — that’s behind Cymer’s progress expected at SPIE in Feb., which is now shifted to a target date of 4Q12. The previous 4Q plans were 100W operating power in continuous mode (with prepulse) at 0.2% dose stability; now the company plans 40-60W in continuous mode with prepulse, and unchanged 0.5% dose stability, by 2Q13.

Three HVM-I sources are kept in-house in Cymer’s San Diego facilities, with one being upgraded to 50W using the prepulse technology by 4Q12. (Two other HVM-I sources are at ASML.) Six of the new HVM-II sources are being built, four at Cymer and two at ASML, which will ship with the 11 3300B systems in 2013, Kumar noted.

Another mixed improvement is in the optics. Carl Zeiss and Fraunhofer Institute have developed a new collector mirror coating that enables an in-situ hydrogen cleaning process, improving collector mirror lifetime at least 45bb pulses on a customer-site HVM-I source — a 4× improvement from previous levels but equally lagging the 120-260bb pulse targets issued in February. (Apparently the mirror was removed at 45bb after a chamber leak, not a problem with the sputtering process, so that 45bb might not be the actual limit.) Cymer claims that 45bb pulses translates to four months of performance on ~100 wafers/day; Kumar extrapolates that volume production at 70wph would mean just 2-3 weeks of collector lifetime which would be "unacceptable for chip companies."

One key update to the EUV source is an improvement in Cymer’s "prepulse" technology. At SPIE in February the company said prepulse on its in-house HVM-I sources had shown 50W average power with high duty cycle but only for a short duration, and 90W in burst power at 20% duty cycle. That’s now been improved to 50W at 40% duty cycle but in a continuous automated mode for five hours (and 160W peak raw power on a development tool, notes Barclays’ Muse). Kumar translates this to 10wph throughput for five hours at 15mJ dose, which would double the output (to 200 wafers/day) with much better imaging results and 90% die yield. If Cymer can indeed deliver 90W power at 100% duty cycle with a 4-amplifier configuration by this time next year (2H13), chipmakers might have 40wph throughput in production — and we’ll start hearing more and louder rumbles of EUV production possibly in 2015.

Other sources

Cymer isn’t the only EUV source developer, though. Ushio (in what Kumar called "an enthusiastic presentation") reported 74W of power in burst mode at 12% duty cycle for a short 1hr run, better than the 30W/100% duty cycle and 37W/50% duty cycle it reported a year ago. The company’s source at imec (using 2 lasers to tailor the pulses) is exhibiting 10-12+J of energy, well improved from the previous version’s ~3J, notes Muse; the company cited specs of ~70%-80% average uptime, and hit ~96% uptime just days ago. A test source, Obelix II, supports very high (>250W) power at low repetition rates. imec, currently the only customer with an ASML 3300 and Ushio source, noted significantly improved uptime after a few Ushio hardware changes.

Still, Ushio "still has not demonstrated high power at high duty cycle, continuous mode operation for extended periods of time," Kumar notes. Its main problem is how to handle molten tin (don’t let it solidify and stay in the system), managing the extremely high electric field in between the drums as power is scaled up, and managing heat extraction from the drums. "Perhaps ASML may consider diverting a portion of the monies received from chip maker customers to keep Ushio’s R&D efforts alive," as a hedge against Cymer, Kumar writes. In the long run, though, "there will likely be only one source supplier," and he’s betting on Cymer.

Gigaphoton, meanwhile, "continues to make incremental progress" but "remains far behind" both Cymer and Ushio/Xtreme, noted Muse. Its Proto 2 source released this year with improvements to the droplet generator, CO2 laser, and EUV chamber is hoped to reach 50W clean power for 1 week stable operation by 1Q13, and a pilot tool ready later in 2013.

Mask inspection

KLA-Tencor says it shipped its first Teron 630 EUV inspection system on Sept. 25. The system, which uses DUV light with flexible illumination and polarization, takes 2-4hrs scan time, and can be extended from 22nm HP to 18nm HP. An actinic tool is under development, with a go/no-go decision needed by 4Q12; the company currently sees no showstoppers, though, and still expects to record actinic tool sales in 2015. This system takes 4-6 hrs for pattern reticles, Kumar notes, and pricing could exceed $50M.

Muse also pointed to another actinic light source from Swiss firm Adlyte, which showed its own high-brightness LPP EUV light source for actinic mask inspection. At SPIE in early 2011 the company described results of low conversion efficiency (about 1%) but respectable source brightness in a compact footprint requiring comparably lower power. Now, this "upstart company" has completed characterization of the engineering tool, with a prototype now in development and bill-of-materials procurement completed. Installation and integration is planned for 4Q12 and testing/demo in 1H13, followed by volume production.

Demonstrating brightness and cleanliness with improved positional stability is important, Muse notes, because of the critical need to perform metrology and inspection on what is printed via EUV. More players in this sector, besides KLA-Tencor and Applied Materials, is "a clear positive that the entire food chain is starting to support EUV," he writes.

Four of the leading micro- and nanoelectronics regions in Europe are joining forces to form a cluster alliance called “Silicon Europe.” The four groups, Silicon Saxony (Dresden/Germany), DSP Valley (Belgium), Minalogic (Grenoble/France) and Point One (Eindhoven/Netherlands), will be cooperating in research, development and business expertise.

Together they represent about 800 research institutes and companies, which account for more than 150,000 jobs; among the companies are global market leaders such as Philips, NXP, Globalfoundries, Infineon, STMicroelectronics, Schneider Electric und Thales.

This is a three year effort, as shown in the diagram. “We want to set up a joint action plan that is organized between the four clusters,” said Frank Bösenberg, in charge of administration of Silicon Europe, speaking at a press conference in Dresden. “Not only this, in the third year, we also want to start implementing this action plan. It’s not only about creating paper, but doing some action. In addition to this, we want to involve if possible additional European players.”


 “Global competition is tough and investments into European microelectronics are declining”, says Jean Chabbal, Chief Representative and CEO at the French Cluster Minalogic (Grenoble/France). In 2007 only 10% of all worldwide investments into microelectronics, around 28 billion Euro, went to Europe, while about 48% went to Asia. Since 2000 Europe’s market share in the semiconductor industry has dropped from 21 to 16 percent, yet the European microelectronics sector still employs 135,000 people directly along with another 105,000 in its supplier industries. “Europe is home to a number of the world’s best known, and most active regions in the micro- and nanoelectronics industry and the semiconductor industry, more specifically. These clusters, established over many years, with strong consolidated structures from industry, research and local governments, serve all application fields of micro- and nanoelectronics and have access to the most advanced research and key competencies – the European micro- and nanoelectronics sector must take advantage of this leading position and further expand upon it. This is the only way for Europe to maintain its role as a world-renowned leader in technology research and development”, continues Jean Chabbal.

Silicon Saxony (Dresden) is a unique conglomeration of companies with know-how in micro- and nanoelectronics, photovoltaic, organic and printed electronics, energy efficient systems, communications technology and sensor networks. More than 300 cluster partners employ 48,000 people. 

At the cluster Minalogic (Grenoble) 204 cluster partners with more than 39,000 employees develop modern micro- and nanoelectronics and integrated system-on-chip technologies. Their work applies to the sectors energy efficiency, connectivity and mobility, health systems and traditional industries. 

Point-One (Eindhoven) connects 170 cluster partners, who jointly develop solutions for mechatronics, integrated systems, photonics and micro-and nanoelectronics. Their solutions apply to lighting systems, to semiconductor and photovoltaic production and also the mobility, logistics and security branches. 

The 75 partners of the technology cluster DSP Valley (Leuven) are focusing on the development of hardware and integrated software technology for digital signal processing and system-on-chip solutions. 

Silicon Europe calls for a European ICT-Summit

 “Our activities and plans will not end at national borders as they did before – Silicon Europe stands for the common interest of the European microelectronics industry”, explains Peter Simkens, Managing Director at the Belgian Cluster DSP Valley. “However, to be successful in the long run, Silicon Europe and European microelectronics need active political support. We are appealing to all national governments to increase the synchronization of their economic and innovation policy with the European Commission and its guidelines. In order to realize this we are calling for a European micro- and nanoelectronics summit, which – similar to the German IT summit – shall bring together leading actors and decision makers from the European Commission, the national governments and all relevant branch organizations and associations. The European economy needs to expand on its strengths now, if it wants to remain competitive in the global market for the long run.”

Transnational Cluster Alliance as a new impetus

“Silicon Europe stands for a new quality of an European industry policy”, says Thomas Reppe, General Manager of the German Cluster Silicon Saxony. “In close cooperation with regional development agencies and institutes we transfer the cluster concept of Saxony’s Research Cluster for Energy Efficiency ‘Cool Silicon’ – the strong cooperation across organizational and institutional borders – onto a transnational level. Through this new and strong cluster alliance we are securing not only Europe’s current know-how in production of KET relevant technologies, but we are also working together on a strategic technology roadmap, which can serve the European Commission as a template and development guide for future programs.”

Silicon Europe offers a platform for active exchange among the clusters and their nearly 800 members, including internationally leading corporations; more than 75 percent of all partners are small and medium sized businesses. By performing a detailed analysis of each of the four cluster’s main research topics and by synchronizing their activities, previously unused synergies are being utilized.

Europe 2020

By intensifying transnational cooperation of regional research-oriented competence clusters, Silicon Europe will make a substantial contribution to “Europe 2020”, the EU growth strategy for the coming decade. The program’s focus is the advancement of research and development as a basis for a modern and strengthened European society. “With their activities, the European Commission aims at a digital and resource-efficient development – for both of these core goals micro- and nanoelectronics are a decisive factor”, says Eelco van der Eijk, contact person for the high-tech industry at the Dutch Ministry of Economic Affairs.  One of the key words for these activities is ‘smart specialization’ – the EU’s control mechanism to tailor and efficiently distribute development funds in the European technology regions.

Michael Kretschmer, Vice-Chairman of the CDU Parliamentary Group at the German Bundestag, member of the German Bundestag and member of the Committee on Education, Research and Technology Assessment explains his support for the initiative: “The Europe-Cluster of the micro- and nanoelectronics sites is a very important signal for both German and European politics. Together and across national borders we have to ensure that this key technology still has a home in Europe in the future. In the past, European clusters seldomly worked together – luckily, this is going to change now. I appreciate the Silicon Europe initiative and wish for it to find numerous supporters and advocates also in the German Bundestag and the German government. The high-tech nation Germany can simply not forego these technologies that by enabling innovations in various industries create jobs and prosperity”.