Tag Archives: Top Story Right

The semiconductor industry posted record results in 2017, with revenue exceeding US$400 billion. Overall demand for semiconductor devices was robust throughout the year, driven by the growing adoption of electronics components across all applications, with particular strength in the mobile and data center markets. Semiconductor growth in 2017 was led by the memory segment, with impressive revenue reaching US$126 billion. It represents an increase of over 60% year-over-year. Yole Développement (Yole) Memory Team forecasts the memory market to reach US$177 billion in 2018, with 40% growth.

Under this dynamic ecosystem, Yole and its partners System Plus Consulting and Knowmade, all parts of Yole Group of Companies, deeply scan the memory area. They propose today valuable memory services to deliver world class research, data and insight. Their aim is to ensure its clients are well-versed in all aspects of this competitive industry. Yole Group of Companies leverage decades of industry experience and expertise while partnering with its clients to make sure they are consistently well-informed on this pushy market.

Today two memory research services, DRAM Service and NAND Service have been developed by Yole Group of Companies. Full description of both services are available in a new dedicated Memory section on i-micronews.com. In addition, a selection of technology & market news are daily selected by Yole’s memory team and posted in this section.

Make sure to collect deep insights and significant analyses from leading industry experts, combining over 50-year experience in memory and semiconductor-related fields.

Both DRAM and NAND markets were in a state of undersupply throughout the year, leading to rising prices and record revenue and profitability for the memory suppliers. Demand was very strong, led by mobile and data center / SSD and augmented by emerging growth drivers including AI , IoT and automotive. Supply growth across both DRAM and NAND was constrained, due to a combination of limited wafer growth and technological challenges.

The current macro trends of AI and machine learning, mobility, and connectivity, are favorable to both the DRAM and NAND markets, and will likely result in Memory continuing to increase its share of the overall the semiconductor market.

“Understanding memory supply/demand dynamics and its relationship with pricing is vital to understanding the broader semiconductor market and all associated supply chains”, asserts Emilie Jolivet, Division Director, Semiconductor & Software at Yole.

The DRAM market is constantly evolving and changing. Yole Group is announcing a 22% CAGR for bit demand over the next five years.

“New Chinese suppliers threaten the current market balance, and emerging memory technologies are poised to cannibalize huge chunks of DRAM demand while the demand drivers of the past, including PCs and smartphones lose steam and no longer push industry demand,” comments .Mike Howards, VP of DRAM & Memory research within the Semiconductor & Software division at Yole.
In parallel, NAND market is expected to set another revenue record in 2018, before a flattish 2019. Therefore it continues to expand, with several consecutive quarters of record revenue and profitability for suppliers.

NAND’s competitive landscape remains incredibly dynamic. Samsung is prepping its first fab at its massive Pyeongtaek site; Intel is emerging as a stand-alone supplier with capacity in China; and the sale of Toshiba’s memory business to a consortium led by Bain Capital is finally happening. Meanwhile, a new entrant looms on the horizon: China’s Yangtze Memory Technologies Co. (YMTC), which threatens to disrupt the status-quo as well as multiple other Chinese projects.

“NAND demand remains robust, with strong growth for enterprise SSDs in data centers, increasing adoption of SSDs in laptop PCs, and continued content growth in smartphones and other mobile devices,” asserts Walt Coon, VP of NAND and Memory Research at Yole.“These segments will continue driving the bulk of NAND bit consumption, though several emerging trends are poised to augment future growth, including AI and VR adoption, automotive, and IoT,” he adds.

Memory Research Service from Yole, provides all data related to NAND/DRAM revenue per quarter, NAND/DRAM shipments, pricing per NAND/DRAM type, near and long-term revenue, market share per quarter, CAPEX per company, and a market demand/supply forecast. It also includes a complete analysis and details on the demand side, with a deep dive into client and enterprise SSD, data centers, mobile, automotive, graphics, PC, and more. Each Memory Research Service is composed of both products, the Quarterly Market Monitor and the Monthly Pricing Monitor.

During the next few weeks, Yole’s Memory Team will attend a selection of key trade shows and conferences to present the Memory Research Services. Make sure you will be there and ask for a meeting right now. Mike Howard and Walt Coon will for example be at SEMICON West mid-July and the Flash Memory Summit (Santa Clara, CA, North America – From August 6 to 9) in August. More information: Yole’s Agenda

The semiconductor industry is nearing a third consecutive year of record equipment spending with projected growth of 14 percent (YOY) in 2018 and 9 percent in 2019, a mark that would extend the streak to a historic fourth consecutive growth year, according to the latest update of the World Fab Forecast report published by SEMI. Over the semiconductor industry’s 71-year history, only once before – in the mid 1990s – has the industry logged four consecutive years of equipment spending growth.

Korea and China are leading the growth, with Samsung dominating global spending and ascendant China on a fast, steep rise, surging ahead of all other markets. See Figure 1.

Figure 1 equipment spending by region (includes new and refurbished)

While Samsung is expected to reduce equipment investments in 2018, the company still accounts for a dominant 70 percent of all investment in Korea. At the same time, SK Hynix is increasing its equipment spending in Korea.

China’s equipment spending is forecast to increase 65 percent in 2018 and 57 percent in 2019.  Notably, 58 percent of investments in China in 2018 and 56 percent in 2019 stem from companies with headquarters in other regions such as Intel, SK Hynix, TSMC, Samsung, and GLOBALFOUNDRIES. Domestic, Chinese-owned companies – backed by large government initiatives – are building a considerable number of new fabs that will start equipping in 2018. The companies are expected to double their equipment investments in 2018 and again in 2019.

Other regions are also ramping up investments. Japan is increasing equipment spending by 60 percent in 2018, with the largest increases by Toshiba, Sony, Renesas and Micron.

The Europe and Mideastern region will boost investments by 12 percent in 2018, with Intel, GLOBALFOUNDRIES, Infineon and STMicroelectronics the largest contributors.

Southeast Asia will boost investments by more than 30 percent in 2018, although total spending is proportionately smaller than in other regions owing to its size. The main contributors are Micron, Infineon and GLOBALFOUNDRIES, though companies including OSRAM and ams are also increasing investments.

The SEMI World Fab Forecast, which also includes information on other companies, covers data and predictions through the end of 2019, including milestones, detailed investments by quarter, product types, technology nodes and capacities down to fab and project level.

Learn more about the SEMI fab databases at:

www.semi.org/en/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats.

Worldwide industrial semiconductor revenues grew by 11.8 percent year over year, reaching $49.1 billion in 2017, according to the latest analysis from IHS Markit (Nasdaq: INFO). Industrial electronics equipment demand was broad-based, with continued growth in commercial and military aircraft, LED lighting, digital signage, digital video surveillance, climate control, smart meters, traction, photovoltaic (PV) inverters, human machine interface and various medical electronics like cardiac equipment, hearing aids, endoscopy and imaging systems. The industry is expected to grow at a compound annual growth rate (CAGR) of 7.1 percent through 2022.

Optical semiconductors delivered excellent performance, due to the continued strength of the general LED lighting market. Power discretes demand has ramped up in industrial motor drives, EV chargers, PV inverters, traction and lighting equipment. General purpose analog has a strong five-year growth in various industrial markets, especially in factory automation, power and energy, and lighting. Microcontrollers (MCUs) are also projected to experience broad-based growth in the long term, thanks to advances in power efficiency and integration features.

“The resilient economy in the United States, and strong demand in China, carried the lion’s share of industrial equipment demand in 2017,” said Robbie Galoso, associate director and principal analyst, industrial semiconductors, for IHS Markit. “A European resurgence also provided a strong tailwind for semiconductor growth.”

Global industrial semiconductor market share rankings

Strategic acquisitions continued to play a major role in shaping the overall semiconductor market rankings in key industrial semiconductor segments. All the following top 10 industrial semiconductor suppliers achieved revenue growth in 2017:

  1. Texas Instruments (TI) maintained its position as the largest industrial semiconductor supplier in 2017.
  2. The acquisition of Linear Technology catapulted Analog Devices into second position.  The combined Analog Devices and Linear Technology company generated $2.8 billion in industrial revenue in 2017. This acquisition boosted ADI’s industrial market shares in diversified segments within factory automation, military aerospace, video surveillance, test and measurement, medical, and power and energy applications.
  3. Intel ranked third, as the company’s Internet of Things (IoT) division continued to generate double-digit revenue growth attributed to innovation and strength in its factory automation, video surveillance and medical segments. Growth was also aided by the proliferation of smart and connected devices and a tremendous uplift in data analytics.
  4. Ranking fourth, Infineon’s strong revenue growth continued to be led by industrial applications, especially in factory automation, traction and various power and energy segments like PV, electric vehicle chargers and power supplies, where its leading discrete and power management devices are used.
  5. In fifth position, STMicroelectronics solid industrial revenue stream stems from a variety of applications, including factory and building automation, where its MCU, analog and discrete components are used.
  6. Micron’s organic revenue from industrial businesses continued to flourish in 2017, pushing the company into sixth place, driven by dynamic random-access memory (DRAM) growth in industrial IoT (IIoT) markets, spanning factory automation, video surveillance and transportation.
  7. Toshiba ranked seventh, with industrial electronics revenue growing to $1.5 billion in 2017. Growth was driven by power transistor discretes, MCU, optical and logic integrated circuit (IC) solutions in manufacturing and process automation, power and energy, and building and home control.
  8. Microchip Technology ranked eighth, and its revenue growth was primarily supported by MCU solutions in manufacturing and process automation, power and energy, and building and home control.
  9. ON Semiconductor was ranked ninth in 2017, driven by manufacturing and process automation, including machine vision, power and energy, building automation and hearing aids and other medical devices.
  10. NXP ranked tenth in the industrial market, with its strong presence in manufacturing and process automation, building and home control, medical electronics and other industrial applications.

Although not part of the top 10 ranking, China’s massive investments in LED manufacturing were especially noteworthy. Chinese firm MLS rose from 18th to 13th place, after posting 50 percent revenue growth and reaching $1 billion in 2017. MLS beat out other leading general lighting LEDs suppliers Nichia, Osram and Cree.

Consumer demand and government mandates for electronic systems that improve vehicle performance, that add comfort and convenience, and that warn, detect, and take corrective measures to keep drivers safe and alert are being added to new cars each year. This system growth, along with rising prices for memory components within them, are expected to raise the automotive IC market 18.5% this year to a new record high of $32.3 billion, surpassing the previous record of $27.2 billion set last year (Figure 1), according to IC Insights’ soon to be released Update to the 2018 IC Market Drivers report.  If the forecast holds, it would mark the third consecutive year of double-digit growth for the automotive IC market.

Figure 1

Over the past several years, the global automotive IC market has experienced some extraordinary swings in growth. After increasing 11.5% in 2014, the automotive IC market declined 2.5% in 2015, but then rebounded with solid 10.6% growth in 2016. It is worth noting that the sales decline experienced in 2015 was primarily the result of falling ASPs across all the key automotive IC product categories—microcontrollers, analog ICs, DRAM, flash, and general- and special-purpose logic ICs, which offset steady unit growth for automotive ICs that year.

IC Insights’ recently updated automotive IC market forecast shows the automotive IC market growing to $43.6 billion in 2021, which represents a compound annual growth rate (CAGR) of 12.5% from 2017 to 2021, highest among the six major end-use applications (Figure 2).

Figure 2

Collectively, automotive ICs are forecast to account for only about 7.5% of the total IC market in 2018, although that share is forecast to increase to 9.3% in 2021.  Analog ICs—both general-purpose analog and application-specific automotive analog—are expected to account for 45% of the 2018 automotive IC market, with MCUs capturing 23% share. There are many suppliers of automotive analog devices but a rash of acquisitions among them in recent years has reduced the number of larger manufacturers. Some of the acquisitions that have impacted the automotive analog market include NXP, which acquired Freescale in 2015 and is now itself in the process of being acquired by Qualcomm; Analog Devices, which acquired Linear Technology in March 2017; and Renesas, which acquired Intersil.

By Deb Vogler

This year’s Advanced Lithography TechXPOT at SEMICON West will explore the progress on extreme ultra-violet lithography (EUVL) and its economic viability for high-volume manufacturing (HVM), as well as other lithography solutions that can address the march to 5nm and onward to 3nm. Several session speakers offered their insights into the readiness of EUVL for 5nm and how other lithography solutions will enable 3nm. See the full list of speakers and program agenda at http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.

Diverging viewpoints on EUVL readiness for 5nm

Mike Lercel, Director of Strategic Marketing at ASML

ASML expects its first customer to start volume manufacturing with EUV at the 7nm logic node and the mid-10nm DRAM node in the 2018/2019 timeframe. “EUV will replace the most difficult layers that require multiple patterning, and many layers will continue to be allocated to immersion tools for the foreseeable future,” said Lercel. “For the 5nm logic node, more layers are expected to migrate to EUV.”

Three ASML customers have early-access versions of the next-generation TWINSCAN NXT:2000i for the development of advanced logic and DRAM nodes. “This system delivers 2.0nm cross-matched on-product overlay, achieved through several hardware advancements,” noted Lercel. “It is also significant because this mix-and-match use with EUV features a significantly different hardware platform.” TWINSCAN NXT:2000i features a new alignment sensor and improved wafer table flatness, endurance, and clamping mechanism to enhance matching to EUV.

ASML has achieved good industrialization progress of its pellicle, with tests confirming that pellicles can withstand 245W source power and an offline power lifetime test indicating 400W capability. Compared to the 7nm logic node, the requirements for EUV masks will become tighter at 5nm, but Lercel noted that ASML sees good progress with the industry infrastructure to support 5nm in areas such as reducing mask blank defects. “We will continue to improve pellicle transmission for enhanced throughput, but there are no fundamental changes in pellicle requirements for 5-3nm logic nodes. We see no infrastructure showstoppers for the introduction of EUVL at the 5nm node.”

Stephen Renwick, Director of Imaging Physics at Nikon Research Corporation of America

Renwick said that the 7nm logic node is expected to be fabbed mostly using 193i lithography. “EUV will struggle to be ready for 5nm, limited by yield issues caused by stochastic effects in the resist,” said Renwick. “Ready or not, though, it will be used.” Renwick suggests that introducing multiple-patterning with EUV may be needed but would increase costs. “193i lithography will continue to be used with quadruple-patterning and in combination with other techniques – there is no single solution.”

Figure 1. Normalized cost/layer vs. lithography method. SOURCE: Nikon Research Corporation of America

When choosing between immersion lithography and EUV for different customer segments at 5nm, Renwick noted that the cost depends on the layer. “Some time ago, we calculated that the costs of either 193i triple-patterning or 193i SADP with two cuts were roughly equal to single-patterning with EUV,” explained Renwick (Figure 1). “That agreed with chipmakers’ public estimates and meant that the choice of lithography method depended more on the performance tradeoffs involved, such as 193i’s better line-edge roughness. At the 5nm node, we are probably faced with quad-patterning from 193i, double-patterning from existing EUV tools, or single-patterning from as-yet undelivered high-numerical aperture (NA) EUV tools.” Renwick believes that the competition between low-NA EUV double-patterning and 193i quad-patterning will be similar to the current situation (i.e., comparison of 193i triple-patterning or 193i SADP with two cuts vs. single-patterning with EUV), but for high-NA EUV tools he believes it’s too early to say.

Other challenges Renwick sees on the horizon for EUVL at 5nm are stochastic effects in EUV resists. “They cause yield problems on contact arrays and unacceptable line-edge roughness on line/space patterns,” said Renwick. “It’s unlikely that these effects will go away without increasing the litho dose, which will further challenge throughput performance.” He also questions whether EUV pellicles, though under development, will be “ready for prime time.”

Harry Levinson, Sr. Director of Strategic Lithography Technology and Sr. Fellow at GLOBALFOUNDRIES

Levinson said additional fundamental engineering work is needed to ready EUV lithography for 5nm. “Among the top problems are stochastics-induced resist defects, which increase significantly as dimensions shrink below those for 7nm,” explained Levinson (Figure 2). “Higher exposure doses will be required to address these issues related to stochastics at 5nm, which will require higher source output” (than 7nm).

Levinson said there will be greater motivation to use EUVL at the 5nm node vs. at 7nm to offset the large number of exposures associated with 193nm immersion multiple-patterning solutions. “The primary application of EUV lithography at 7nm will be for contact, via and cut layers,” Levinson noted. “It will be important to enable EUVL for metal masks at the 5nm node, which increases the need for an ample supply of very low defect EUV mask blanks.” Levinson added that the 7nm node is already stressing defect inspection capabilities, and no actinic defect inspection system is yet available for patterned masks. “This situation becomes more problematic with widespread application of EUVL to metal layers.”

Mask development for 5nm

Christopher C. Progler, CTO & Strategic Planning at Photronics

Progler said that the basic infrastructure for delivering EUV masks is available, especially for dark field layers and near in nodes. “The interconnected or more open frame patterns will need refinements to the processes and two to three nodes out will need certain new infrastructure,” said Progler. Overall, the main challenges for initial insertion are about creating a cost-effective and rapid-turn EUV mask process, he said. “The industry can certainly deliver EUV masks in some form. It is more a question of doing it efficiently and productively to match the stated value proposition of EUV over other lithographic methods. We don’t want a pick two of ‘cost, cycle time, capability’ sort of mask solution.”

More specifically, Progler explained that after the initial EUV mask development for 5nm focused on contacts and block layers, the major push for N5 switched to delivering single-exposure EUV metal patterning as early as possible. “This has opened some new challenges for masks given the resolution, critical pattern density and tight pitch defect requirements of the re-aggregated single-layer metal mask designs,” said Progler. “For example, on the resolution side, we are accelerating the insertion of higher dose photoresists and also driving patterning module improvements in CD control, mask LER and sidewall angle.” Progler added that at N5, the mask 3D structure itself – including the sidewall – will have a greater impact on lithography because it is tied to stochastic error rates on the wafer.

“Reliable, wide-area metrology for some of these 2D and 3D mask parameters is currently hard to come by. We may see an evolution of the blank structure at some point in N5, including hard mask options for pattern stability and expect earlier insertion of EUV mask process correction with model-based hot spot detection and rule checking as well. We also hope mask-scanner dedication is not needed, but there are some indications process sensitivity may push us earlier in this direction.” He added that to reduce metal layer defects, more attention needs to be devoted to advanced repair and model-based validation. “We are, unfortunately, still in a situation of blurry vision and high native defect counts alongside possible in situ contamination during mask changes.”

Figure 2. Resist stochastics-induced defects. Graph courtesy of Peter DeBisschop, imec; Source: GLOBALFOUNDRIES

Progler pointed out that, with the advent at 5nm, metal masks will require some level of actinic blank inspection for yield, increasing the cost of an already expensive mask technology. “So, unless we want to contend with double and triple photomasks’ starts to deliver a single metal layer, it will be very important to tighten the multi-sensor inspection, defect abatement, and repair loops,” said Progler. He does see some clouds forming around high-volume manufacturing pellicles for metal layers. “This remains an open question, mainly for thermal and materials reasons, not to mention cost and cycle time,” Progler said. “We may be pessimistic, but we do not see an HVM pellicle solution converging in the required timeframe, which means leaning even more on a wafer-level inspection in the validation loop.” He believes that streamlining validation will be a differentiator. “I can imagine one losing most of the EUV cycle time benefits by endlessly circling masks around if this is not done well.”

How does the industry get to 3nm?     

ASML plans to ship its first high-NA EUV prototope/pilot systems between 2020 and 2023 to support 3-2nm process development. “System designs are now being finalized and the platform is starting to come to life,” said Lercel. ASML supplier ZEISS is building a high-NA cleanroom for optics production. ASML believes that EUV, high-NA and DUV systems will be used together at the most advanced nodes and is designing to account for this mixed environment. “As chipmakers drive toward smaller geometries in the most advanced nodes like 3nm, they face unprecedented challenges in devices and materials. This will make the process control requirements even more challenging.” ASML is tackling these challenges with its YieldStar metrology platform, e-beam metrology (HMI) and computational lithography solutions that are designed to expand the process window, enhance process control, and improve patterning defect detection. “This ‘Holistic Lithography’ approach will become increasingly important to ensure throughput and yield at the most advanced nodes.”

Levinson said that the issues he projects for 5nm will need to be addressed further at 3nm. “The challenges associated with resists at 3nm dimensions are such that it isn’t clear that chemically amplified resists will be capable of meeting requirements,” said Levinson. “If true, we would be seeing the most significant change in resist platforms in a quarter of a century. Potentially cost-reducing technologies such as directed self-assembly (DSA) are always welcome, but EUVL will be the lithographic workhorse through the 3nm node, and likely beyond.”

At 3nm, mask makers will confront the realities of higher EUV NA tools. “We will need to implement thinner mask absorbers, new films, and perhaps hard masks,” Progler said. “This puts us in a new materials regime for masks, and history has shown us the mask industry takes a long time to refine processes and tools for new mask materials.” He explained that the small scale of the mask ecosystem and the small number of large suppliers available to address the challenges accounts for this lengthy time frame.

Still, looking ahead, Progler noted that Photronics has already done a few studies on the impact of proposed half-field, high NA anamorphic optics on masks. “We uncovered some challenges that need to be addressed, particularly at boundaries and within the overall mask flow,” said Progler. As mask resolution continues to scale down, the industry will need fundamentally higher resolution mask making and inspection processes, requiring next-generation multi-beam mask writing and electron beam inspection, he explained.

At 3nm and below, Progler noted that the metrology needs for masks, while not as severe as that for wafers at these nodes, will test the mask equipment infrastructure in ways that could challenge the relatively small mask industry. “Of course, EUV multi-patterning comes into play as well, and with that, the SRAF sizes will drop below 20nm, requiring an asymmetric compensation over a much wider influence area than the OPC people are used to considering.” With EUV multi-patterning, Progler explained that it will be increasingly important to match or pair EUV masks and to consider how 3D effects and stochastics will drive new technology to enable new requirements for high-speed metrology and simulation components. “All the justifiable hand-wringing over EPE with ArF multi-patterning today gets introduced to the EUV scene when masks are ganged together to make a single device layer,” said Progler.

Originally published on the SEMI blog.

Memory devices employ a wide range of packaging technology from wire-bond leadframe and BGA to TSV.

BY SANTOSH KUMAR, Yole Développement, Lyon-Villeurbanne, France

The memory market is going through a strong growth phase. The total memory market grew by >50% YoY to more than US$125 billion in 2017 from US$79.4 billion in 2016. [1] RAM and NAND dominate the market, representing almost 95 % of standalone memory sales. There is a supply/demand mismatch in the market which is impacting on the ASP of memory devices, and as a result the large memory IDMs are reaping record profits. The memory industry has consolidated with the top five players – Samsung, SKHynix, Micron, Toshiba and Western Digital – accounting for 90% of the market.

The demand for memory is coming from all sectors but the mobile and computing (mainly servers) market is showing particularly strong growth. On average, the DRAM memory capacity per smartphone will rise more than threefold to reach around 6GB by 2022. DRAM cost per smartphone represents >10% of the bill of materials of the phone and is expected to increase further. The NAND capacity per smartphone will increase more than fivefold to reach >150GB by 2022. For servers, the DRAM capacity per unit will increase to a whopping 0.5TB by 2022, and the NAND capacity per SSD for the enterprise market will be in excess of 5TB by 2022. The growth in these markets is led by applications like deep learning, big-data, networking, AR/ VR, and autonomous driving. The automotive market, which traditionally used low density (low-MB) memory, will see the adoption of DRAM memory led by the emerging trend of autonomous driving and in-vehicle infotainment. The NOR flash memory market also saw a resurgence and is expected to grow at an impressive 16% CAGR to reach ~US$4.4 billion by 2022, due to its application in new areas such as AMOLED displays, touch display driver ICs and industrial IoTs.

On the supply side, the consolidation of players, the difficulty in migrating to advanced nodes due to technical challenges, and the need for higher investment to migrate from 2D to 3D NAND, has led to shortfall in both DRAM & NAND flash supply. DRAM players want to retain high ASPs (& high profitability) to justify the huge capex investment for advanced node migration and as such are not inclined to increase capacity. Entry of Chinese memory players will ease the supply side constraint, but it’ll not happen before 2020.

Memory device packaging

There are many variations of memory device packaging. This implies a wide range of packaging technology from the low pin count SOP package to the high pin-count TSV, all depending upon the specific product requirements such as density, performance, cost, etc. We have broadly identified five packaging platforms for memory devices: viz lead frame, wire-bond BGA, flip-chip BGA, WLCSP and TSV, even though in each platform there are many varia- tions and different nomenclature in industry.

The total memory package market is expected to grow at 4.6% CAGR2016-2022 to reach ~US$26 billion by 2022. [1] Wire-bond BGA accounted for more than 80% of the packaging market in dollar terms in 2016. Flip-chips, however, started making inroads in the DRAM memory packaging market and is expected to grow at ~20% CAGR in the next five years to account for more than 10% of the memorypackagingmarket.Currentlytheflip-chipmarket is only around 6% of the total memory packaging market. Flip-chip growth is led by its increased adoption in the DRAM PC/server segment fueled by a high bandwidth requirement.

Currently Samsung has already converted >90% of its DRAM packaging line. SK Hynix have started the conversion and other players will also adopt it in future. At Yole Développement (Yole), we believe that all DDR5 memory for PC/servers will move to flip-chip.

TSV is employed in high bandwidth memory devices requiring high bandwidth with low latency memory chips for high performance computing in various applications. In 2016 the TSV market was <1% of the total memory market. However, it is expected to grow by >30% CAGR to reach ~8% of memory packaging in dollar terms. WLSCP packaging is used in NOR flash and niche memory devices (EEPROMs/EPROM/ROM). It is expected to grow at >10% CAGR, but in terms of value will remain <1% of the market by 2022.

In mobile applications, memory packaging will mainly remain on the wire-bond BGA platform but will start to move into the multi-chip package (ePoP) for high end smartphones.

The main requirement of NAND flash devices is high storage density at low cost. NANDs are stacked using wire bonding to provide high density in a single package. The NAND packaging market is expected to reach ~ US$ 10 billion by 2022. NAND flash packaging will remain on the wire bond BGA platform and will not migrate to flip-chip. Toshiba, however, will start using TSV packaging in NAND devices to increase the data transfer rate for high end applications. Following Toshiba, we believe Samsung and SKHynix will also bring TSV packaged NAND devices into the market.

OSATs account for <20% of the memory packaging business

The total memory packaging market is estimated to have been ~US$20 billion in 2016. There are many OSATs involved in the memory packaging business, and >80% of the packaging (by value) is still done internally by OSATs. The majority of these are small OSATs and have only low-end packaging capability. Global memory IDMs have much experience in packaging, accumulated over years, and have their own internal large capacity. Therefore, there is limited opportunity for OSATs to make inroads into the packaging activity of IDMs. Many Chinese players, however, are entering the memory market with more than US$50 billion investment committed. [1] These new entrants do not have experience in memory assembly / packaging, unlike global IDMs, and they will outsource major packaging activities to OSATs. The flip-chip business for memory packaging will increase to 13% of the total market to reach US$3.5 billion in 2022. This is an opportunity for low-end memory OSATs to invest in flip-chip bumping and assembly capacity. Otherwise they will lose business to the big OSATs with advanced packaging capability.

Conclusion

The memory industry is going through a golden phase with strong demand coming from all sectors, particularly from the mobile and computing (mainly servers) markets.

Memory devices employ a wide range of packaging technology from wire-bond leadframe and BGA to TSV. Wire-bond BGA still accounts for the bulk of the memory packaging market. However, flip-chip technology will start making inroads in DRAM memory packaging and will grow at 20% CAGR (by revenue) over the next five years, accounting for ~13% of the total memory packaging market by 2022. The memory packaging market is mainly controlled by IDMs. OSATs have limited opportunity to impact IDM packaging activity. Many Chinese players, however, are entering the memory business and, unlike global IDMs, these new players lack experience in memory assembly/packaging and they outsource most of their packaging activity to OSATs.

SANTOSH KUMAR is a Senior Technology and Market Research Analyst at Yole Développement in France.

References

1. Memory Packaging Market and Technology Report 2017, Yole Développement

Photolithography of organic semiconductors is an emerging technology that can enable high resolution OLED displays.

BY PAWEL MALINOWSKI and TUNGHUEI KE, imec, Leuven, Belgium

Modern society has grown accustomed to an overflow of visual information, with displays in the center of most user interfaces. The pace of introducing new technologies and of reducing cost of manufacturing has been impressive and does not seem to slow down. The most prominent examples are OLED displays (based on organic light emitting diodes), evolving from a curiosity only some years ago to a technology that is dominating the market position today. 2017 has seen major increase in both shipments (more than 400 million units) and revenue (around $25 billion) for AMOLED display panels (according to UBI Research and DSCC).

From the very beginning of OLED history, it was crucial to find a way to maintain efficient emission in stacks composed of very fragile materials. As most of the materials used in an OLED structure are highly sensitive to a lot of elements (e.g., air, moisture, solvents, temper- ature, radiation), protecting the device has always been crucial, both during fabrication and during operation. This has evolved into several research tracks. Firstly, great effort by material companies to synthesize new molecules and polymers resulted in many OLED families, both for thermal evaporation and solution processing. Secondly, equipment advances made it possible to uniformly deposit stacks on large substrates with indus- trial takt time. Thirdly, different encapsulations were developed to protect the OLED stack during usage to ensure enough lifetime for consumer applications. All of the above required years of research and significant investments, which makes it challenging to introduce new OLED manufacturing techniques and change the existing process flows.

At the same time, current manufacturing methods have their limitations. Two main approaches are color-by- white (WOLED) and side-by-side red-green-blue (RGB OLED), differing by the way that the colors are realized in subpixels (FIGURE 1). In WOLED, the light source is a continuous layer of a broadband (white) OLED emitter and the three basic colors are selected by passing the light through color filters (CF). The advantage is that the pixel density is limited only by the backplane resolution and the CF resolution, which is why this is the main concept used for OLED microdisplays with CMOS circuitry. The disad- vantage is that significant portion of the light is lost due to CF absorption, which impacts the display power efficiency. In RGB OLED, each subpixel is a different material stack, so each subpixel is a separate light emitter. This is typically realized by depositing each stack by thermal evaporation through a fine metal mask (FMM) and is used for most smartphone OLED displays. The advantage is that each color is optimized, so the display efficiency is much higher. At the same time, it is difficult to scale the FMM technique both in substrate size (masks tend to bend under their own weight, so the motherglass has to be cut for OLED deposition) and in resolution (standard masks are not suitable for resolutions above several hundred ppi and the cross-fading area limits the aperture ratio).

An alternative way to realize side-by-side RGB pixels is to use photolithography techniques known very well from the semiconductor industry (and used in displays for the TFT backplane fabrication). In such case, after depositing a blanket OLED stack, photoresists could be used to transfer the pattern and remove the unnec- essary material by etching (FIGURE 2). The challenge here is, again, susceptibility of OLED materials to solvents – using standard (semiconductor) photo- resist chemistry results in dissolution/removal of the stack. Still, the gains are definitely worth the extra effort, as litho can provide both very high pixel density (submicron pixel pitch) and, at the same time, very high aperture ratio (emitting area maximized thanks to minimizing pixel spacing). Over the years, some new approaches for photolithography have been proposed. One way, followed by Orthogonal Inc, is to use fluorinated materials which should not have any chemical interaction with the organic stacks (thus, orthogonal to OLED). The other approach, followed by imec together with Fujifilm, is to pattern organic stacks using a non-fluorinated, chemically amplified photoresist system.

For imec, R&D hub with long traditions of devel- oping new photolithography nodes, organic photolithography is a way to address the challenges of next- generation high resolution displays. In virtual and augmented reality (VR/AR) applications, the display is very near to the eye of the user. This results in very aggressive requirements in terms of pixel density in order to avoid annoying “pixilation.” The same goes for required minimum pixel spacing, to avoid “screen door effect”. With photolithography, these two challenges can be addressed simultaneously. The OSR photoresist system from Fujifilm can deliver lines and spaces with 1 μm pitch, which fits in the roadmap towards several thousand ppi resolution for the OLED frontplane. We have realized a dot pattern transfer to OLED emission layer with 3 μm pitch, which corresponds to 8400 ppi resolution in a monochrome array. After stripping off the photoresist, the EML remains on the substrate, as verified by photolumines- cence (FIGURE 3).

On the device level, we have fabricated OLED arrays with 10 μm pixel pitch (FIGURE 4), corresponding to 2500 ppi. In this case, an important parameter is the alignment accuracy, which defines how much of the total display area can be used for emission. Another limitation is the resolution of the PDL (pixel definition layer), a dielectric layer separating the OLED stack from the bottom contact level. The resolution of this layer limits the maximum opening that can be achieved, which translates to the aperture ratio of the pixel – or the percentage of the area that is used for OLED emission. In this example, the “photo- luminescence aperture ratio”, or the relation of the OLED island to the pixel area is around 50%, which is enabled by small spacing (<3 μm). However, the “electroluminescence aperture ratio”, of the relation of the area emitting light, is 25% because of the PDL area and the necessary overlap of the OLED island. Assuming minimum line spacing of 1 μm, one can envision PL ratio of 81% (9 x 9 μm) and EL ratio of 64% (8 x 8 μm) for a subpixel of 10 x 10 μm. With such scaling, the usable area of the array can be enlarged, which results in longer device lifetime (since we can reduce the driving current density) and in reduction or elimi- nation of the screen-door effects.

Obviously, interrupting the optimum deposition process in ultra-high vacuum and exposing the OLED stack to photolithography materials has an impact on the device performance. Just breaking the vacuum results in a hit on lifetime performance. Additionally, our initial process flow includes exposure of the stack to ambient atmosphere (air and humidity), as we have been using standard cleanroom equipment. In the beginning, such “worst case scenario” resulted in proof-of-concept of emitting OLEDs after patterning, but, unsurprisingly, with device lifetime of only few minutes. In the course of the development, we have introduced improvements on three fronts. Firstly, there have been continuous upgrades of the photoresist system to make it more compatible with the organic stack. Secondly, the process flow has been optimized to reduce the impact of process parameters on device performance. Thirdly, the OLED stacks have been tuned for robustness, for example by introducing additional protection layers for the most critical interfaces. All these actions resulted in device lifetimes of several hundred hours at 1000 nit luminance. As the lifetime is the major concern when it comes to the readiness of this technology, this is an ongoing effort to bring all the parameters to a level acceptable by the industry.

In parallel to performance improvement, we have been developing a route for patterning of multicolor arrays with photolithography. The main challenge in this case is to protect the previous “color” (OLED stack) while patterning the next one. Once this condition is satisfied, side-by-side arrays with several stacks can be realized – and, this is not limited to light emitters. Next to red-green-blue OLEDs, for example an organic photo- detector subpixel could be fabricated to add functionality to the display. In terms of manufacturing, each “color” of the frontplane would be fabricated in a similar way as it is done for each layer of the backplane.

In our recent work, we fabricated a 2-color passive OLED display and this prototype was demonstrated at the Touch Taiwan 2017 exhibition (FIGURE 5). The 1400 x 1400 pixel array has a subpixel pitch of 10 μm, resulting in a resolution of 1250 ppi. The stacks are phosphorescent red and green small molecule OLEDs, deposited by thermal evaporation. The display is designed for top emission and uses glass encapsulation. Thanks to the separate driving of two groups of subpixels, the two colors can be displayed independently. The prototype has been in operation for tens of hours with all pixels turned on, with no visible degradation. This indicates that the process flow for multicolor patterning proves basic functionality and already ensures stability for reasonable working time. A similar frontplane can be integrated with a TFT or CMOS backplane, enabling then video mode of operation, with individual driving of each subpixel. In a separate demonstration, we have also verified that the fabrication process is compatible with a FPD backplane process using IGZO TFT and flexible substrate.

Taking everything into account, photolithography of organic semiconductors is an emerging technology that can enable high resolution OLED displays. Many technology milestones have been already cleared – we know that we can achieve patterns of few microns, realize side-by-side multicolor pixels, integrate the pixelated frontplane on different backplanes, and get encouraging efficiency and lifetime performance. Currently, optimization of OLED performance after patterning is still the top priority. At the same time, we are addressing the complete integration flow and manufacturability aspects. To have this technology fully incorporated in a fab process flow, material and equipment developments are required. Still, the prospect of ultra-high resolution with simultaneous high aperture ratio in a process flow based on standard semiconductor techniques remains very attractive and justifies going the extra mile to tackle the pending engineering challenges.

IC Insights will release its May Update to the 2018 McClean Report later this month.  This Update includes a discussion of the 1Q18 IC industry market results, an update of the 2018 capital spending forecast by company, and a look at the top-25 1Q18 semiconductor suppliers (the top-15 1Q18 semiconductor suppliers are covered in this research bulletin).

The top-15 worldwide semiconductor (IC and O-S-D—optoelectronic, sensor, and discrete) sales ranking for 1Q18 is shown in Figure 1.  It includes eight suppliers headquartered in the U.S., three in Europe, two in South Korea, and one each in Taiwan and Japan.  After announcing in early April 2018 that it had successfully moved its headquarters location from Singapore to the U.S. IC Insights now classifies Broadcom as a U.S. company.

The top-15 ranking includes one pure-play foundry (TSMC) and four fabless companies.  If TSMC were excluded from the top-15 ranking, Taiwan-based fabless supplier MediaTek ($1,696 million) would have been ranked in the 15th position.

IC Insights includes foundries in the top-15 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted.  With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers.  As shown in the listing, the foundries and fabless companies are identified.  In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

Overall, the top-15 list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

Figure 1

Figure 1

In total, the top-15 semiconductor companies’ sales surged by 26% in 1Q18 compared to 1Q17, six points higher than the total worldwide semiconductor industry 1Q18/1Q17 increase of 20%.  Amazingly, the Big 3 memory suppliers—Samsung, SK Hynix, and Micron, each registered greater than 40% year-over-year growth in 1Q18. Fourteen of the top-15 companies had sales of at least $2.0 billion in 1Q18, four companies more than in 1Q17. As shown, it took just over $1.8 billion in quarterly sales just to make it into the 1Q18 top-15 semiconductor supplier list.

Intel was the number one ranked semiconductor supplier in 1Q17 but lost its lead spot to Samsung in 2Q17 as well as in the full-year 2017 ranking, a position it had held since 1993.  With the continuation of the strong surge in the DRAM and NAND flash markets over the past year, Samsung went from having 5% less total semiconductor sales than Intel in 1Q17 to having 23% more semiconductor sales than Intel in 1Q18!

It is interesting to note that memory devices represented 83% of Samsung’s semiconductor sales in 1Q18, up six points from 77% in 1Q17 and up 12 points from 71% just two years earlier in 1Q16.  Moreover, the company’s non-memory sales in 1Q18 were only $3,300 million, up 6% from 1Q17’s non-memory sales level of $3,125 million.

As would be expected, given the possible acquisitions and mergers that could occur this year (e.g., Qualcomm/NXP), as well as any memory market volatility that may develop, the top-15 ranking is likely to undergo a significant amount of upheaval over the next few years as the semiconductor industry continues along its path to maturity.

By Lung Chu

Lung ChuThe growth of China’s semiconductor industry outstripped sector expansion in many other regions in 2017 thanks in part to heavy government investments and supportive state policies. But China’s chip industry also struggled under the weight of overheated investment, inconsistent project quality, insufficient investment in research and development, a poor ability to innovate, and barriers to international cooperation. To overcome these headwinds to growth, China must identify global trends in the development of global semiconductor industry and better understand the forces it needs to mobilize to further expand its own semiconductor sector.

AI and 5G fuel global semiconductor industry growth

In 2017, global semiconductor industry revenue reached a seven-year peak, expanding 22 percent to nearly USD 420 billion, and entered a new growth phase with artificial intelligence (AI), 5G and other new technologies leading the surge with greater market segmentation, diversification and decentralization. The emergence of smart automobiles, smart cities, smart medicine, AR/VR and other new markets headed the list of new applications. In the next three to five years, semiconductor industry growth is expected to remain stable, with no marked declines. In 2018, the growth rate is expected to fall to between 5 percent and 8 percent, with the expansion more comprehensive and balanced.

The memory market, in particular, will find it hard to match its 2017 blistering growth rate. The market’s expected growth of 10 percent to 20 percent will be chiefly driven by DRAM and 3D NAND Flash. In 2019, NAND growth will continue but DRAM shipments could decline.

Emphasis on both innovation and investment key to sustainable growth of Chinese IC

Under the China government’s Guidelines to Promote National IC Industry Development, designed to provide key policy guidance and capital support for the development of China’s IC industry, the Chinese semiconductor industry is seeing particularly rapid growth that is expected to be a key contributor to continuing global industry expansion. In IC design, HiSilicon and Unigroup Spreadtrum & RDA ranked among the top 10 in the world. In wafer fabrication, Chinese IC manufacturing accounted for 13 percent to 15 percent of global market capacity despite SMIC and Huahong Group lagging international competition in advanced processing. In packaging and testing – China’s strongest segment – JCET, NFME and Huatian Technology also ranked in the global top 10.

The Guidelines to Promote National IC Industry Development has fueled a boom in capital investments. However, investments must go well beyond fab construction to add new capacity for China’s semiconductor industry to flourish. A strategy for sustainable, long-term chip industry growth must focus more on technology innovation while continuing heavy capital investments, though it takes time for innovation to lead to higher capacity demand and GPD growth and more jobs.

Despite large investments by the 02 Special Project in semiconductor equipment and materials, China trails other regions of the world in advanced technologies. Global spending on semiconductor equipment reached a record-breaking USD 56 billion in 2017, with Korea a major driver. In 2017, Samsung alone invested USD 25 billion in semiconductor equipment, followed by TSMC (USD 10.8 billion), Intel (USD 11.5 billion), Hynix (USD 8.5 billion), Micron (USD 0.5 billion), SMIC (USD 2.3 billion) and YMTC (USD 2 billion). In 2018, Samsung’s equipment spending is expected to drop slightly, to USD 24 billion, while investments by Intel and TSMC will be remain roughly equal.

China’s equipment spending will continue to grow in 2018, with SMIC and YMTC maintaining investment levels similar to last year’s and other China semiconductor manufacturers starting to ramp up investments. In 2018, China is expected to surpass Taiwan in equipment spending to claim the number two position after Korea.

SIIP China dedicated to international connection and cooperation

The huge investments in China’s semiconductor industry need to be supported by robust business strategies, greater international cooperation, deeper expertise in advanced technologies, and more skilled workers. China lags the global industry in all of these areas. The rapid rise of China’s semiconductor industry has raised concerns among many countries over China’s growing influence, with some, most notably the United States, going so far as to implement containment measures. Other regions including Japan, Korea and Taiwan followed suit.

The continued growth of China’s semiconductor industry hinges on technological innovation enabled by international cooperation, as well as strong international communication to allay concerns and misunderstandings over the rising prominence of China’s chip sector. China must overcome these obstacles. One partial solution is for China to convince the rest of the world that its need a thriving semiconductor industry if only to meet enormous demand for electronics products within its own borders.

As the largest international semiconductor industry association, SEMI enjoys a unique ability to strengthen the connection between China’s semiconductor sector and its international counterparts. SEMI is well-known for its vital support of the traditional semiconductor equipment and materials markets, but SEMI’s work also spans IC design, manufacturing, packaging and testing. What’s more, SEMI has expanded into innovative market vertical applications such as AI, smart manufacturing, smart transportation and smart automotive as it aims to bring together supply chains across these growth areas.

For its part, SEMI China remains dedicated to improving communications and cooperation between the Chinese and global semiconductor industries. SEMI China will also continue to encourage deeper collaboration among individual enterprises and government institutions in the interest of industry growth while making full use of SEMI’s international, professional and localization platform to promote the development of China’s semiconductor industry.

Last year, we established SEMI Innovation Investment Platform (SIIP) China to help grow China’s pool of skilled workers, promote advanced technology, generate industry capital, and expand China’s semiconductor industry while developing stronger connections with chip sectors in other regions. SIIP China is focused on the following:

  • Promoting sustainable development of the Chinese semiconductor industry
  • Establishing stronger connections to help take advantage of global technology and investment opportunities
  • Providing a platform for open communications between the Chinese and global semiconductor industries
  • Promoting greater coordination between China and its global partners
  • Helping newly enterprises secure funds for expansion

Encouraging greater cooperation with foreign semiconductor manufacturers in the interest of openness and mutual benefit will be the best way for China to overcome obstacles to the development of its semiconductor industry. Meanwhile, China will continue to strive to merge into the global semiconductor industry and become a key partner.

SEMICON China has witnessed the development of Chinese semiconductor industry

SEMICON China-1

SEMICON China marked its 30th anniversary this year. Over the past three decades, China’s semiconductor industry has seen remarkable growth. This year’s SEMICON China was the largest ever. SEMICON China and FPD China 2018 numbered 3,628 booths, covered 74,000 square meters of exhibition space and attracted 1,116 exhibitors from 21 countries and regions and 91,252 professional attendees from 58 countries and regions.

Most of China’s top device makers and global leading packaging houses, together with their equipment and materials suppliers, exhibited at SEMICON China and FPD China 2018, representing the global IC manufacturing ecosystem. The number of SEMICON China and FPD China 2018 visitors jumped 32.3 percent from last year, with representation by professionals from the design, manufacturing, assembly and test, equipment and materials sectors.

Lung Chu is President of SEMI China.

Originally published on the SEMI blog.

The top 10 IC suppliers in the $54.5 billion analog market last year accounted for 59% of the category’s worldwide sales in 2017, according to a recent monthly update to IC Insights’ 2018 McClean Report. Collectively, the top 10 companies generated $32.3 billion in analog IC sales last year compared to $28.4 billion in 2016, which was a 14% increase and a gain of two percentage points in marketshare during 2017, said the 50-page April Update to The McClean Report.  Eight of the top-10 suppliers exceeded the 10% growth rate of the total analog market in 2017, according to the update.

With analog sales of $9.9 billion and 18% marketshare, Texas Instruments was again the leading supplier of analog integrated circuits in 2017.  In 2016, TI’s marketshare was 17% in analog ICs.  The company’s analog sales increased by about $1.4 billion last year—rising 16%—compared to 2016 and were more than twice that of second-ranked Analog Devices (ADI). TI’s 2017 analog revenue represented 76% of its $13.0 billion in total IC sales and 71% of its $13.9 billion total semiconductor revenue, based on IC Insights’ estimates.

3fed36cb-49c2-4a3f-a24c-a5fd1acf60c4

Figure 1

TI was among the first companies to manufacture analog semiconductors on 300mm wafers.  TI has claimed that manufacturing analog ICs on 300mm wafers gives it a 40% cost advantage per unpackaged chip compared to using 200mm wafers.  In 2017, about half of TI’s analog revenue was generated on devices built using 300mm wafers.

Second-place ADI registered a 14% increase in analog IC sales in 2017 to $4.3 billion, according to IC Insights’ supplier ranking. The 2016 and 2017 revenue numbers shown for ADI include sales from Linear Technology, which was acquired by the company in 1Q17 for $15.8 billion.

NXP was the only supplier in the top-10 ranking that experienced a decline (-1%) in its analog sales last year.  Some of NXP’s analog revenue decline can be attributed to the sale of its Standard Products business to a consortium of Chinese investors consisting of JAC Capital and Wise Road Capital.  The $2.75 billion transaction was completed in February 2017.  The Standard Products business was renamed Nexperia and headquartered in the Netherlands.

Among the top 10, ON Semiconductor showed the largest analog sales gain in 2017, with revenues increasing 35% to $1.8 billion, which represented a 3% share of the market.  This follows a 16% rise in its analog sales in 2016. Some of the strong increases in sales during the last two years were a result of ON Semi’s acquisition of Fairchild Semiconductor in September 2016 for $2.4 billion.  ON’s analog business was also boosted in 2017 by record sales of its power management products to the automotive market, specifically for active safety, powertrain, body electronics, and lighting applications.