October 18, 2012 – SPTS Technologies has signed a joint development program with the Fraunhofer Institute for Reliability and Microintegration (Fraunhofer-Institut f
Tag Archives: Advanced Packaging
October 12, 2012 – The advent of leading-edge semiconductor packaging technologies dictates efficient use of capital, and only the top-tier companies will have the financial wherewithal to develop required expertise and capacity. That means consolidation needs to happen in the semiconductor assembly and test services (SATS), according to a recent report from Gartner.
IDMs started moving packaging plants into the Asia-Pacific region in the 1980s, and by the early 1990s outsourced packaging had bloomed, and gained speed with the emergence of the fabless/foundry model, explains Gartner analyst Jim Walker in a recent report ("Competitive Pressures Will Bring Consolidation to the SATS Market"). Over the past 10 years outsourcing has accelerated with proliferation of customized, application-specific packaging demand, and today the market has quintupled since 1997 to $25B, with nearly all the 130 SATS companies still in the greater Asia-Pacific region (including Japan).
Right now the SATS market is on a 8% CAGR trajectory from 2011-2016, but growth on an annual basis is slowing, Walker notes. The top five SATS companies currently comprise 50% of the market and will expand to nearly 60% by 2012 — that’s five out of more than 130 suppliers. The top 20 SATS companies comprise more than three-fourths of the market.
Top 10 SATS companies in 2011, sales as a percentage of total market. (Source: Gartner)
Consolidation is not only inevitable, it is sorely needed. Several factors will push these firms together:
- Slower growth, due to market saturation. Crossing the 50% outsourcing saturation mark in 2011 implies that the total market available for packaging services from IDM, OEM, and fabless companies is shrinking, and will be more tied to industry unit growth and new business sectors.
- Increasing competition at leading-edge technology nodes, and in niche markets. The process node migration continues (28nm, 20nm, 14nm, eventually 10nm and below), as does increased demand for mobile devices, which together necessitate more packaging technology and capacity for capabilities including WLP, flip-chip, through-silicon via (TSV), and redistribution layers. Those who can stomach the capital requirements for these, will stay on top — and those who cannot will find themselves on the losing end.
Similarly, as the outsourcing sector aligns to industry unit growth, SATS companies focusing on specific markets (e.g. memory) are more exposed to narrow, commodity-like and price-sensitive market forces. Such companies need to expand on their own into other markets, or consolidate with bigger and broader SATS companies. See recent expansion/divestment news from PTI, Power ASE, SPIL, and ChipMOS. (In fact this trend could spell the end of memory-specific packaging and test services market, Walker notes.)
- Continued efforts by IDMs and OEMs to outsource backend processes. Technology investments and capacity additions are a hard sell when utilization rates are low (or aren’t at full strength). The proliferation of packaging options (Gartner cites >2000 unique packages) is forcing OEMs/IDMs to rethink sharing capital investments, deciding to leave it to the outsourced "experts."
- Increasing importance of a China market strategy. Most top 10 SATS companies have at least one Chinese manufacturing facility, initially taking advantage of cost savings and incentives. But now, recognizing China’s swelling appetite for electronics components and systems, SATS firms want and need those domestic capabilities to satisfy demand. ASE, for example, has led the way in defining a strategy that straddles operations in both Taiwan and China, including $1.2B to build up operations in Shanghai and Pudong.
Continued emergence and development of wafer-based packaging process technologies requires both wafer fabrication and semiconductor packaging manufacturing equipment, processes, and expertise — meaning foundries can do some of them too, such as wafer bumping and underbump metallization. Similarly, 3D package stacking, embedded components, and system-in-package (SiP) devices require both processes and technologies for packaging and printed circuit board assembly — and technologies such as system-on-package will further blur these roles. SATS firms should expect to see increased competition from the foundry market, Walker notes. They also need to expand their services to include test capabilities, package design, and module offerings. And perhaps most importantly, they need to get virtual or vertical — develop an acquisition plan or partnerships/joint ventures with foundries, EMS/ODM firms, and/or materials and equipment companies, he advises.
October 10, 2012 – Nanium says it has shipped its 200 millionth embedded wafer-level ball grid array technology (eWLB) component, a milestone reached in less than two years. The achievement represents a 10% year-over-year productivity increase, and reflects full conversion to the company’s eWLB overmold technology that allows both thinner and more robust packages, according to the company.
The shipment milestone "demonstrates that eWLB technology is a robust low-cost solution delivering both high reliability and high yields for manufacturing advanced electronic products with high I/O density in a small form-factor," stated Armando Tavares, president of NANIUM
October 5, 2012 – Tessera Technologies (Nasdaq:TSRA) is giving CEO Robert A. Young a big financial incentive to spin off one of its two businesses within the next several years, one of the company’s key long-term strategic goals. The directive, issued by the board of directors and compensation committee, authorizes immediate vesting of 550,000 stock options at their Oct. 2 pricing, worth roughly $7.54M. It’s contingent on successful spin-out of one of the company’s business units by March 31, 2015; if no spinoff happens by that date, the promised stock options will expire.
"The 2012 compensation arrangement provides an additional financial incentive for Bob to pursue a key strategic alternative, and reflects the board’s continuing efforts to closely align executive compensation with the best interests of stockholders," stated company chairman Robert J. Boehlke.
Tessera Technologies is a holding company with operating subsidiaries in two segments. Its Intellectual Property unit handles license agreements with semiconductor companies and outsourced semiconductor assembly and test companies, while a Digital Optics division covers imaging and optics products and capabilities.
Reuters quotes Tessera’s newly appointed CFO, Richard Neely, suggesting the strategy centers on the digital optics side of the business: "We’ve been talking about building up the digital optics business and spinning it off." He was hired in August 2012 to build up the Digital Optics business "into a global, vertically integrated supplier of original design camera modules for handsets and other applications," while also helping grow the IP licensing business.
In a related SEC filing, Tessera reveals more of the incentive plan, as well as more details of Young’s overall compensation scheme — including his base annual salary ($684,000), potential annual bonuses equaling that salary, and $150,000 per year to offset expenses from traveling between his Connecticut home and the company’s offices in California.
Tessera currently projects 3Q12 sales of $66.5M-$69.0M, up 8%-12% from 2Q12. Most of that is in the IP licensing side ($53.0M-$54M, flat with 2Q), helped by a recent settlement with Amkor Technology. The digital optics business is expected to generate $13.5M-$15.0M in sales in 3Q, up from $8.4M in 2Q12.
September 27, 2012 – Researchers at the Karlsruhe Institute of Technology (KIT) say they have developed a novel optical connection process for semiconductors using "photonic wire bonding" and femtosecond lasers, that achieves data transmission rates of several Tbit/sec.
Developing and integrating high-performance optical emitters and receivers onto semiconductors is already a reality, but it’s been harder to figure out how to actually bridge chips optically. "The biggest difficulty consists in aligning the chips precisely such that the waveguides meet," explains Christian Koos, professor at the KIT Institutes of Photonics and Quantum Electronics (IPQ) and of Microstructure Technology (IMT) as well as member of the Center for Functional Nanostructures (CFN).
So he and his team looked at the problem from the other side: arrange the chips and then structure a polymer-based optical waveguide. They developed a method for 3D structuring of an optical waveguide using high-resolution, two-photon polymerization — a femtosecond laser writes the freeform waveguide structure directly into a polymer on the surface of the silicon-on-insulator chips. (Specifically they used laser lithography from Nanoscribe, a KIT spinoff.) Importantly, this means the interconnection adapts to the chip’s position and orientation, so such restrictive alignment isn’t necessary from the beginning — making this process more suitable for industrial production scale-up.
Prototypes of the photonic wire bonds were said to have very small losses and very high transmission bandwidth in the range of IR telecommunications (1.55
September 19, 2012 – SPTS Technologies has introduced a low-temperature plasma-enhanced chemical vapor deposition (PECVD) system for via-reveal passivation in 3D IC packaging. The Delta fxP cluster system deposits dielectric layers onto bonded substrates at wafer temperatures below 200
September 10, 2012 – EV Group (EVG), St. Florian, Austria, has updated its modular EVG 150 automated resist processing system to address specific needs for backend lithography, conformal coating, and planarization. The new system was announced at last week’s SEMICON Taiwan.
The newest version of the EVG150 high-volume coater/developer performs spin coating, developing, spray coating and lift off on 50-200mm wafers, enabling up to four wet process modules combined with two stacks of hot plates, chill plates, and vapor prime modules. Two key additions include EVG’s OmniSpray technology (with proprietary ultrasonic nozzle), which allows the conformal coating of high topography surfaces (e.g. ultra-thin, fragile, or perforated wafers) and can result in up to 80% reduced material consumption vs. traditional spin coating, according to the company. The other key addition is the NanoSpray coating technique to coat surfaces with vertical sidewall angles — for example, processing through-silicon vias (TSV) with polymer liners and photoresist.
EVG reps summarized the additions for SST:
- A modular design allowing roll-in/-out of process modules, for enhanced uptime and serviceability
- A new spray coating module (the company’s OmniSpray technology) with x,y (raster) spray coating
- A new module for the company’s proprietary "NanoSpray" process for coating blind vias
- A new structural frame with most chemicals stored within the main frame, to shorten point-of-use and optimize process control
- CIM Framework software, to help meet rigorous requirements for uptime, process control, and fab automation
"Close collaboration with our customers made it clear that the next logical step for our coater/developer technology was to create a universal approach for high-volume processing of devices with more complicated structures and topographies," stated Markus Wimplinger, EV Group’s corporate technology development and IP director.
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spraycoated cavity (cavity 150
September 6, 2012 – Rudolph Technologies says it has received an order for its MetaPulse G metrology system from "a premier global industry research center in Asia" for its advanced packaging process development activities.
The unidentified group will use the system, which shipped in August, for thin-film metrology performed in development and control of advanced wafer-level packaging processes that use metal structures, such as redirect layers (RDL) and under bump metallization (UBM) to route signals from the chip to the package.
"In addition to providing the fast and accurate measurements of thickness, density and roughness, its small spot size and ability to measure structures directly on product wafers allow users to see pattern dependent variations that are not detectable with monitor wafers," according to Tim Kryman, Rudolph
September 4, 2012 – Ultra Tec Manufacturing has released a new endpoint detection module for its ASAP-1 IPS selected area preparation system, for improving electronic package decapsulation and sample preparation.
The patent-pending hardware/software enhancement to the ASAP-1 IPS provides the capability to quantify and act upon the capacitive and/or resistive properties of electronic device and packaging materials, in order to enhance the sample preparation process. Such "controlled microsurgery" with interactive endpinting opens the door for improved resolution in various microscopy techniques (SQUID, INSB thermography/lock-in, thermal laser stimulus) without fully exposing the die topside or by stopping a few microns before target on silicon from the backside.
Ultra tec’s ASAP-1 IPS is a digital sample preparation system for the decapsulation, thinning and polishing of packaged and wafer-level devices. The new endpoint module will be available for demos at the upcoming International Symposium for Testing and Failure Analysis (ISTFA) conference in Phoenix, AZ, Nov. 11-15).
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