Tag Archives: Advanced Packaging

January 9, 2012 — Multitest, semiconductor test equipment provider, qualified its UltraFlat process for high parallel vertical probe card tests. UltraFlat provides permanent overall PCB flatness for better wafer-level test.

For applications such as DDR3 memory, board flatness is crucial at wafer-level testing. For optimizing MLO/MLC attachments and contact element interfaces, a better surface is needed. Additionally, flatter PCBs require less compliance from the probe interface and reduce interface wear.

UltraFlat is based on PCB stack up engineering and PCB construction technologies, allowing for a very tight overall flatness tolerance to be maintained by removing bows/twists in the PCB. The technique creates a permanent overall flatness, unlike baking techniques that are temporary, Multitest reports.

With UltraFlat, Multitest typically is able to comply with bow/twist requirements of 1.0%.

Multitest manufactures test handlers, contactors, and ATE printed circuit boards for semiconductor test. For more information, please visit www.multitest.com/pcb.

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January 6, 2011 — Wedge and wire bonder maker Hesse & Knipps Inc., the Americas subsidiary of Hesse & Knipps Semiconductor Equipment GmbH, launched its next-generation BONDJET BJ93X heavy wire bonder for back-end semiconductor assembly, targeting manufacturers of power semiconductors and automotive electronics.

Hesse & Knipps will demo the wire bond tool at APEC 2012, February 6-9 in Orlando, FL (http://www.apec-conf.org/), Booth 914.

The BONDJET BJ93x heavy wire bonders feature a heavy wire bond head with integrated pull test and 305 x 410mm table travel for automotive electronics and power semiconductor interconnect requirements. The BONDJET BJ920 handles aluminum, gold and copper heavy round wire and ribbon wire at speeds of 3 wires/sec. Patented PiQC Process Integrated Quality Control analyzes 5 critical measurements of bond quality in real time for every bond

January 5, 2012 — Standards org JEDEC Solid State Technology Association released a new standard for wide I/O mobile DRAM: JESD229 Wide I/O Single Data Rate (SDR). Wide I/O mobile DRAM increases die integration — stacking chips with through silicon via (TSV) interconnects with a system on chip (SoC) — and improves bandwidth, latency, power, weight and form factor.

The standard defines features, functionalities, AC and DC characteristics, and ball/signal assignments. It is particularly well-suited for applications requiring extreme power efficiency and increased memory bandwidth (up to 17GBps). Wide I/O offers twice the bandwidth of the previous generation standard, LPDDR2, at the same rate of power consumption.

Also read: IPC, JEDEC devise package strain test and JEDEC releases serial NOR Flash standard

Mobile wide-I/O DRAM are used in smartphones, tablets, handheld gaming consoles and other mobile devices. Sophie Dumas, Chairman of the JC-42.6 Subcommittee for Low Power Memories, notes that the high-resolution displays, high-quality graphics, and multi-tasking capabilities of next-gen devices require technologies like wide-I/O mobile DRAM.

JESD229 may be downloaded free of charge from the JEDEC website at http://www.jedec.org/sites/default/files/docs/JESD229.pdf.

JEDEC develops standards for the microelectronics industry. All JEDEC standards are available online, at no charge. For more information, visit www.jedec.org.

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January 5, 2012 — Haruo Matsuno, president and CEO of Advantest Corporation (TSE:6857, NYSE:ATE) announced the company’s major goals in his New Year’s address to employees and stakeholders.

By fiscal year (FY) 2014, Advantest plans to bring in revenue of 250 billion yen, over 20% operating margin, and have over 50% total market share of semiconductor test systems and test handlers. The $1B acquisition of Verigy in 2011 boosted Advantest’s offering for memory and SoC customers, Matsuno said when the deal was announced. It combined Advantest’s strength in memory semiconductor test systems and mass production lines and Verigy’s strength in non-memory semiconductor test systems and R&D.

"To reach out new targets above and maximize synergies from the Verigy integration, we will spark innovation in all areas," said Matsuno, pointing to a new business model utilizing cloud computing, flexible productions processes, and a global marketing and organizational structure.

Outside of semiconductor test products, Advantest will bring its measurement technologies into scanning electron microscopes (SEM), electron beam (e-beam) lithography, RF measurement devices, MEMS switches, terahertz analysis systems, and healthcare products.

Advantest manufactures electronic measuring instruments, automatic test equipment, and electron beam lithography systems. Learn more at www.advantest.co.jp.

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Update February 1, 2012 – BUSINESS WIRE — Tessera Technologies, Inc. (NASDAQ:TSRA) announced that, after a series of discussions with Starboard Value LP, together with its affiliates, Starboard has agreed in writing to rescind its nomination notice for the election of directors at the upcoming 2012 Annual Meeting of Stockholders.

"After constructive discussions with Tessera Technologies, Inc., we have decided not to move forward with the nomination of directors at the 2012 annual meeting. Based on the Company

January 3, 2012 – PRNewswire — Packaging equipment provider NEXX Systems sold a 300mm Stratus electrochemical deposition (ECD) system to Powertech Technology (PTI), a major IC packaging and testing company in Taiwan. PTI will use the Stratus to make copper pillar bumps and re-distribution layers (RDL) for portable intelligent device packages, targeting smart phone and tablet PC applications.

The tool will be evaluated for PTI’s through silicon via (TSV) commercialization program.  

Also read: Nantong Fujitsu Microelectronics installs NEXX tool for copper pillar, RDL packaging

PTI is primarily known for memory device assembly, in high volumes, supplying integrated device manufacturers (IDMs) and fabless companies, said Scott Jewler, Senior General Manager, PTI. Jewler expects that the new deposition tool will help PTI lower the cost of leading-edge packaging.

NEXX Systems offers electrochemical deposition and physical vapor deposition systems for advanced semiconductor packaging. Learn more at www.nexxsystems.com.

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December 30, 2011 — As the semiconductor industry moves into the 22nm silicon technology node, device fabrication is not the only challenge that the industry will face. According to the International Technology Roadmap for Semiconductors (ITRS), a porous ultra-low-k (ULK) material will replace the traditional silicon dioxide. Stresses within the die must be controlled, not only during wafer fabrication, but also in packaging and assembly.

This will be even more challenging than the industry

December 29, 2011 – At the recent 7th annual RTI 3-D Architectures for Semiconductor Integration and Packaging (3D ASIP) Conference in Burlingame CA, the "buzz" centered around the presentation by TSMC‘s Doug Yu, senior director of integrated interconnect, who repeated the case he had made at the November Georgia Tech Interposer Conference [see "2.5D announcements at the Global Interposer Tech conference"] for the pure foundry model for 2.5 and 3DIC — claiming that TSMC was readying to take on full beginning to end interposer manufacturing.

Yu told the audience of more than 200 that sharing the fabrication process with OSATs is not the preferred option for TSMC, because "the risk for the customer is too high […] therefore we [TSMC] will take full responsibility and accept full risk." TSMC is proposing that such one stop shopping will be simpler, cheaper and more reliable than using multiple sources (i.e. foundries, assembly houses and potentially other partners). Yu remained steadfast in his assessment that the required investments and the technology needed to handle thinned wafers would require that the foundries take control of such processing: "This is a new ballgame; the old ways of doing business are out of date for this new technology." On rumors that TSMC is currently working with only a handful of 2.5D/3D customers (including Xilinx); he indicated that "new customers will have only the integrated solution proposal […] some, but not all of them [customers] want us to work with other partners, but many like our new approach very much."

Certainly with customer Xilinx being first to enter the 2.5D market space, TSMC appears ahead of the rest of the foundries in this regard. Ivo Bolsens, VP and CTO of Xilinx detailed the company’s Virtex 2000T FPGA product which he claims delivers 4