Tag Archives: letter-semi-tech

At its annual Imec Technology Forum USA in San Francisco, imec today presented an electrically functional solution for the 5nm back-end-of-line (BEOL). The solution is a full dual-damascene module in combination with multi-patterning and multi-blocking. Scaling boosters and aggressive design rules pave the way to even smaller dimensions.

As R&D progresses towards the 5nm technology node, the tiny Cu wiring schemes in the chips’ BEOL are becoming more complex and compact. Shrinking the dimensions also reduces the wires cross-sectional area, driving up the resistance-capacitance product (RC) of the interconnect systems and thus increasing signal delay. To overcome the RC delay challenge and enable further improvements in interconnect performance, imec explores new materials, process modules and design solutions for future chip generations.

Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

One viable option is to extend the Cu-based dual-damascene technology – the current workhorse process flow for interconnects – into the next technology nodes. Imec has demonstrated that the 5nm BEOL can be realized with a full dual-damascene module using multi-patterning solutions. With this flow, trenches are created with critical dimensions of 12nm at 16nm.  Metal-cuts (or blocks) perpendicular to the trenches are added in order to create electrically functional lines and then the trenches are filled with metal. Area scaling is further pushed through the introduction of fully self-aligned vias. Moreover, aggressive design rules are explored to better control the variability of the metal tip-to-tips (T2Ts).

Beyond 5nm, imec is exploring alternative metals that can potentially replace Cu as a conductor. Among the candidates identified, low-resistive Ruthenium (Ru) demonstrated great promise. The imec team has realized Ru nanowires in scaled dimensions, with 58nm2 cross-sectional area, exhibiting a low resistivity, robust wafer-level reliability, and oxidation resistance – eliminating the need for a diffusion barrier.

“The emergence of RC delay issues started several technology nodes ago, and has become increasingly more challenging at each node. Through innovations in materials and process schemes, new BEOL architectures and system/technology co-optimization, we can overcome this challenge as far as the 5nm node,” said Zsolt Tokei, imec’s director of the nano-interconnect program. “Imec and its partners have shown attainable options for high density area scaled logic blocks for future nodes, which will drive the supplier community for future needs.”

For the longer term, imec is investigating different options including but not limited to alternative metals, insertion of self-assembled monolayers or alternative signaling techniques such as low-energy spin-wave propagation in magnetic waveguides, exploiting the electron’s spin to transport the signal. For example, the researchers have experimentally shown that spin waves can travel over several micrometers, the distance required by short and medium interconnects in equivalent spintronic circuits.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC.

Sono-Tek Corp. unveiled a new photoresist ultrasonic coating system in Booth #2146. The new photoresist coating system, SPT200, has been designed specifically to meet the unique challenges of coating high aspect ratios and deep well topographies such as MEMS wafers with photoresist.

The SPT200 replaces traditional spin coating equipment, providing more uniform coverage of side walls in difficult to coat applications. Ultrasonic spray has been used for photoresist deposition for years, and is a well proven method for semiconductor lithography manufacturing.

SPT200 is typically configured with Vortex or AccuMist ultrasonic spray shaping nozzles, depending upon coating requirements. Sono-Tek’s team of application engineers ensures the correct configuration for each process. At the heart of the system is Sono-Tek’s patented ultrasonic nozzle technology. All ultrasonic nozzles feature up to 95 percent reduction in material consumption, non-clogging performance, and precise, targeted spray patterns at ultra-low flow rates.

SPT200 unique system features include:
• Automated spray coating with recipe storage
• Designed for 100, 150, 200, and 300mm wafers
• Precision temperature control
• Integrated wafer lockdown
• Highly repeatable syringe pump with auto refill
• Manual wafer load/unload
• Highly repeatable, stable process

Sono-Tek has application expertise in depositing photoresist onto MEMS and other semiconductor wafer substrates.

Pall Corporation announced this week the availability of its new 5nm XpressKleen filter. The filter is the latest addition to the company’s XpressKleen chemical filter line-up and is a key component of Pall’s disposable PFA (Perfluoroalkoxy alkanes) KleenChange assemblies. The new 5 nm XpressKleen filter is designed to meet the growing defectivity challenges of sub-10nm critical chemical processing. It demonstrates finer retention, fast flow, and higher purity than previous filters. Retention is validated using Pall’s gold nanoparticle challenge test.

“The 5 nm XpressKleen filter leverages Pall’s proprietary ‘XP’ cleaning process that reduces trace metal contamination by 50% to less than 500 parts per trillion (ppt) total for nineteen critical metal ions for a ten-inch device,” said Steve Chisolm, President of Pall Microelectronics. “The ‘XP’ cleaning process also removes organics, surface particles, and anions. Pall is proud to bring these important purity and retention capabilities to the market to enable the semiconductor scaling cadence.”

Pall’s completely integrated manufacturing capability extends from PTFE resin to the finished filter device. The company’s advanced manufacturing process uses clean room manufacturing and statistical process control to ensure the reliability and performance of every 5nm XpressKleen filter.

By Ed Korczynski, Sr. Technical Editor

Medical and health/wellness monitoring devices provide critical information to improve quality-of-life and/or human life-extension. To meet the anticipated product needs of wearable comfort and relative affordability, sensors and signal-processing circuits generally need to be flexible. The SEMICON West 2016 Flexible Electronics Forum provided two days of excellent presentations by industry experts on these topics, and the second day focused on the medical applications of flexible circuits.

Flexible ultra-thin silicon

While thin-film flexible circuits made with printed thin-film transistors (TFT) have been developed, they are inherently large and slow compared to silicon ICs. Beyond dozens or hundreds of transistors it is far more efficient to use traditional silicon wafer manufacturing technology…if the wafers can be repeatedly thinned down below 50 microns without damage.

Richard Chaney, general manager of American Semiconductor, presented on a “FleX Silicon-on-Polymer” approach that provides a replacement polymer substrate below <1 micron thin silicon to allow for handling and assembly. Processed silicon-on-insulator (SOI) wafers are front-side temporarily bonded to a “handle-wafer”, then back-side grinded to the buried oxide layer, then oxide chemically removed, and then an application-specific polymer is applied to the backside. After removing the FleX wafer from the handle-wafer, the polymer provides physical support for dicing and the rest of assembly.

For the last few years, the company has been doing R&D and limited pilot production by shipping lots of wafers through partner applications labs, but in the second-half of 2015 acquired a new manufacturing facility in Boise, ID. Process tools are being installed, and the first product dice are “FleX-OPA” operational amplifiers. Initial work was supported by the Air Force Research Laboratory (AFRL), but in the last 12-18 months the company has seen a major increase in sample requests and capability discussions from commercial companies.

Printed possibilities

Bob Street of Xerox’s Palo Alto Research Center (PARC) presented on “Printed hybrid arrays for health monitoring.” There are of course fundamentally different sensor needs for different applications, and PARC is working on many thin-film transducers and circuits:

Gas sensing – outer environment or human breath,

Optical sensing – monitoring body signals such as blood oxygen,

Electrochemical sensing – detect specific enzymes, and

Pressure/Accelerometers – extreme physical conditions such as head concussions

“There are many and various ways that you can do health monitoring,” explained Street. “There will be sensors, and local electronics with amplifiers and logic and switches. One of the prime features of printing is that it is a versatile system for depositing different materials.”

PARC has built an amazing printing system for R&D that includes different functional dispense heads for ink-jet, aerosol, and extrusion so that a wide varieties of viscosities can be handled. The system also include integrated UV-cure capability. Printing tends to have the right spatial resolution on the scale of 50-100 microns for the target applications spaces.

PARC worked on an early system to monitor for head concussions and store event information. They used printed PVDF material to print accelerometers and pressure sensors, as well as ferroelectric analog memory. Various commercially available materials are used to print organic thin-film transistors (OTFT) for digital logic. For complementary digital logic, different metals would conventionally be needed for contacts to the n-type and p-type TFTs, but PARC found an additive layer that could be applied to one type such that a single metal could be used for both.

A gas sensor prototype that can can detect 100-1000ppm of carbon-monoxide was printed using carbon nano-tubes (CNT) as load resistors. They printed a 4-stage complementary inverter to provide gain, using 7 different materials. “This is a case where a very simple device uses many layers,” explained Street. “Four drops of one materials does it, so you wouldn’t look at using a subtractive process for this.”

Rigid/flex integration

Dr. Azar Alizadeh, GE Global Rsearch, presented on “Manufacturing of wearable sensors for human health & performance monitoring.” Wearables in healthcare applications include medical, high exertion, occupational, and wellness/fitness. The Figure shows a flexible blood pressure-sensor that measures from a finger-tip. Future flexible devices are expected to provide more nuanced biometric information to enable personalized medicine, but any commercially viable disposable device will have to cost <$10 to drive widespread adoption. Costs must be limited because just in the US alone the annual amount spent to serve ~50M patients in hospitals is >$880B.

Finger-tip optical blood-pressure sensor created with printed photodetector by GE Corp.

Finger-tip optical blood-pressure sensor created with printed photodetector by GE Corp.

By Shannon Davis, Web Editor

Kateeva is out to change the way displays are being made, and during Tuesday’s Silicon Innovation Forum keynote, Kateeva President and COO Conor Madigan, PhD, laid out how their YIELDJet inkjet system is making that happen.

In recent years, OLED displays have captured the imagination of the industry because of the materials’ capability to enable new kinds of form factors, specifically flexible displays. One of the compelling characteristics of OLED is designers can make a display on a thin piece of plastic, freeing them from rigid glass.

Another compelling aspect, Madigan explained, is that OLED displays have fewer subcomponents than their LCD counter parts, so manufacturing cost can be lower. And he believes inkjet technology will play a key role in making OLED more affordable. His company, Silicon Valley-based Kateeva, has focused their efforts on developing an inkjet platform for OLED manufacturing called YIELDJet, a completely different style of inkjet system.

Kateeva’s YIELDJet inkjet printing platform.

Kateeva’s YIELDJet inkjet printing platform.

When the concept of flexible OLEDs was first catching on, designers had some significant manufacturing obstacles to overcome, Madigan explained. Designers in R&D were using vacuum-based technique for depositing the films in the OLED structure.

“It was very slow; it required planarization to make a smooth surface, and this didn’t do that well,” said Madigan. “There were many particle defects, and the cost was high.”

Kateeva worked with adapting inkjet technology to this process. Madigan explained that YIELDJet uses individual droplets of ink in a pattern, merges that ink together, and then uses UV lights to cure into a single layer, which has improved the quality of the films.

“Nowadays, we’re focused on broadly enabling low cost, mass production OLEDs with inkjet printing,” Madigan said. “What we’re working on now is a general deposition platform for putting down patterned films at high speed over large areas, realizing the full potential of inkjet technology for the display industry.”

In developing Kateeva’s YIELDJet, Madigan said they focused on how the glass would be handled, how to perform maintenance on a printer system that would be completely enclosed in a nitrogen environment, and managing particle decontamination.

YIELDJet employs a technique that floats a panel of glass on a vacuum and pressure holds, holding it at the very edge, which significantly reduces the size of the system when compared to conventional system which requires glass be moved on a large, often bulky holder. To address accessibility of their complicated system, Kateeva engineers made the system fully automated and able to recover quickly if it needed to be opened up to air.

“It was a new thing to make a printer that was low particle contaminating,” said Madigan. “In one of these printers, you have about ten thousand nozzles, to do fast coating.”

Kateeva was able to develop techniques to monitor all of these nozzles simultaneously, resulting in completely uniform coatings and films.

“The analysis that we’ve done with our customers is that, once they can move to inkjet printing, then you’ll quickly see OLED come down to cost parity and even be below LCD in cost,” Madigan concluded.

By Pete Singer, Editor-in-Chief

N2O, or Nitrous Oxide, also known as laughing gas, is a weak anesthetic gas that has been in use since the late 18th century. Most people have experienced nitrous in the context of dentistry, but it’s also used to make whipped cream, in auto racing, deep sea diving, or – in the semiconductor industry — as the oxygen source for chemical vapor deposition (CVD) of silicon oxy-nitride (doped or undoped) or silicon dioxide, where it is used in conjunction with deposition gases such as silane. It’s also used in diffusion, rapid thermal processing and for process chamber treatments.

The problem – and why it’s no laughing matter – is that after CO2 and CH4, N2O is the 3rd most impactful man-induced greenhouse gas (GHG), accounting for 7% of emissions. According to the U.S. Environmental Protection Agency, 5% of U.S. N2O originates from industrial manufacturing, largely semiconductor manufacturing. “It’s very much of interest because of its high global warming potential, combined with its long atmospheric lifetime of over 100 years,” said Mike Czerniak Environmental Solutions Business Development Manager, Edwards. “After PFCs, this is one of the most impactful gases from semiconductor manufacturing.” With a TLV of 50ppm, N20 is also poses a health risk.

There are two ways to get rid of N2O: reducing and oxidizing. “Reducing means getting rid of the oxygen in it so you just drive it down to be nitrogen, or you can oxidize it and add additional oxygen to it,” Czerniak explained.

Oxidizing is the easier approach in that it involves putting the gas through an ordinary flame. “The problem with doing this is you then make nitrogen oxides, NOx, and that generally is very bad because that’s the gas that’s the acid rain contributor and it also does nasty things to people,” Czerniak said. When NOx and volatile organic compounds (VOCs) react in the presence of sunlight, they form photochemical smog, a significant form of air pollution, especially in the summer. “If you do make NOx, then you probably want to do some additional treatment to try and get rid of the NOx that you’ve generated,” Czerniak said.

Reduction, therefore, is preferable. N2O can be catalytically reduced to H20 + N2. A reducing flame can be used in a combustor; this requires the presence of a reducing agent, such as methane (a commonly used fuel gas) or even a hydrogen-containing process gas such as silane. “You can avoid forming NOx if you use low temperatures, moderate amounts of oxygen, and you add a reducing agent like methane,” Czerniak said.

Edwards presently offers the Atlas series of inward-fired combustion gas abatement solutions. Atlas systems have low fuel consumption compared with previous-generation gas abatement devices and utilize proven Alzeta inward-fired combustor technology to achieve significantly reduced costs of ownership. With one to six inlets with a number of options, including a temperature management system (TMS), they can reach a flow capacity of up to 600 slm and they offer enhanced ease-of-use and more efficient maintenance.

After CO2 and CH4, N2O is the 3rd most impactful man-induced greenhouse gas (GHG). Source: Climate Analysis Indicators Tool, World Resources Institute.

After CO2 and CH4, N2O is the 3rd most impactful man-induced greenhouse gas (GHG). Source: Climate Analysis Indicators Tool, World Resources Institute.

Leti, a CEA Tech institute, today announced it has developed a new on-chip communications system to improve high-performance computing (HPC) that is faster and more energy efficient than current solutions and is compatible with 3D architectures.​

Leti researchers, working in the frame of IRT Nanoelec, boosted computing power and slashed energy consumption by stacking chips on top of each other in a single enclosure, or by placing the chips side by side on a silicon interposer. The chips, which have progressed from demonstrator to fabrication-ready, exchange data via a new communications network that is part of the network on chip (NoC) called 3D-NoC.

3D-NoC technology has been demonstrated with a homogeneous 3D circuit that is comprised of regular tiles assembled using a 4x4x2 NoC. It also features robust and fault-tolerant asynchronous 3D links, and provides 326 MFlit/s @ 0.66 pJ/bit. It was fabricated in a CMOS 65nm technology using 1,980 TSVs in a Face2Back configuration.

This second generation 3D-NoC technology has been integrated in the INTACT circuit developed in the frame of IRT Nanoelec. The 3D circuit, currently in foundry, combines a series of chiplets fabricated at the FDSOI 28nm node and co-integrated on a 65nm CMOS interposer.  The active interposer embeds several lower-cost functions, such as communication through the NoC and system I/Os, power conversion, design for testability and integrated passive components.

Moreover, the chip requires 20 times less energy for data transmission than chips placed on an electronic circuit board. This new IP is compatible with standard remote direct-memory-access-type software used for data transmission and has likely industrial uses in virtual-server migration applications.

“The steady rise in the number of applications that require high-performance computing creates a demand for new hardware-plus-software communications solutions that improve both performance and energy consumption,” said Denis Dutoit, Leti strategic marketing manager. “This new technology brick makes it possible to transfer data between processors via a network-on-chip delivering more powerful, energy-efficient computing.”

Leti will host its annual workshop during Semicon West on “Sensing your Future with Leti” at 5 p.m., July 12, at the W Hotel.  Registration is here.

Leti scientists will be available at booth #2028 in the South Hall during Semicon West to discuss this announcement and other recent research developments and initiatives.

Rudolph Technologies, Inc. (NYSE: RTEC) today unveiled its new patented Clearfind technology, which can detect organic defects that are difficult or impossible to see with conventional white-light imaging techniques. Organic contaminants are often the root cause of field failures, which occur after the material has been exposed to operating conditions for extended periods. Rudolph has been actively collaborating with several key customers to fully understand their inspection challenges and how the new technology addresses them, and plans to incorporate Clearfind technology in its upcoming defect inspection systems for advanced packaging applications.

“As advanced packaging processes become more complex, process windows are shrinking and manufacturers are seeking better methods for control and inspection that balance the need for high throughput against the ‘escape’ of true defects and the ‘false positive’ detection of nuisance defects,” said Mike Goodrich, vice president and general manager of Rudolph’s Process Control Group. “Organic defects, in particular, have become more troublesome as die interconnects shrink and there is less surface area for good adhesion. Clearfind technology will help our customers see these defects earlier in the process, permitting faster action to mitigate the root cause and reducing the amount of product in jeopardy.”

Goodrich continued, “Using laser illumination we are able to clearly identify residue defects that typical white-light optics would miss. In addition to optimizing the wavelength of the illumination to enhance detection, we have specifically designed the mechanics of the system to accommodate the high warpage found in advanced packaging applications.”

Clearfind technology highlights organic residues on bumps and bond pads or at the bottoms of vias so that they are easy to detect. On metals, it eliminates the high-contrast graininess seen under conventional illumination, resulting in an obvious defect signal against a featureless background. This same graininess in conventional imaging can also cause false positives, which are especially costly at this stage of the process where the sunk cost of unnecessarily rejected good product is high. Finally, Clearfind technology readily detects shorts and opens in metal lines when inspected with an underlying organic layer. Rudolph believes these capabilities will significantly increase its customer’s ability to detect process and manufacturing related issues earlier in the process resulting in significant yield, which equates to millions of dollars in savings, especially for processes utilizing known-good die. Rudolph’s customers see this as a critical technology to improve quality for their customers in order to avoid the high costs of replacement and penalties.

For more information about the new Clearfind technology, please visit Rudolph at SEMICON West, booth 6543, in the North Hall.

clearfind-images-final

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the EVG50 automated metrology system. Designed to support the increasingly stringent manufacturing requirements for advanced packaging, MEMS and photonics applications, the EVG50 performs high-resolution non-destructive multi-layer thickness and topography measurement, as well as void detection, in bonded wafer stacks and in photoresists used in optical lithography. The system measures layers down to two microns in thickness, can inspect up to one million points, and achieves throughputs of up to 55 300-mm wafers per hour. This combination of extremely high resolution and high throughput provides cost-efficient full-wafer inspection that enables device manufacturers to improve their wafer bonding and lithography processes, as well as achieve higher yields.

The EVG 50 Automated Metrology System from EV Group performs high-throughput, high-resolution measurements of critical wafer bonding and lithography process parameters.

The EVG 50 Automated Metrology System from EV Group performs high-throughput, high-resolution measurements of critical wafer bonding and lithography process parameters.

Dr. Thomas Glinsner, corporate technology director at EV Group, noted, “The semiconductor industry is witnessing a trend toward total control and monitoring of all production processes. Mid-end-of-line and back-end packaging processes face tighter process constraints at levels previously seen only in front-end-of-line wafer processing. This is creating an urgent need for highly accurate in-line metrology that can provide critical process data quickly and cost-effectively. The EVG50 is an important addition to our suite of metrology solutions that achieves these goals at speeds and resolutions that far surpass those of competitive systems.”

Building on a legacy of widely adopted metrology solutions

The standalone EVG50 system was developed based on the company’s existing in-line metrology module (IMM), which is available as an option in EVG’s line of 300-mm process equipment and has been widely implemented in high-volume manufacturing. The EVG50 complements the company’s versatile EVG40NT measurement system, which is the industry standard for bond overlay inspection, to meet increased customer demand for full-area layer thickness and topography measurement in critical applications. The EVG50’s high throughput and unparalleled accuracy and repeatability, even at ultra-high resolutions, enables cost-effective, 100-percent inspection of production wafers, resulting in improved process control.

The EVG50’s versatility allows it to measure coating thickness for lithography as well as wafer bow and warpage, and make void inspections for a bonded wafer stack on the same system, while its low-contact edge handling enables particle-free, full-area wafer inspection. Another key benefit of the EVG50 is its flexibility. Leveraging a multi-sensor measurement mount, the system can be customized for different thickness ranges and substrates to address a wide variety of customer requirements. Its self-calibration capability also allows for better system reproducibility and productive uptime.

Media, analysts and potential customers interested in learning more about EVG’s suite of metrology solutions, including the EVG50, are invited to visit the company’s booth #1017 in the South Hall of the Moscone Convention Center in San Francisco, Calif., at the SEMICON West show on July 12-14.

Caen, Oct. 22, 2015 – Two years after the launch of the PICS project (funded by the FP7 funding instrument dedicated to research for the benefit of SMEs), three European SMEs, IPDiA, Picosun, and SENTECH Instruments along with CEA-Leti and Fraunhofer IPMS-CNT announce the major technological results achieved during this program.

Started in September 2013, the PICS project was focused on developing innovative dielectric materials deposited by atomic layer deposition (ALD) and related tools (ALD batch tool and etching tool) to bring to mass production a new technology of high- density and high-voltage 3D trench capacitors targeting high-end markets like medical or aeronautics. Capacitors are key components presented in every electronic module. The integrated silicon capacitors technology offered by the SME IPDiA outperforms current technologies (using ceramic or tantalum substrates) in stability in temperature, voltage, aging and reliability and enables to build highly integrated and high-performance electronic modules.

The consortium’s three major technological results are:

  • A novel ALD batch tool was developed by Picosun and Fraunhofer IPMS-CNT. It enables to reduce cost-of-ownership and deliver better uniformity and step coverage for high-K dielectrics into 3D structures. With its demonstrated, optimized, and production-proven ALD processes, Picosun is solidifying its position as a technological leader in the IC, Semiconductor, MEMS markets, from R&D to production systems.
  • A new process for accurately etching high-K dielectrics, which are very specific materials, was demonstrated by SENTECH with the help of Fraunhofer IPMS-CNT. As a result, SENTECH has the potential to gain market share in the field of high-k materials, which have high interest for different applications, e.g. LED, MEMS, magnetic data storage.
  • Two new dielectric stacks were developed and integrated into the IPDiA 3D trench capacitors by IPDiA, CEA-Leti and Fraunhofer IPMS-CNT. The initial specifications were fulfilled and proven by electrical measurements. A new record on capacitance density (>500nF/mm² at 3.3V) and an extended operation voltage (10V with 150nF/mm²) were obtained, which expands IPDiA’s ability to meet current market requirements particularly in the field of medical or aeronautics. Qualification procedure was initiated during the project by launching preliminary reliability studies and it will continue in the coming months.

On top of these R&D results, the other main objective of PICS was the industrialization of this new integrated capacitors technology. Thanks to the partnerships set up, the manufacturability and financial viabilities were ensured by developing adequate industrial tools targeting mass production.

The PICS project is a success for all three SMEs and a good example of the benefits brought by the EU funding instrument “Research for the benefit of SMEs”. The SMEs were able to outsource a part of their research to get from RTD performers innovative know-how and cutting-edge technological processes. The project was built to answer the SMEs’ specific needs and a common goal was set up around the new IPDiA capacitors technology and the specific tools (ALD batch tool and etching) required for its commercial exploitation.