Wafer Processing

WAFER PROCESSING ARTICLES



Varian, Novellus tie for chip tool supplier rankings

05/24/2011 

Varian, Novellus, and Disco prove that customer service really does matter, in VLSI Research's latest annual customer satisfaction survey of large and small chipmaking equipment suppliers.

SEMI: Tool demand inches up in April

05/23/2011 

Demand for semiconductor manufacturing equipment continues to inch up, with demand staying relatively steady as prior sales flush out the supply chain, according to data from SEMI.

ASMC in review: Keynotes and key papers

05/23/2011 

Gary Green, co-chair of the interactive poster session at last week's Advanced Semiconductor Manufacturing Conference (ASMC), reviews key themes discussed, including the need for collaboration across several fields, as well as technical topics from metrics for defect sampling to lithography patterning for 32nm and below.

ASMC 2011: EUV, image sensors, and a capital perspective

05/19/2011 

The last day of this week's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (ASMC) featured talks on EUV readiness and hurdles, CMOS image sensors' increasing complexity, embedded memory failure analysis to improve yields, and a coming shift from chip technology efficiency back to innovation.

Tighter chip densities tease out litho, metrology weaknesses, says Intel

05/19/2011 

Janice Golda, Intel, co-led a session at The ConFab 2011 on continued device scaling. EUV infrastructure will be a major topic, as well as transistor challenges. While lithography difficulties exist at tighter device densities, Golda reminds us that metrology obstacles must also be tackled.

Wafer fab roadmap below 10nm: imec at The ConFab

05/19/2011 

An Steegen, imec, shares how imec is helping enable Moore's Law's continuation to <10nm. Moore's Law through 19nm could be lithography-enabled, Steegen says, but past that point we need to rely on materials, such as high-k, and new device architectures. She also provides an update on imec's EUV progress.

Major IC makers are on 450mm wafers, says ISMI

05/19/2011 

Since the beginning of 2011, the supply chain has been secure and ready to make the wafer size transition from 300mm to 450mm, says Tom Jefferson, 450mm program manager, ISMI, in this video interview at The ConFab 2011.

LEDs are fundamentally semiconductors, running up against fab and packaging issues, says Philips Lumileds

05/19/2011 

LED manufacturing processes lack the level of automation seen in the semi chip fab industry. Wafer size transitions are occuring rapidly, and thicknesses also vary. The forefront of LED fab, much like chip fab, is wafer level packaging, cluster tools for automation, and advanced substrate materials. Iain Black, Philips Lumileds, presents an overview of LED fabrication, device architectures, and markets for the end products.

ASMC 2011: Approaching device scaling, manufacturing challenges with partnerships

05/18/2011 

Another eventful (but still rainy) day at this week's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (May 16-18) offered two highlights sharing a theme: how partnerships can address challenges in device scaling and manufacturing.

Alchimer wet deposition debut targets RDL, other 3D IC processes

05/18/2011 

Alchimer's wet-deposition process, AquiVantage, grows interconnect layers for interposer redistribution layers (RDLs) and significantly enhances via-last backside wafer interconnects. The process eliminates 2 costly photolithography steps.

450mm gaining momentum in the supply chain

05/18/2011 

Thomas Jefferson, ISMI 450mm program manager, presented results to date on the consortium's progress in ushering in the next wafer transition, and how industry participants are doing their part to keep momentum going.

Supply? Tight. Demand? High. Bill McClean forecasts a good year for ICs

05/17/2011 

Bill McClean, IC Insights, explains that demand is good for the IC industry, thanks to smartphones and tablets. Supply, on the other hand, is relatively tight. IC Insights is forecasting 10% growth for the semiconductor market in 2011. The video was recorded at The ConFab 2011 in Las Vegas.

KLAC: Yields are key to low costs, in traditional chips and emerging LEDs

05/17/2011 

High performance and low power consumption are expected of today's chips and LEDs. Today's chip makers still expect to keep their costs down. The key to making this work, says Brian Trafas, KLAC, is yield optimization. Trafas, speaking at The ConFab 2011 in Las Vegas, touches on tool supplier/user collaborations as well.

Wafer bonding: Many options for many devices

05/17/2011 

Wafer bonding. SOURCE: Yole May 2011. Wafer bonding is a complex process, used on 2" to 12" wafers for MEMS, image sensors, advanced packaging, LEDs, and other chips. Yole Développement published a technology study and market research report, "Permanent wafer bonding," to derive trends in the market and technology through 2016.

Connecting investments to industry trends

05/17/2011 

Bob Krakauer, CFO of GlobalFoundries, summarized industry trends in manufacturing and end-applications, a changing foundry landscape, and his company's own long-term investments in semiconductor manufacturing, in his Confab presentation.

More Moore & More than Moore require fabless, foundry, and packaging houses on board

05/17/2011 

Complex supply chain. SOURCE: Yu, The ConFabToday at The ConFab, John Chen (Nvidia), Jeong-ki Min (Samsung Electronics), and Abraham Yee (Nvidia) gathered foundry, OSAT, and chip maker leaders to discuss what happens beyond Moore's Law. The following are key points from "Collaboration to Strengthen the IC Supply Chain."

Silicon Valley upstate: NY's semiconductor manufacturing ambitions

05/16/2011 

Silicon Valley's NY cousin, Mohawk Valley, is attracting investment with university-industry collaborations on leading edge semiconductor manufacturing. Mark Reynolds, Marcy Nanocenter and Mohawk Valley Edge and David Rooney, Center for Economic Growth, speak with Debra Vogler at The ConFab 2011.

2012 and onward for semiconductor fab managers at The ConFab

05/16/2011 

Bill Tobey, ConFab advisory board member and president of ACT InternationalBill Tobey, ConFab advisory board member and president of ACT International, discusses the role of fab managers in today's chip manufacturing environment. After the 2008 financial fallout, and 3 years of recovery, 2012 and onward present challenges and opportunities for research and development, collaboration, etc.

Benchmark "mid-end" tools and materials for 3DIC and wafer-level packaging (WLP)

05/13/2011 

Yole Développement released "Equipment & Materials for 3DIC and Wafer-Level-Packaging," a database and complete report analyzing in detail the equipment and materials tool-box for wafer-level packaging (WLP). This semiconductor packaging technology falls into the "mid-end," where frontend semiconductor wafer fabs and backend packaging facilities both operate.

3D packaging disrupts the IC supply chain -- ConFab session dedicated to the OSAT/foundry/fabless relationship

05/13/2011 

The ConFab gathers semiconductor industry leaders to discuss the biggest trends in the chip manufacturing sector. One of these major trends is 3D packaging, and Session 2 on Monday (May 16) will combine packaging house, fabless, and foundry approaches to the new supply chain, with speakers from Amkor, GLOBALFOUNDRIES, STATS ChipPAC, and Qualcomm.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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