06/28/2012 

This webcast will explore the present status of 2.5 and 3D integration, including TSV formation.

06/26/2012 

Solid State Technology is hosting 3D and 2.5D Integration: A Status Report, sponsored by EVG and ALLVIA, and is free for all attendees. This preview shares a sneak peek at

06/26/2012 

Solid State Technology is hosting a free webcast, 3D and 2.5D Integration: A Status Report. A fourth presenter has just been announced, Brent Przybus, Senior Director, Product Line Marketing, Xilinx Inc.

06/25/2012 

Dow Corning will collaborate with SUSS MicroTec on a temporary bonding process (materials and equipment) for through-silicon vias (TSV) in high-volume advanced semiconductor packaging.

06/25/2012 

Solid State Technology will present 3D and 2.5D Integration: A Status Report on June 27, free for all attendees. William Chen, ASE, will join speakers David McCann, GLOBALFOUNDRIES and E. Jan Vardaman, TechSearch International.

06/20/2012 

In a webcast scheduled for June 27^th at 1:00 Eastern, 11:00 Pacific, David McCann of GLOBALFOUNDRIES will provide a status report on advanced packaging and 3D integration. McCann is responsible for Packaging R&D and back-end strategy and implementation at GLOBALFOUNDRIES.

06/18/2012 

DARPA

06/15/2012 

Attendance was high at this year's Electronic Component Technology Conference (ECTC) in San Diego. Sandra Winkler is senior industry analyst at New Venture Research and IEEE/CPMT Luncheon Program Chair, shares the key trends in ECTC's sessions, like WLP, 2.5D, LED packaging, and more.

06/12/2012 

UltraSource Inc. announced CopperVia, a process that fills vias with pure copper to yield low-cost, high-conductivity, reliable electrical and thermal interconnects in ceramic thin film circuit substrates.

06/12/2012 

ESCATEC added package-on-package (PoP) capability at its Heerbrugg, Switzerland, facility, adding a dipping unit for ball grid array (BGA) packages on its Siplace assembly line.

06/11/2012 

The Full Service Foundry business unit of ams extended its dedicated test solutions for foundry customers, offering known good die (KGD), with customers' complex analog/mixed-signal ICs 100% electrically tested according to their own test specification.

06/11/2012 

Tohoku University of Sendai, Japan and imec signed a collaboration agreement during the Belgian economic mission to Japan, expanding their R&D into areas such as MRAM and 3D semiconductor packaging.

06/08/2012 

Advantest is developing a line of fully automated and integrated test and handling solutions for TSV-based 2.5D and 3D packages. The concept model test cell, DIMENSION, integrates a high parallel test cluster along with singulated die and 3D die stack automated handling capabilities.

06/08/2012 

Singapore

06/07/2012 

Day 3 of the 15th IITC (International Interconnect Technology Conference) opened in San Jose, CA under clear sunny skies and a pleasant breeze. The herd thinned a bit, down to ~150 hearty souls from the original 230 the prior two days.

06/06/2012 

Ron Huemoeller of Amkor presented in the Advanced Packaging session of Solid State Technology

06/06/2012 

With many advanced packaging processes taking place on the semiconductor wafer, the traditional supply chain of front-end fab at the foundry and back-end fab at the packaging and test house is falling apart. The ConFab session,

06/06/2012 

As packaging has played a larger and larger role in chip performance, form factor, and capabilities, The ConFab has increased its focus on back-end processes. Cue

06/05/2012 

The 15^th IITC (International Interconnect Technology Conference) opened Monday, June 4 at the Doubletree Hotel in San Jose, CA. Recurring themes this year were variations on 3D and TSV, novel systems and packaging, and back end memory. Mike Fury reports.

06/04/2012 

The ConFab 2012, Solid State Technology’s invitation-only meeting of the semiconductor industry, opened today in Las Vegas with a keynote address from John Chen, PhD, VP of technology and foundry operations at Nvidia Corporation.