05/19/2011 

PoP provides a cost/performance solution that solves business and logistics issues associated with stacking devices directly. 3D TSV, with its associated uncertainties, cannot yet meet PoP's benefits, says TechSearch International (TSI).

05/19/2011 

A recurring theme at this year's Confab is that 3D integration shows tremendous promise, particularly with many fabless companies, yet many barriers remain -- and the first and biggest is preparing the supply chain.

05/19/2011 

The semiconductor industry is moving to 3D device structures, says Raj Jammy, SEMATECH, at The ConFab 2011, discussing TSV and system-in-package (SiP) opportunities and challenges. He also summarizes logic and memory roadmaps.

05/18/2011 

Another eventful (but still rainy) day at this week's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (May 16-18) offered two highlights sharing a theme: how partnerships can address challenges in device scaling and manufacturing.

05/18/2011 

Alchimer's wet-deposition process, AquiVantage, grows interconnect layers for interposer redistribution layers (RDLs) and significantly enhances via-last backside wafer interconnects. The process eliminates 2 costly photolithography steps.

05/18/2011 

Raj Jammy, VP of materials and emerging technologies at SEMATECH, covered a broad swath of CMOS scaling drivers, system and device trends, and infrastructure requirements.

05/17/2011 

Intermolecular's John Behnke offers his impressions from Day 1 of this year's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (ASMC) in New York. Highlights: a keynote from a suddenly famous GlobalFoundries exec, on-the-fly edge inspection, equipment health monitoring, and a TSV overview.

05/17/2011 

Harvey Frye, vice-chairman of TEL America, summarized the new supplier landscape in his Confab talk, taking both a macro point of view of trends, and how his company as a top supplier is addressing them: collaboration among suppliers, and an increasing focus on consumer needs.

05/17/2011 

Today at The ConFab, John Chen (Nvidia), Jeong-ki Min (Samsung Electronics), and Abraham Yee (Nvidia) gathered foundry, OSAT, and chip maker leaders to discuss what happens beyond Moore's Law. The following are key points from "Collaboration to Strengthen the IC Supply Chain."

05/13/2011 

The ConFab gathers semiconductor industry leaders to discuss the biggest trends in the chip manufacturing sector. One of these major trends is 3D packaging, and Session 2 on Monday (May 16) will combine packaging house, fabless, and foundry approaches to the new supply chain, with speakers from Amkor, GLOBALFOUNDRIES, STATS ChipPAC, and Qualcomm.

05/11/2011 

John Iacoponi, IITC 2011 co-chair, reviews Day 2-3 discussions at IITC/MAM, including interconnect reliability, BEOL memory, 3D integration, process integration, ultralow-k, and future-looking talks on graphene and carbon nanotubes.

05/05/2011 

Semiconductor Research Corporation is leading an effort to address key roadblocks for wide-scale adoption of the emerging 3D ICs and systems. These new initiatives will address critical reliability and design tool issues and leverage partnership between researchers from universities and the semiconductor industry.

05/01/2011  It is expected that from the 15nm node on, the industry will need to adopt new transister architectures; among the contenders: FinFETs and TunnelFETs. Thomas Hoffmann, imec, Leuven, Belguim

04/21/2011 

T.Onishi, Grand Joint Tech and E.J. Vardaman, TechSearch International share the highlights on low-k dielectrics, 3D packaging, copper pillar, and other exciting work presented at the International Conference on Electronics Packaging (ICEP) in Japan.

04/20/2011 

Georgia Tech PRC believes current silicon interposers are limited in performance by high electrical loss of silicon and high cost of wafer-based interposers. Georgia Tech PRC has undertaken silicon R&D with the potential to reduce the cost by 5-10x, in the Silicon and Glass Interposer Industry (SiGI) Consortium.

04/19/2011 

CEA-Leti has installed multiple EVG tools in its 300-mm cleanroom dedicated to R&D and prototyping for 3D integration applications. EVG's equipment will be used in 3D technology demonstrations for Leti's global customer base, as well as low-volume pilot production on 300mm wafers.

04/19/2011 

STATS ChipPAC Ltd. (SGX-ST: STATSChP), semiconductor test and advanced packaging service provider, is expanding its 300mm through silicon via (TSV) offering with the addition of mid-end manufacturing capabilities.

04/07/2011 

Tessera Technologies Inc. (Nasdaq:TSRA - News) began two corporate initiatives to expand its technologies in semiconductor microelectronics beyond packaging, and to potentially separate its Imaging & Optics business.

04/01/2011  Electrografting nanotechnology has been optimized for highly conformal growth of TSV films, enabling a large reduction in cost-of-ownership per wafer compared to the dry process approach. Claudio Truzzi, Alchimer S.A., Massy, France

03/31/2011 

Zvi Or-Bach, MonolithIC 3D, describes the TSV-beating monolithic IC fab process, and argues for scaling "up" rather than down. Or-Bach compares the costs of further semiconductor scaling to advanced packaging.