Issue

Innovation again took center stage at Advanced Packaging's 2003 Advanced Packaging Awards Ceremony, held July 16 in conjunction with SEMI and the back-end portion of SEMICON West.

Global semiconductor sales reached $12.54 billion in June 2003, up slightly from the $12.49 billion in revenue reported in May 2003.

A number of years ago when I became involved in electronics manufacturing, many of the large companies that dominated the marketplace, such as IBM, Motorola and Xerox, operated as "vertically integrated" organizations.

Generally, companies save their exciting new product introductions for the major trade shows to make the biggest industry splash possible.

There was a time when electronics manufacturers focused most of their efforts on developing ways to increase production capacity to meet consumer demand.

There are almost as many definitions of system-in-package (SiP) as there are companies manufacturing them. For the sake of clarity, this article defines SiP as a single package having one or more ICs plus passives with multiple interconnections.

To simplify the thermal management task facing customers, every chip released must meet tough internal performance specifications. But it is difficult to determine the thermal performance of a new design without actually building and testing it, which normally does not occur until relatively late in the design cycle.

Ball shear strength alone does not guarantee a reliable package. By design, ball grid array (BGA) and chip scale package (CSP) device families have to overcome repeat temperature extremes and environmental conditions.

Military hybrids and microwave devices are a distinct subset of microelectronics assembly. Because these devices emphasize power, reliability and robustness in harsh operating environments, assembly techniques require a high level of precision, particularly in the areas of dispensing epoxy and handling die.

The potential of 90 nm application-specific integrated circuit (ASIC) designs is introducing new packaging challenges that threaten the IC designer's ability to take full advantage of this advanced process technology.