Category Archives: 3D Integration

(July 22, 2010) — These market statistics were compiled by Nancy Wu & Mary Olsson, part of the Gary Smith EDA team. The biggest change in 2009 was Mentor passing Cadence to become number two in product sales in EDA. This is an indication of the market shift caused by the move into the ESL Methodology. Synopsys remains a strong number one.

Mentor also grabbed #2 overall in IC design. With the acquisition of Valor, Mentor is also now 3× as large as its next competitor in PCB design.

We believe that the recent changes in Cadence has stopped their market share decline, similar to the changes made at Mentor, bringing in Walden Rhines, during the switch to the RTL design methodology.

Table. Market Share 2009. Note: All numbers show the best estimates of the Gary Smith EDA Analyst. Source: Gary Smith EDA (June 2010)
Rank  2008  2009  Growth, 2008-2009  Market share, 2009
1  Synopsys 1,227.40   1,250.45   1.9% 31.0%
2  Mentor Graphics 755.10 758.50   0.5% 18.8%
3   Cadence Design Systems    905.12      746.08   -17.6%  18.5%
4  Magma Design Automation       159.50      113.80   -28.7% 2.8%
5  Agilent EEsof       110.10      113.40   3.0% 2.8%
Other  1,074.15 1,051.56   -2.1% 26.1%
All companies 4,231.37   4,033.78   -4.5% 100.0%

Gary Smith EDA Market Statistics are a continuation of the Dataquest EDA Market Statistics that were started in 1985. Gary Smith EDA Market Statistics consist of Market Share, Market Forecast and Market Trends. In order to better serve the start-up community, Gary Smith EDA splits Market Trends into five reports. Basic Service consists or a minimum of one Markey Trend report and ten hours of Inquiry. For more information, visit http://www.garysmitheda.com/contact.php

In this video interview from SEMICON West 2010, Walden Rhines, Mentor Graphics, discusses 3D technologies. EDA tools need to be extended to meet the needs of 3D — parasitic extraction and timing, place-and-route, and other steps are different with 3D. The tools are evolving for various 3D techs.

To watch a video interview with Segare Kekare, Synopsis, about rapid root cause analysis and process change validation using design-centric volume diagnostics, go to: Yield metrology looking at systematic failure mechanisms: Synopsis

(July 20, 2010) — In this video interview from SEMICON West 2010, Walden Rhines, Mentor Graphics, discusses 3D technologies. EDA tools need to be extended to meet the needs of 3D — parasitic extraction and timing, place-and-route, and other steps are different with 3D. The tools are evolving for the various 3D technologies. He also touches on lithography evolution.

Also read:
Workshop addresses simulating, measuring 3D IC stress using TSVs

SEMATECH and Fraunhofer IZFP hosted a follow-up meeting in conjunction with SEMICON West to evaluate a design-for-manufacturing (DFM) approach to managing stress in 3D interconnects, and to drive consensus and support for these techniques across the industry.

(July 13, 2010) — CEA-Leti has opened a complete 300mm fab extension dedicated to 3D integration applications. The integration line includes lithography, metallization, deep etching, dielectric deposition, wet etching and packaging tools.

Final equipment installations will continue through to the end of this year with an inauguration event planned in January, 2011. Once assembled, the line will be available for Leti’s customers and partners around the world. It will complement Leti’s 3D-integration toolbox, which already includes through-silicon vias (TSV), alignment, bonding, grinding, thinning, planarization, bumping, micro-inserts and design capabilities and mixed-signal IC applications.
 
“Leti is recognized as a key player in 3D integration R&D and this new line is a vital addition to our continuously expanding 3D capabilities,” said Laurent Malier, CEO of Leti. “It also will enable us to offer heterogeneous integration technologies to customers on 200mm and 300mm wafers.”
 
CEA is a French research and technology public organization, with activities in four main areas: energy, information technologies, healthcare technologies and defence and security. Within CEA, the Laboratory for Electronics & Information Technology (CEA-Leti) works with companies to increase their competitiveness through technological innovation and transfers. CEA-Leti is focused on micro and nanotechnologies and their applications, from wireless devices and systems, to biology and healthcare or photonics. For more information, visit www.leti.fr

by Larry Smith, 3D integration, reliability & product interlock, SEMATECH

July 13, 2010 – Management of mechanical stresses is one of the key enablers for the successful implementation of 3D integrated circuits using through-silicon vias (TSVs). Copper-filled TSVs and wafers thinned to a few tens of microns modify the stress profiles in the silicon, and may exacerbate the stresses introduced by tier-to-tier bonding and chip-package interactions. These stresses have the potential to modify device characteristics, affecting functional and parametric yield and reliability. The stress-related impact of the processing done at the various companies in the manufacturing supply chain needs to be characterized and shared, and designers need a DFM-like solution for managing stress.

To address the need to simulate and measure the stresses being created by 3D IC fabrication processes, SEMATECH and Fraunhofer IZFP hosted a follow-up meeting, “Second workshop on stress management for 3D ICs using through silicon vias" in conjunction with SEMICON West on Tuesday, July 13. More than 40 technology managers from 27 companies and institutions in the US, Asia and Europe gathered to evaluate a design-for-manufacturing (DFM) approach to managing stress in 3D interconnects, and to drive consensus and support for these techniques across the industry.

Keynote speaker Riko Radojcic from Qualcomm presented a stress management for 3D TSV stacking technologies intended to support a DFM-like solution that would take stress modeling out of a T-CAD realm, and enable design entities to quantitatively model stress implications on their designs. The proposed flow is a blend of traditional FEA based tools used at package level, specialized FEA tools used to model the effects of mechanical stress on device performance, and a compact model based “stress hot spot" checker.

In a series of invited talks, other speakers discussed the following:

  • A perspective on multi-simulation flow for stress assessment and a potential approach for addressing the various relevant interactions was shared by Mentor Graphics’ Valeriy Sukharev (“3D TSV Technology: Stress assessment for chip performance")
  • Ehrenfried Zschech from Fraunhofer IZFP presented on the need for multi-scale materials characterization and techniques for nanometer-scale materials characterization (“Multi-scale simulation flow and multi-scale materials characterization for stress management")
  • Strategies to mitigate TSV induced stresses and simulating the effect of mechanical stresses on Si devices and structures was shared by IMEC’s Pol Marchal (“TSV-induced stress modeling")
  • Synopsys’ Xiaopeng Xu presented on 3D TCAD modeling for stress management (“Modeling TSV stress impact on performance and reliability")
  • Robert Geer from the College of Nanoscale Science and Engineering at the U. of Albany showed comparison of micro-Raman measurements and stress modeling of copper TSVs (“Profiling of process-induced stress in Cu TSVs for 3D integration")
  • A summary of the Japanese ASET program research on stress from wafer thinning, microbumps, and TSVs was presented by Mitsu Koyanagi from Tohoku University.

In the afternoon, a working session focused on reviewing the required material properties, measurement techniques, and corresponding simulation use modes to support the proposed DFM flow.

A third workshop will be held at SEMICON Europe in the fall (Oct. 20), hosted by Fraunhofer IZFP in collaboration with SEMATECH, to focus on multi-scale characterization and multi-scale materials and parameters. The workshop will feature invited talks reviewing the methodology and conclusions from the previous workshop — including tables of required material properties, measurement techniques, and corresponding simulation use modes — and assess the industry’s current approaches to this problem. There will also be a working session to establish a proposal for a complete calibration flow for intra-channel stress components of the test chip devices, based on a direct comparison between simulation and experiment.

SEMATECH and Fraunhofer IZFP have launched a wiki site to provide a forum to the community to discuss the issues raised in these workshops.

Larry Smith is a member of the technical staff at SEMATECH, responsible for 3D cost and yield modeling and reliability. He previously worked on copper low-k reliability and process integration. Prior to joining SEMATECH, he worked on high density interconnect for packaging applications, managing the design group for thin-film-on-laminate BGA substrates at Kulicke & Soffa, and managing programs on multi-chip packaging at MicroModule Systems, Dell Computer, and MCC. He received his Ph.D from the University of Illinois-Urbana. E-mail: [email protected].

(July 12, 2010) — This advanced packaging report from Research and Markets covers new and established technologies for embedded package integration. Benefits of embedded package integration include miniaturization, improvement of electrical and thermal performance, cost reduction and simplification of logistic for OEMs.  

Several players such as Freescale with its RCP, Infineon with its eWLB and Ibiden for die embedding into PCB laminated substrates have developed dedicated technologies and process IP in this area for years.

Things are moving really fast at the moment as this year, we see both fan-out wafer level packaging (WLP) and chip embedding into PCB laminate infrastructures emerging at the same time, ramping to high-volume production.  

Fan-Out WLP technology is emerging on both 200mm and 300mm infrastructures

Infineon is having a great success with its proprietary eWLB technology: the first FO-WLP wafers are mass produced on 200mm both at Infineon, STATS ChipPAC and ASE since 2009. Indeed, Fan-Out WLP is extending the general concept of Wafer Scale Packaging to new application categories, especially the ones with higher pin-counts and larger chip size such as wireless communication ICs. First embedded package products based on eWLB have been identified within LGE and Nokia handsets. This year, a few additional players are even more aggressive in putting further capacity for eWLB manufacturing as both STATS ChipPac and NANIUM are at the moment ramping-up their facilities for manufacturing the first generation eWLB on 300mm reconfigured wafers. Other packaging houses such as SPIL, Amkor, UTAC, ACET and others are also on the point to announce the start of their own Fan-out wafer level packaging operations.  

Embedded die package technology to expand fast from niche to high-volume markets

At the same time, embedded die package technology has made a lot of progress on its side. Based on PCB laminate infrastructure, chip embedding technology is actually on the way to catch a relatively important portion of the actual WLCSP packaging business as it does leverage the existing WLP/RDL infrastructure already established worldwide: indeed, most of WLCSP die applications are "embedded ready," so to realize the full benefits of this "WLCSP to Embedded die" conversion, only a few extra manufacturing steps are missing like the realization of thin copper plating process, extreme wafer thinning down to 50µm, thin dies handling and dicing.  

Electrical performance, testing and manufacturing yields are still major issues and showstoppers for chip embedding technology to move forward. Therefore, initial volume markets for embedded packages will be rather small, low pin-counts analog type of applications such as integrated passive devices (IPD), RFID and power MOSFET components that are at the moment under qualification for mass production before the end of this year already. Generally speaking, we believe that the winning situation for embedded die packages can be met for company partnerships able to cross-over the traditional packaging, assembly and test supply chain. A good example would be to put together a leading analog IC player (such as TI, Maxim IC, NXP or ST) with a WLP/RDL partner (such as FCI, Casio Micronics, NEPES, etc.) together with a PCB integrator player (such as Imbera / Daeduck, Ibiden, AT&S, Taiyo Yuden or SEMCO). This type of emerging partnerships are absolutely necessary in order to standardize the embedded package technology and to leverage an entire new packaging infrastructure based on low-cost, panel size PCB manufacturing techniques.  

FOWLP versus Chip Embedding: competing technologies and infrastructures?  

Today, embedded die and Fan-Out WLP technologies are not competing at all. Indeed, these two emerging semiconductor packaging techniques are targeting very different applications initially: the chip embeddeding technology is looking for replacement of low cost, low pin-counts WLCSP/SOT/QFN/LGA family package applications while FOWLP technology is rather targeting the direct replacement of higher I/Os (> 120 pins) BGA package applications. However, in the long term, with standardization and through further technology improvements towards higher yield, better electrical performance, lower profile, better testability and smaller pitch features, Fan-out WLP and Embedded die technology could seriously compete in the fast growing 3D Packaging market space as they will both enable the construction of ever more complex, larger SiP modules with different active and passive functions, all connected on both sides of the active substrate. So Fan-out WLP and chip embeddeding into PCB laminates are just two additional key pieces of the widening tool-box for 3D Packaging.

Conclusions

This section of the report covers application space for each generation of FO-WLP & Embedded die technology; the impact of 3D TSV and silicon interposer technology concepts; and global 3D packaging development roadmaps mixing interposer, FO-WLP, and embedded die package technologies.

The appendix is a Yole Developpement company presentation & services.

For more information, view the report order page at http://www.researchandmarkets.com/product/9e5d3d/embedded_waferlevelpackages_fanout_wlp_  

(July 12, 2010) — Alchimer S.A., a provider of nanometric deposition technology for through-silicon vias (TSV), semiconductor interconnects, and other electronic applications, announced that Panasonic Corporation (NYSE: PC) has become an equity investor in the company.

“Throughout the electronics supply chain, manufacturers are increasingly in need of high-quality nanometric metal films that can be mass-produced at low cost,” said Patrick Suel, venture partner with Panasonic Venture Group. “We see this at the wafer level, on substrates, and in 3D packaging, which is emerging as an important technology to lower costs for future ICs and systems. We believe that Alchimer’s nanometric films have tremendous potential to change the traditional cost-performance ratio at many points along the value chain.”

Alchimer’s breakthrough technology, electrografting (eG), is an electrochemical process that enables the growth of extremely high quality polymer and metal thin films on both conducting and semiconducting surfaces. The company’s deposition technology reduces overall cost of ownership for high-aspect-ratio TSV metallization by up to two-thirds compared to conventional dry processes, and shortens time to market. 

In addition to electrografting, Alchimer has developed chemical grafting (cG), an electroless process sequence that enables the growth of highly adherent, low-resistivity copper-diffusion barrier films on isolating surfaces through the formation of strong chemical bonds between the films. 

Funding has been facilitated by the Panasonic Venture Group, a Silicon Valley-based unit of global consumer electronics leader Panasonic R&D Company of America, which invests in companies that may present a technology-based advantage to Panasonic. Through its investments, Panasonic Venture Group champions technology partnerships between private companies and R&D units of Panasonic. The dollar amount of the investment and Panasonic Venture Group’s equity holding were not disclosed.

 “The Panasonic Venture Group is known for its investments in companies that present potential strategic competitive advantages to Panasonic, and we are very pleased to have them as an investor as we commercialize our technologies,” said Steve Lerner, CEO of Alchimer. “We believe that electrografting offers substantial promise as an enabling technology for TSVs and 3D interconnects, which we expect to move quickly into high-volume production in the next few years.”

Alchimer develops and markets innovative chemical formulations, processes and IP for the deposition of nanometric films used in semiconductor interconnects and 3D TSVs (through-silicon vias), as well as other applications in the electronics value chain. Visit the company at SEMICON West in San Francisco this week, Moscone Center, South Hall, Booth 1811.

Get all the latest news from SEMICON West at http://www.electroiq.com/index/Semiconductors/semiconwest2010.html

(July 8, 2010) — Lasertec Corporation of Japan has joined SEMATECH’s 3D Interconnect program at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. Lasertec will partner with SEMATECH to develop robust, cost-effective process metrology technology solutions for readying high-volume via-mid through silicon via (TSV) manufacturing. 

The collaboration between Lasertec and researchers from SEMATECH’s 3D Interconnect program will include investigations and comparisons of 3D TSV depth metrology schemes. This work is necessary not only for TSV RIE process control, but also for providing critical feed forward data for wafer thinning and TSV expose processes. To facilitate this work, Lasertec will place a 300 mm TSV infrared (IR) etch metrology tool in SEMATECH’s 3D R&D center, providing advanced measurement capabilities that will enable accurate, repeatable TSV depth measurements over a range of TSV dimensions.

“We are pleased to welcome Lasertec to the 3D program,” said Sitaram Arkalgud, director of SEMATECH’s 3D Interconnect program. “Our common goal is to address the technical challenges of via-mid TSV technology. The metrology expertise of Lasertec combined with the capability of the TSV 300-IR will fill an important gap in our integration scheme. Together, we will provide our members with a world class TSV depth metrology solution capable of addressing today’s needs as well as tomorrow’s aggressive dimensions.”

Sitaram Arkalgud, Sematech, summarized the company’s 3D metrology to measure TSV depths and profiles. This technology is important to determine how far to thin wafers. He also updates SST/AP on TSV standardization.

Get all the latest videos, podcasts and news from SEMICON West 2010 at http://www.electroiq.com/index/Semiconductors/semiconwest2010.html

“Lasertec is looking forward to contributing our expertise in the fields of metrology and inspection to further explore innovative metrology capabilities that will make 3DTSVs commercially viable,” said Hal Kusunose, CTO of Lasertec. “Our cutting-edge TSV 300-IR tool will allow SEMATECH researchers and SEMATECH’s member companies to address important metrology challenges of TSV technology.”

“The leading-edge R&D that is critical for commercializing innovative TSV technologies will be further enhanced by the addition of Lasertec to CNSE’s Albany NanoTech Complex,” said Richard Brilla, CNSE VP for strategy, alliances and consortia. “This new collaboration builds on the SEMATECH-CNSE partnership to support the advanced technology needs of our global corporate partners and the nanoelectronics industry.”

TSV technology is a method of combining integrated circuits (ICs) in a vertical stack to enable high functionality and performance with low power consumption in a small footprint. While employing many standard chip manufacturing and packaging processes, TSVs present several new technical and logistical challenges, now being addressed by SEMATECH.

SEMATECH’s 3D program was established at CNSE’s Albany NanoTech Complex to deliver robust 300 mm equipment and process technology solutions for high-volume TSV manufacturing. To accelerate progress, the program’s engineers have been actively engaging with leading-edge equipment and materials suppliers. Eventually, 3D interconnects will provide cost-effective ways to integrate diverse CMOS technologies and chips with emerging technologies such as micro and nano electromechanical systems (MEMS, NEMS) and bio-chips.

Lasertec supplies innovative semiconductor, LCD and PV related inspection and measurement equipment: TSV etching depth inspection system, wafer inspection/review system, EUVL mask blank inspection system, photomask inspection system, photomask haze removal system, color filter repair system, PV cell conversion efficiency distribution measurement system and various types of confocal laser microscopes. For more information, go to www.lasertec.co.jp.

The UAlbany CNSE college is dedicated to education, research, development, and deployment in the emerging disciplines of nanoscience, nanoengineering, nanobioscience, and nanoeconomics. The UAlbany NanoCollege houses the only fully-integrated, 300mm wafer, computer chip pilot prototyping and demonstration line within 80,000 square feet of Class 1 capable cleanrooms. For more information, visit www.cnse.albany.edu.

July 22, 2010 – Elpida Memory and Taiwanese chip firms Powertech Technology Inc. (PTI) and United Microelectronics Corp. (UMC) are banding together to push 3D IC integration for advanced semiconductor processes.

The combination will result in what the partners call "a total 3D IC logic+MDRAM integration solution" — incorporating interface design, through-silicon via (TSV) formation, wafer thinning, testing, and chip stacking assembly — for devices that package memory and logic chips for both processing and storing data, with target applications in consumer electronics and mobile gadgets. No schedule for availability was announced, though the Nikkei daily and Digitimes suggest sampling on UMC’s 28nm process technology by mid-2011 (sampling) and volume ramp by mid-2012.

Their work will combine Elpida’s DRAM, which last fall used TSVs for 8GB DRAM (eight stacked DRAMs); UMC’s logic foundry experience, particularly with systems-on-chip (SoC); and PTI’s assembly know-how (it works with down to 50μm thin wafers, and is developing 16+ die-attach packages, as well as systems-in-package for logic customers.

The stacked architecture enables many I/O connections between logic and DRAM to "massively increase the data transfer rate and reduce power consumption, making possible completely new kinds of high-performance devices," says Takao Adachi, Elpida director and CTO, in a statement. "Our plan now is to speed up development in a way that supports ultimate system solutions that will be made possible by freely joining together all kinds of devices through TSV integration."

Pursuing the DRAM+logic TSV integration also means "less expensive product technology and a manufacturing process that can handle large-volume production on neutral ground," Adachi added.

June 17, 2010 – Toshiba Corp. is revealing at this week’s VLSI Symposium in Hawaii a new silicon nanowire transistor for system LSI for 16nm node and beyond.

The device achieves a 1mA/μm on-current, a record for a Si nanowire transistor, thanks to reduced parasitic resistance and 75% better on-current levels, the company says.

As planar transistor architectures scale down in size, current leakage between the source and drain at off-stage ("off-leakage") is a critical problem; to answer this, transistors with 3D architectures are being investigated. Among these options are Si nanowires, which can suppress off-leakage and achieve further short-channel operation because their thin wire-shaped silicon channel is controlled by the surrounding gate — but parasitic resistance (especially under the gate sidewall) is still a problem.

Click to Enlarge
Figure 1: Structure of a silicon nanowire transistor. (Source: Toshiba)

To address this, Toshiba optimized gate fabrication and reduced the gate sidewall thickness from 30nm to 10nm. Epitaxial Si growth on the source/drain with such a thin gate sidewall improved on-current by 40% and realized low parasitic resistance. A further 25% increase in current performance was achieved by changing the direction of the Si nanowire channel from the <110> to <100> plane direction. The result: on-current level of 1mA/μm and off-current of 100nA/μm — a 75% increase in on-current, with no change in off-current condition.

Click to Enlarge
Figure 2: Comparison with the previous work. (Source: Toshiba)

Toshiba says it will continue to push development of this transistor, toward "establishing fundamental technologies for high-performance, low-power system LSIs." The work was partly supported by the New Energy and Industrial Technology Development Organization (NEDO).