Category Archives: 3D Integration

BY PER VIKLUND, Mentor Graphics Corp.

Packaging technology has evolved over the years, transitioning into more of a revolution with the introduction of new packaging styles practically every month. Designers face designing extremely high-performance packages with mixed technology content such as high speed digital, analog, and RF. At the same time, density requirements force the use of 3D packaging technologies. As prototypes are a relic of the past when it comes to packaging design, early planning/evaluation, parasitic extraction simulation, and verification becomes more and more critical.

Clearly, the system packaging dilemma is a wide and complex topic. Therefore, investigating the complexity buried in the mere co-existence of multiple technologies in a chip package system requires a broad overview.

Multi-die Package Design Flow

Traditionally, chip designers design the chip core functionality and then hand it over to the I/O ring design teams (Figure 1). Ideally, these teams collaborate with package engineers on where to place specific signals and where to position power and ground. Gernerally, this is driven directly from the IC design teams.


Figure 1. Typical design flow for a multiple-die package design.
Click here to enlarge image

Skilled engineers and a great deal of experience means that teams can still push their designs through, but it is becoming harder to succeed within reasonable time, which leads to unpredictable lead times and quality.

Co-design

The latest trend, cross-discipline collaboration – known by some as “co-design” – carries different meaning for different people. Early co-design tools looked at how to let IC designers see the impact their actions had on the package to provide package-aware chip design. As system-in-package (SiP) becomes more popular, the same solutions are expanded to support multiple die, and assist design teams with various levels of optimization and a means to write the optimized results back to the chip-design environment.

SiPs have grown in complexity to a level where a different kind of co-design is needed. Figure 1 shows how the flow is broken at several places so that package-aware chip design is no longer enough. ASCII or spreadsheet files may be convenient, but in addition to being proprietary, it’s not a data format designed for the task it’s set to solve. Secondly, feedback of package information to chip design is poor, if at all available. Every I/O and power/ground decision at chip level impacts package design, and also PCB design. A way to analyze effects, optimize the situation, and feedback updates to chip design is needed that must be robust and secure.

Top Level Connectivity

Once there is a system-wide schematic (a classical symbol schematic, table driven, or a mix), the design can be considered at system level. Rather than deal with a single die, multiple die, the package, and even the PCB can all be in flux. Managing top-level package connectivity is necessary to allow system-wide optimization and management of design constraints.

Pin-out

The chip or package engineer typically designs package pin-out. The result affects chip, package, and board design; and ultimately system performance. The trend is going from optimizing I/Os only at chip level, to second-generation solutions that optimize chip-to-package design. System-level optimization would involve optimizing package pin-out against board and package content at the same time.

Package-on-package (PoP) devices with two sets of pin-outs – one on the bottom surface and one on the top surface – are also becoming more prevalent. Often, the top-level pin-out is fixed, dictated by JEDEC standards, while at other times it is flexible. Regardless, the top surface pin-out will impact the optimal bottom surface pin-out and, therefore, the chip I/O configuration and the bottom surface pin-out.

Interaction

SiPs typically contain multiple circuit blocks of different technology such as RF or microwave, analog, and high speed digital. As package designs are dense, interaction between these systems is unavoidable. These cross-disciplinary aspects have to be handled early, when changes to the design are almost free.

However, at this point, so little is known about the design that all data entered for evaluation are pure assumptions. By estimating the total number of chip connections, early package feasibility studies can commence, using dummy die and connectivity to establish required package size and type. Having a rough idea of power consumption also allows for early power integrity planning at the package level.

As soon as there is a transition from “virtual prototyping” into “actual” design work, the cost increases rapidly as the design cycle progresses. Therefore, it may be beneficial to spend extra time in the early planning.

Incrementally Add Circuit Intelligence

When a signal list is available, it is possible to generate a preliminary pin-out driven from both chip and board. Import signal lists for each die, and then establish a top-level connectivity, analogous to a system schematic, but for the package alone. Table-driven interconnect editor-type tools are ideal for this purpose as they give an overview of the connectivity, and offer effective editing and signal manipulations for large signal counts.

At this time, chip design should have progressed enough to benefit being added to the package flow. Using standard data formats (Open Access, Lef/Def, HDL) incrementally adds real design knowledge to the process.

Evaluate Drivers and Topology

With signals in place, making initial signal I/O ring placement for each die can begin, as well as a preliminary power and ground port placement. Using SI and PI exploration tools, in combination with the SI models from the I/O library, makes it possible to run virtual SI/PI analysis where signal lengths and driver loads are estimated to see if the chosen I/O cell types will be capable of driving the given topology. The I/O ring with power/ground ports can now be fed back to IC design environments for each die for evaluation by the IC designer.

Stacked Die

Part of this iterative process is to evaluate different chip stacking configurations. It is often obvious which parts make sense to stack. What is less obvious is in what order and what rotation.


Figure 2. Correct-by-design 3D bond-out of two stacked die.
Click here to enlarge image

It is necessary to run preliminary bond-outs (for wire-bonded die) already in the co-design process as wire bond patterns strongly affect several aspects of package design (Figures 2,3).


Figure 3. Three-dimensional view of the same bond out shown in Figure 2.
Click here to enlarge image

Busses and differential signals require extra care, and sometimes evaluation of thermal aspects of a stacking configuration is required before the best option is settled upon. It may now be necessary to run yet another iteration of I/O optimization.

Virtual Becomes Actual

At this stage it makes sense to start the more detailed package design. What initially was just virtual data has gradually been replaced by real data.

Analysis between systems such as model the coupling of a high-speed clock line into an RF circuit or vice versa begins. Circuits are grouped together and pushed over an RF analysis tool, which generates an n-port S-parameter model to describe the interaction scenario. This information allows relocatation of circuits, changes in ground planes, RF routing etc.


Figure 4. Looping transpires between blocks in the flow until both sides are satisfied with the result.
Click here to enlarge image

This process is different from the traditional flow. Beginning before data is actual, and as seen in Figure 4, looping between any blocks in the flow is allowed until both sides are satisfied with the result.

Conclusion

Using standard formats, such as Open Access and Lef/Def, this flow would work with almost any IC design tool on the market. By facilitating virtual prototyping and SI and PI analysis at the planning and co-design stage, it is possible to catch expensive issues before they happen and design correctly rather than being in a fix mode.

PER VIKLUND, director, IC packaging and RF system design division, may be contacted at Mentor Graphics (Scandinavia) AB Hassle Bösarp 12 Kista SE-27493 Sweden; +46/411 456 11; [email protected].

December 5, 2007 – EV Group (EVG) and Brewer Science say they have demonstrated temporary wafer bonding capabilities for a wide range of backside processes, including through-silicon vias (TSVs) and backside metallization, using an approach optimized for high-temperature advanced packaging applications.

Earlier this summer, the two companies announced that after more than a year of development work, they had successfully combined Brewer’s WaferBOND HT series of materials and EV Group’s 850TBDB bonding and debonding equipment platforms to perform temporary bonding of original-thickness device wafers (sub-100-micron) onto rigid carrier wafers (up to 300mm).

The combined technology platform addresses an industry need as it increases use of 3D stacking and wafer-level packaging approaches, including TSV, the companies said in a statement.

“Three-dimensional device stacking is essential to producing multifunctional devices with improved performance and compact footprints. High-temperature processing compatibility and fast debonding processing times of less than five minutes are important attributes to furthering the viable production capability of this innovative technology,” noted Jim Lamb, director of corporate business development with Brewer Science.

This arrangement expands Agilent’s product offerings. Multiprobe is already using the Agilent B1500A semiconductor device analyzer in its current products.

(December 6, 2007) SCOTTS VALLEY, CA — Vertical Circuits Inc. (VCI), has announced a long-term license agreement with Shinko Electric Industries, enabling Shinko to utilize VCI’s patented vertical interconnect pillar (VIP) technology to develop and produce next-generation chip scale 3D packaging solutions.

November 20, 2007 – STATS ChipPAC says it will expand its flip-chip offerings to its Shanghai, China operation, encompassing wafer bump, sort, assembly and final test.

The first phase of the plan will add and qualify assembly and test equipment specifically tailored to high-volume manufacturing of flip-chip packages, with volume production expected to start in 1H08. A second phase will add electroplated wafer bumping capabilities, for 200mm wafers in 1H07 and 300mm wafers in 2H08.

“As demand for flip-chip technology continues to grow in applications such as high performance ASICs and graphics as well as DSPs and integrated 3D packages for mobile platforms, it will be essential to have a low-cost, high-volume manufacturing location for flip-chip solutions,” particularly in China where customers “are looking for cost effective flip chip technology,” explained Wan Choong Hoe, EVP and COO of STATS ChipPAC, in a statement.

The new capabilities in China will complement existing bumping capabilities in Taiwan and Singapore, following three years of “aggressive” expansion in flip-chip technology and capacity, and the company views the technology as key to its plans to make its Shanghai operation “into a megasite for full turnkey backend solutions encompassing wafer bump, sort, assembly and final test,” Wan said.

Roozeboom joins a distinguished team of industry researchers devoted to creating a cost-effective 3D integration method. The technical team consists of both semiconductor materials companies and equipment companies, including technology groups Fraunhofer IZM in Berlin, KAIST (Korea Advanced Institute of Science and Technology), SAIT (Samsung Advanced Institute of Technology), CEA-LETI in France, and TAMU (Texas A&M University).

(November 15, 2007) Saint-JEOIRE, France — S.E.T., the former SUSS MicroTec Device Bonder Division, has announced that the partnership between S.E.T. and CEA Leti has resulted in a radically new-generation, high-accuracy (0.5 µm), high-force (4000 N) device bonder for wafer diameters up to 300 mm. The FC300 bonder includes a built-in chamber for collective reflow in a gas or vacuum environment and also features nanoimprinting capabilities.

Complementing its existing portfolio of small 8×8 mm and 5×5 mm packages, the Actel device in the new package is said to offer designers four times the density, three times the I/O and a 36% reduction in size compared to competitive programmable logic devices. Smaller than a kernel of corn, the new IGLOO FPGAs are an ideal solution for power-sensitive, space-constrained handheld devices such as smart phones, portable media players, secure mobile communications devices, remote sensors, security cameras and portable medical devices.

(November 14, 2007) PHOENIX, AZ — FlipChip International has introduced its new Embeddable Die Customization (EDC) technology targeted at readying integrated circuits and other devices for integration into emerging 3D packaging solutions. EDC enables the embedding of semiconductor devices within printed circuit boards or other interconnection schemes, thereby enabling lower profile, more reliable packaging schemes for applications including next generation cell phones.

November 6, 2007 – AMD, Carl Zeiss SMT, and Qimonda AG are forming a 12M euro (US ~$17.4M) “innovation center” in Dresden, Germany (“Silicon Saxony”), under a larger “Nanoanalysis” project to develop new analytical and characterization methods for next-gen chip development.

The initiative is part of the German Federal Ministry of Education and Research’s (BMBF) IKT2020 program, involves setting up and expanding microelectronics competency centers. This particular center will utilize ultrahigh-resolution particle beam systems to image, analyze, and process specimens in support of characterization of 3D semiconductor structures and development of new materials for chip fabrication.

The site is open to “all interested firms and institutes in the Dresden area,” including all partners of “Silicon Saxony” — e.g. the Dresden Technical U. or the Fraunhofer Center Nanoelectronic Technologies CNT.

“Only through the consistent enhancement of the analytical and measuring methods will it be possible to master the future challenges posed by the development and production of state-of-the-art storage technologies,” noted Frank Prein, managing director of Qimonda’s Dresden operation and SVP of technology, in a statement.

Wolf-Dieter Lukas, head of the BMBF department “Key Technologies – Research for Innovations,” added that “only by setting targeted priorities in research funding will we succeed in maintaining Dresden’s leading role in high-tech chip production and in further expanding it through such innovative approaches as here in the field of nanoanalysis.”

“Through our joint work in the Carl Zeiss Innovation Center Dresden, we have access to leading-edge electron and ion microscopes and believe we can therefore further accelerate the introduction of new technologies,” stated Udo Nothelfer, VP of AMD’s Fab 36. “The experience gained in industrial utilization may be incorporated at an early stage in the development of future analytical systems.”

by Bob Haavind, Editorial Director, Solid State Technology

With the trend toward 3D integrated circuits gaining momentum, SEMATECH organized a workshop in Albany, NY earlier this month (Oct. 11-12) as it plans to move its work on 3D from Austin to its New York branch. Why does every chipmaker have 3D approaches using through-silicon vias (TSVs) on its roadmap as the industry heads toward 32nm and beyond? There are four main drivers, explained Phil Garrou, Microelectronic Consultants of North Carolina, in an opening overview of the field:

– Failure of low-k dielectric integration, due to persistent problems with mechanical failure, delamination, etc.;
– Latency and processing speed for multi-core processing, which could be aided by shorter traces (TSVs) in the z-axis within bonded chip stacks;
– Hetero-integration, or stacking a variety of chips requiring different processes; and
– Form factor — such as stacking up to eight memory chips in a package taking the same space as a single chip.

As 3D has progressed, it has become clear that electrical performance can be superior to that of system-on-a-chip (SoC) approaches, with the added advantage of being to optimize processes for each chip in a stack.

Garrou also cited a recent report by IBM, Toshiba, and Samsung that found no difference in electrical performance between 32nm and 22nm chips. If there is no performance advantage, he noted, why go to the huge expense of changing lithography and processes for 22nm when a similar form factor could be achieved by stacking chips using 32nm features?

While extensive development of 3D methods will be needed to achieve true hetero-integration, which may be a number of years off, the techniques are already being employed with memory chips. In fact, according to Garrou, a face-to-face bonded processor and memory stack was designed into Sony’s PlayStation 3, enabling the use of 90nm chips rather than having to go to 65nm. Seven Japanese companies are now working on 3D image processing chips (for cameras), he added, with one full side for imaging and TSVs to the backside to connect to processing circuits.

“The easy stuff will be first,” Garrou suggested, especially flash memory and other memory stacks, followed by image processing stacks.

The TSVs generally are etched deep into a wafer or chip, similar to trench capacitors for memory chips, and then the backside is thinned away up to the bottom of the vias. Copper “nails” can be deposited to make contact between wafers or chips that are bonded into stacks. Die are repartitioned to achieve closer trace distances from block to block than could be done on an SoC.

Because of these shorter signal paths, some cite the potential for 35%-40% reductions in interconnect lengths in the 3D approach vs. a conventional horizontal surface layout. But a number of speakers at the workshop pointed out that chip architects already had optimized most layouts to eliminate long traces, so that 5%-10% reductions seem more likely. A potential advantage discussed during the Q&A session would be to cut down on interconnect layers on a chip — for example, putting a processor and DRAM on separate chips and connecting them with TSVs might reduce interconnect layers from eight to five, and thus reduce processing costs.

Myriad problems remain, however, before 3D can be effective beyond simple memory stacks. Thermal design will be one of the toughest, and so that was the focus of the SEMATECH workshop. Hot spots within a multichip stack will make heat removal challenging, and thinning either wafers or chips will make the problem even worse, speakers pointed out. Numerous approaches to dealing with thermal problems were discussed, although work enabling physical modeling of heat flow through a stack is just being initiated, so it is not yet clear how well most of them would work.

While thermal metallized interposers between chips might help remove heat, they also would lengthen signal paths, so some speakers felt they were an unlikely solution. A technique mentioned by a number of presenters was to simply add extra vias in hot spot areas, to conduct away heat. Jason Cong, et. al., UCLA, discussed work going on to extend EDA to deal with thermal analysis and to determine the number of extra vias needed to reach a target temperature. If the analysis is not optimized, it might lead to using 2.5x more vias than needed to reach the target, he said.

But Muhannad Bakir, research engineer at Georgia Tech, suggested that very large numbers of vias would be needed for heat removal in gigascale systems, and an air-cooled heat sink at one end of the stack would have to be much larger than the die to be effective. As an alternative, Georgia Tech is investigating microfluid channels with multi-layers of cooling within a chip stack. Since the researchers are also exploring optical signals, they have developed what they call “trimodal planar interconnects” using hollow polymer pins and fiber optics.

A single-phase, microfluidic cooling system with about 2W pump power at some 2.1 atm pressure could remove 800 W/cm2 from a chip stack, according to Bakir. He said that the researchers had learned that work on microfluid cooling was going on elsewhere, as well as at Georgia Tech.

Another approach might be thermoelectric cooling, discussed by Seri Lee of Nextreme, using copper pillar bumps. P and n elements about 10-20μm thick might form a heat pump to remove heat, although extra vias to conduct the heat would still be needed according to Lee.

Some have suggested that 3D designs should be based on 3D placement and routing and sophisticated standard cell placement algorithms. This is wrong, according to Ruchir Puri, IBM T.J. Watson Research Center. 3D needs to be exploited at the architectural level, including physical planning. Wire length is not the most important criteria, he said, timing and critical paths are what needs to drive co-design of chip performance and power, including thermal design and a physical view. 3D architecture and performance must be linked to thermal analysis.

“We need thermally aware design tools,” Puri said.

To achieve yield, it would be desirable to assemble thinned chip stacks of known good die. But since bonding and connecting operations may create new faults, testing would have to be duplicated after assembly, doubling test costs, some speakers pointed out. Instead, less complete testing might be done, so that “pretty good die” are assembled to keep costs down. Once a 3D stack is assembled, access to circuits within the stack will be limited, so built-in self-test structures and sophisticated testing strategies will be needed.

As the industry moves down to 32nm and beyond, physics constraints will force so many changes in materials, processes, and device structures, that even if solutions can be found, they may be very expensive and time-consuming to develop and put into production in fabs. This appears particularly true for lithography. As a result, suggested Robert Patti, founder and CTO of Tezzaron Semiconductor, Naperville, IL, we may see much more subtle shifts down the node scale well beyond the half-node shifts of past cycles.

While the industry struggles to continue on the Moore’s Law track, doubling the number of devices per chip area every two years, 3D approaches, first using bonded chip or wafer stacks with TSVs, and then building multi-layers of circuitry right onto the chip, may provide an interim solution if the shrink slows down. — B.H.

For an editor of a semiconductor manufacturing publication, there are several sides to every trade show. On one hand are the technical sessions, where we get a glimpse of the latest and greatest technologies being developed, and garner ideas for technical features to fill upcoming issues. On the other hand, are the industry players