Category Archives: Materials and Equipment

July 23, 2007 – The latest monthly data from SEMI indicates soft demand at the midpoint of 2007, days after the group joined the growing chorus of industry watchers in expressing pessimism that the equipment industry will see anything above a few percentage points of growth this year.

After revising May figures slightly down (billings a fraction of a percent, and ~1.6% for bookings), SEMI reports preliminary June billings from North American-based manufacturers of semiconductor equipment were $1.75 billion, up about 5% from May and nearly 13% from June 2006, perhaps indicating a typical end-of-quarter sales push. That level in terms of dollars surpasses August 06, and represents four straight months of positive sequential growth, following six straight months of declines.

Preliminary bookings, though their highest dollar amount in nearly a year ($1.65 billion), were essentially flat (0.6%) vs. May, and down -7.3% from a year ago, the worst Y-Y decline since December 2005.

Also taking a dip was the June book-to-bill ratio (B:B), which fell further below the even-parity mark to 0.94, meaning that $94 worth of orders were received for every $100 of product billed for the month. That’s the lowest since October 2006 (also 0.94); the previous low before that was also in December 2005.

Despite the clear slowing trend so far this year, SEMI still sees “strong sales in 2007” for North American-based semiconductor manufacturing equipment, topping $40 billion, thanks to investments in 45nm and 300mm tools. That avoids the topic of growth, though — which in its midyear forecast last week, SEMI shaved down to just 1.1% growth, instead of the 3.7% it previously projected. The group also now sees 2008 with barely mid-single-digit growth as well, vs. 13.3% it thought at the beginning of this year.

by Debra Vogler, senior technical editor

SEMATECH is continuing to discuss many of the themes from papers it presented at the VLSI Symposium (see our previous reports on the VLSI Symposium by SST editorial board member John Borland: Part 1 and Part 2). According to Raj Jammy, director of front end processes at SEMATECH, the consortia has settled on a gate first/high-k metal-inserted poly stack (MIPS) electrode approach instead of FUSI or replacement gates. “We’ve been doing high-k/metal gate [research] for quite a while and we chose a path that was more manufacturable and that fits in more easily with existing technologies in terms of scalability, contamination prevention, and integration,” said Jammy, in a pre-show interview with WaferNEWS.

Noting that FUSI hasn’t played a role in recent announcements from IC manufacturers, Jammy told WaferNEWS that it has a long way to go until it is manufacturable. “Replacement gate is an option; a couple of companies have pursued it,” he said, though he noted that scalability of this approach is also a big issue.

SEMATECH continues to remain mum about exactly which materials systems are preferred for pFET metals — details are reserved for consortia members, but Jammy did say that three or four solutions have been discussed. For nFET metals, two candidate systems within the lanthanide series have been identified, but which of these is the best is, again, only available to member companies.

Along with materials selection, annealing is another “hot” topic at SEMICON West. Jammy noted that at 45nm, some companies will use millisecond annealing (flash or laser), though some may only need spike annealing at this node. By 32nm, however, he projects that almost everyone will have to use millisecond annealing, with the possibility that some applications may need a combination of the two anneals. — D.V.

July 19, 2007 — Surrey NanoSystems has won a major order for its carbon nanotube growth tool from ITA, the advanced technologies research institute in Trapani, Sicily.

ITA selected the NanoGrowth tool for its ability to repeatably grow defined carbon nanotube configurations, and to grow materials at low temperatures. The institute will use the equipment to research carbon nanotube-based nanocomposites and mechanical sensors for medical and
aerospace applications.

ITA included in its tool configuration a large range of materials processing modules to support diverse research programs. In addition to the NanoGrowth tool’s core CVD (chemical vapor deposition) and PECVD (plasma-enhanced CVD) nanomaterial growth capabilities, Surrey will fit modules for catalyst delivery, ion etching, and thin-film deposition. This will allow ITA researchers to grow precision single- and multi-walled nanotube structures and silicon nanowires, as well as being able to dope, etch, and deposit silicon.

In addition to the provision of equipment, the two organizations have signed a three-year development partnership to share intellectual property.

July 18, 2007 – Jerry Coder, president emeritus of Dupont Electronic Technologies’ semiconductor materials business, has been appointed as the new chairman of SEMI’s board of directors, succeeding Hermes-Epitek CEM Archie Hwang. Coder has been active in SEMI, holding leadership roles on the group’s finance, executive, EHS executive, and emerging technologies committees.

SEMI members also elected four new board members: Susumu Kohyama (Covalent Materials Corp.), Kiyoshi Togawa, (Hitachi Chemical Co. Ltd.), Way Tu (Allegro Manufacturing Pte. Ltd.), and Kazuo Ushida (Nikon Corp. and Nikon’s Precision Equipment Co.). Existing board members reelected included Andre Auberton-Herve (Soitec), Douglas Neugold (ATMI), Mary Puma (Axcelis Technologies), Stephen Schwartz (Asyst Technologies), and Mike Splinter (Applied Materials Inc.).

July 18, 2007 – Keithley Instruments Inc. and European R&D institute CEA-Leti have agreed to jointly research methods for characterizing advanced semiconductor materials and devices that support DC, high frequency, and RF-level signals on both micro- and nano-level structures. Under the deal, Keithley’s RF-enabled semiconductor test equipment will be installed at CEA-Leti’s facilities.

“As semiconductor technology pushes the upper limits to achieving RF-level signals and device miniaturization to nano levels, measurement technology must not only keep pace but even lead researchers’ ability to build and test these devices,” said Mark Hoersten, Keithley VP of business management, in a statement. “Our partnership with CEA Leti is a unique opportunity to create new measurement technology at the point where many of our customers’ technologies converge: semiconductor, RF/wireless, and nanotechnology.”

“The ability to make high quality electrical measurements is crucial to advance the ‘More Moore’ and ‘More Than Moore’ initiatives forward,” stated Olivier Demolliens, head of the nanotech division at CEA Leti. “Our electrical experts need the finest data to understand, model, and improve our devices. The partnership with Keithley makes it possible to help develop and boost the measurement technology to coincide with the needs of research and industry experts.”

By Fran&#231oise von Trapp, managing editor, Advanced Packaging

Participants in Tuesday’s Interconnect Symposium at SEMICON West, hosted by Kulicke & Soffa and Advanced Packaging magazine, shared insights into a list of trends, challenges, and opportunities in advanced packaging (e.g., wire-bonding and flip-chips) that are being thrust into the semiconductor manufacturing spotlight.

“This is one of the most exciting years in the industry with all the developments happening,” noted TechSearch International founder/president E. Jan Vardaman. “If you’re an advanced packaging engineer, you’re finally getting the recognition you deserve.”

Speaking to a packed audience, Vardaman led off with an analysis between wire-bonding and flip-chip trends. Advanced packaging accounted for 30% of the total packaging market in 2006, and will grow to 36.5% in 2010, according to Vardaman. “A lot of companies will tell you that their money is being made in advanced packaging,” she said.

The usual casts of characters — mobile phones, PDAs, and MP3 players — are driving the market, and the thin-is-in craze that started with Apple’s iPod is expected to continue with the iPhone, which reportedly sold more than 700,000 units in the first weekend. “There’s cool packaging inside this thing,” Vardaman noted, showing images of an iPhone teardown to identify many wire-bonded parts and a few wafer-level packages, including an Intel stacked-die package, and package-on-package (PoP) technology from Samsung consisting of a microprocessor in the bottom package with two stacked die in the top.

Stacked-die packaging reached 2.2 million units in 2006, and TechSearch expects that to hit 3.2 billion units in 2010. It has been demonstrated that 16 die can successfully be stacked, though 4-5 is more commonly seen, Vardaman noted, adding that most of these stacks are wire bonded and gold-stud bump bonded.

Looking ahead, Vardaman said that stacked package trends forecast thinner packages with higher levels of stacking and multifunctional chips. Challenges include wafer thinning and die attach, wire bonding, material selection, thermal performance, and business issues of logic and memory — the latter having driven PoP development. At least 10 major OEMS in handset and digital-still-camera markets have adopted PoP, due to the ability to use known-good-die (KDG). In 2006, 67 million PoPs shipped, and that number is expected to grow, Vardaman noted.

For IC packages, wire bonding contributes 124 billion units, or about 90% of the total available market. The remaining 10% are bumped die, though market penetration could increase to 14.9% by 2010, Vardaman suggested. Advanced packaging continues to grow in units and revenue, and 67% of all advanced packages are wire bonded — so why doesn’t flip-chip dominate? “We use what’s best suited to the technology at hand,” said Vardaman, explaining that flip-chip is used when needed for performance or for pad-limited designs. But because it’s more expensive (~30%) to build, “it’s used because you have to use it, not just for grins.” She noted that Intel has delayed major flip-chip adoption out to 2009, because wire bonding still produces viable products. And wire-bond technologies continue to advance, making the transition to flip-chip less critical. “Conventional technologies don’t stand still while novel technologies are developed,” Vardaman concluded.

Other Interconnect Symposium presenters included Stephen Lee, chief scientist at Freescale, who talked about the company’s bond-over-active (BOA) evolution and addressed the issue of metal lift failures; and Flynn Carson, STATS ChipPAC, who addressed advancements in stacked die packaging and interconnect schemes. Carson says we’re headed to increased density with through-silicon vias and 3D systems-on-chip, but that these processing developments are still a few years out. All levels of interconnection integrated together will support the next generation of highly functional cell phones, he added. Bob Chylak, Kulicke & Soffa, explained how to control pad structural damage for ultra-fine pitch copper wire. –F.v.T.

The SEMICON West Interconnect Symposium presentations will be available online at “http://www.kns.com.

July 18, 2007 — Accelrys Inc., maker of computer aided nanodesign (CAN) products, has released a new version of its QMERA software. Developed by the Accelrys Nanotechnology Consortium, QMERA is a multi-scale method that enables users to include quantum mechanical and molecular mechanic methods (QMMM) simultaneously through a hybrid simulation approach. The update will be commercially available to members of the Nanotechnology Consortium as part of Materials Studio 4.2, expected to be released this month.

Accelrys launched the Nanotechnology Consortium in 2004 to develop and commercialize “innovative science that helps researchers investigate complex models of nanostructures and devices.” The consortium says its success is measured not only by its 29 members, but by the amount of new software solutions it has developed to meet customers’ needs. In addition to QMERA, Nanotechnology Consortium development efforts have resulted in software included in Materials Studio 3.2, 4.0 and 4.1. The software includes ONETEP, a linear scaling quantum mechanics program and GULP, a force field package for calculating a wide range of materials properties.

Accelrys has also added new members to its Nanotechnology Consortium, including the National Nanotechnology Center (NANOTEC) in Thailand, and DENSO Corporation. Accelrys plans to launch Phase II of the Nanotechnology Consortium later this year.

Active Heat Spreaders


July 16, 2007

The CL-1000 series of heat spreaders offer a large, flat, and thin surface area to connect components and thermal interface materials (TIMs), or serve as a heat pipe or heatsink. The products are reportedly 44% lighter than pure copper and 10–15&#215 more thermally conductive.

July 12, 2007 – Taiwan foundry United Microelectronics Corp. (UMC) and SEMATECH’s Advanced Technology Development Facility (ATDF) are extending their year-long collaboration to evaluate “emerging technology products,” focusing on specialty technologies such as nanotech and memory designs.

ATDF will assess feasibility and perform qualification testing for groups or companies technologies; UMC then will review ATDF’s test results to evaluate the technologies’ manufacturability and commercialization potential, and select potential manufacturing partners.

The extended partnership “gives technology innovators an important new resource for implementing their best ideas,” providing a clearer path to manufacturing in a foundry, particularly important for the industry’s smallest players, noted Dave Anderson, ATDF general manager, in a statement.

Joe Ko, VP of UMC’s specialty technology division, added that the partnership not only keeps UMC at the edge of semiconductor R&D, it also helps UMC target more fabless firms and startups who need a manufacturing partner to commercialize their IP.

UMC and ATDF originally forged the partnership in May 2006, under which ATDF was to manage several custom technology development projects. UMC has stood out as the only major foundry player without participation in some kind of partnership or consortium to develop leading-edge process technologies. Rival TSMC had worked with Crolles2 Alliance partners Philips, STMicroelectronics, and Freescale Semiconductor, while Chartered is allied with IBM, and SMIC has ties to Infineon and Toshiba.

July 12, 2007 — Xidex Corp. has been awarded a new contract from the National Science Foundation (NSF) to develop Selective Nanotube Etching, a process designed for manufacturing carbon nanotube (CNT) devices.

The project will enhance Xidex’s CNT device manufacturing process and produce a new tool that other nanodevice developers can use for product fabrication or repair. Xidex will work in collaboration with The University of Texas at Austin’s Department of Chemistry and Biochemistry, and the University of Tennessee’s Department of Materials Science and Engineering.