by M. David Levenson, Senior Technical Editor

The special Friday session of BACUS ’06, organized by Bob Naber of Cadence, addressed the question of industry progress and readiness for DFM, and discussed the remaining challenges as well as proposed solutions. Mark Mason of Texas Instruments pointed out that “DFM is a journey, not a destination,” and worried that management did not yet understand how hard it was going to be. Michael Lercel, director of lithography at SEMATECH, noted that all manufacturing options have limits that must be respected by designers. In particular, said Lercel, limiting the number of exposures needed for “double patterning technology” to merely two will require design restrictions. He worried that variability will limit CD uniformity no matter what, and that the 1.2nm (3σ) spec for 32nm half-pitch on the ITRS roadmap is just unfeasible — even for EUV. If so, designers will have to learn to accommodate more variability.

Luigi Capadieci of AMD captured part of the challenge, saying that the pages of
design rule manuals are growing exponentially: 250 pages today and 2000 predicted for 22nm, most of them “restrictive rather than prescriptive” — basically, pages and pages of things not to do, but little information as to what should be done. Still, tools are becoming available and design info is being shared with metrology and APC. What is needed more than anything, according to Capadieci, are standard interfaces to facilitate sharing.

Naoya Hayashi of DNP lamented that the total edge length on a typical mask is now 42km — the length of a marathon run — and mask inspections are expected to find 20nm sized defects or anomalies on this route. Just writing a 45nm CD mask takes 30 hours today, even before inspection and repair. For maskmakers, he predicted the key DFM tool will be a “mask behavior model.”

At Intel, the main DFM approach is “designing variety out,” according to Sunit Rikhi, Director of Advanced Design. He described a unique organization that transformed tape-out into the technology module (DMW, for “design-mask-wafer”) where manufacturing begins. The Intel DFM framework deals with variability in three stages: mitigation, co-optimization (both for design and manufacturing), and control.

Fabless companies have a completely different challenge, as described by Tim Horel, VP of hardware development at startup Tabula, and Artur Balasinski of Cypress. Depending on their phase in the technology cycle, different companies have different needs, with DFM enabling leading-edge products but “only” increasing yield for trailing nodes. Horel believes that improving the education of designers is crucial, and foundries should be responsible for facilitating it.

There is quite a ways to go before mask customers understand what actually can be made, according to data presented by Peter Buck of Toppan Photomasks. He reported that 13% of masks have unresolvable data that cannot be transferred to the physical plate, and that 16% of that is in the main pattern, rather than scribe lines, fill, or company logos. Mask-makers are left to guess at the designer’s intent, and have disincentives for alerting customers (who may go elsewhere) of the problem. To ship product, questionable regions are often labeled “do not inspect” (DNIR), with little or very late customer input. While mask rule check (MRC) procedures can mitigate this problem, the EDA tools owned by many customers cannot comply with MRCs, according to TI’s Mason.

Kevin Lucas of Freescale Semiconductor outlined the difficulties of implementing something as new as DFM in our complex industry environment. Even though implementing DFM would conservatively increase yield by 2% across the industry and save $4 billion, comparable to the entire revenue of the EDA industry, DFM is still a hard sell. For example, it requires at least three split lots to document a 1% yield increase — and it is possible that DFM methods can actually reduce yield. Thus, DFM is adopted only for the minority of designs where large improvements can be documented or are expected with confidence. David Lan of leading foundry TSMC also lamented the difficulty of convincing designers to adopt DFM methods, partly because it is so hard to estimate the return-on-investment early in the process. (And several speakers alluded to the perception that designers have always moved on to other things before the DFM problems appear, so there is no one to whom fab engineers can complain!)

The resistance to adopting best practices is, perhaps, the reason that so much of what happened at BACUS this year seemed like marketing rather than technology — we generally know what to do to live with the pattern transfer capabilities, but cannot yet bring ourselves to do it. Promoters of DFM and EDA tools need to adapt them to current processes so they do not seem disruptive and, in the words of Wojtek Poppe of U. California-Berkeley, help designers develop a gut feeling for manufacturability. Once today’s good ideas are adopted, the way may be cleared for something really new. — M.D.L.

What are the real pain points of DFM that are being underestimated? How can we take the step to embrace and assimilate DFM capabilities, and clear the way for some really new concepts?