(September 13, 2010) — U. K. Klostermann, T. Mülders, T. Schmöller, W. Demmerle, Synopsys GmbH and G. F. Lorusso, E. Hendrickx, IMEC, assess the readiness of rigorous physical resist model calibration for accurate EUV lithography (EUVL) simulation — first, summarizing the experimental setup for the EUVL and discussing pattern selection for calibration, then illustrating the speed and robustness of model building, which allows overnight determination of accurate models. Next, they examine the results of the model validation performed using an independent dataset (i.e. data not included in the calibration). The predictability of the resist model is demonstrated across various flare levels, pitches and critical-dimension (CD) ranges, and the impact of 3D mask effects, resist profile information and other factors is discussed. Finally, the article will look at the application of the calibrated resist model to a reticle with a different mask stack, to demonstrate that observed across-die CD fingerprint characteristics can indeed be reproduced by simulation.
As chip manufacturers develop strategies to accommodate the coming 16nm technology node, many consider extreme ultraviolet lithography (EUVL) a key contender for patterning these ultra-deep-submicron devices. While rigorous physical models have already proven powerful for EUV modeling, [1] limited tool time is available to perform experiments, despite the steady buildup of an EUVL infrastructure. This fact underscores the critical need for an accurate, predictive EUV lithography process simulation to enable reliable pre-production studies.
Therefore, not only EUV-specific imaging effects such as flare, 3D mask shadowing and horizontal-vertical (H-V) bias need to be captured by the simulator, but also the patterning behavior of EUV photo resist. Due to their partly empirical nature, computational resist models need to be calibrated against experimental data to ensure a high degree of predictability.
During the phase of EUV process development, there is a wide range of EUV resist candidates that need to be evaluated, each of which requires a well-calibrated resist model. The analysis of various material options requires a fast, efficient resist model calibration process.
EUV lithography process development
Proven equipment and stable process conditions are the key to reliable results. Equipment and materials deployed for this calibration study included ASML’s EUV alpha demo lithography tool, on which all test wafers have been exposed; Shin-Etsu’s SEVR-59 photo resist, representing IMEC’s baseline process; Synopsys’ Sentaurus Lithography simulation software and the accompanying resist calibration module; and a Hitachi CG4000 scanning electron microscope (SEM) for measuring CD data used for resist model calibration and validation. All exposures were performed using IMEC’s TM08 reticle, which holds a wide range of one-dimensional (lines and spaces) and two-dimensional (line end structures and contact holes) test patterns with various dimensions in horizontal and vertical orientation.
Wafer stack & resist process conditions
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Substrate: Silicon (plain)
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Resist: Shin-Etsu SEVR-59
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Underlayers: Not applied
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Resist film thickness: 65nm
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Exposure settings: ASML EUV ADT
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Wavelength: 13.6nm
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Numerical Aperture: 0.25
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Source shape: Circular; σ = 0.5
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Flare TIS: 14%
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| Figure 1. Process and simulation conditions for (a) wafer/resist stack properties and (b) exposure tool settings on the ASML alpha demo tool (ADT) at IMEC. |
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| (c) Cross section view of the mask; due to the reflective geometry of the exposure process, light inclines at an angle of 6 degrees. The topographic nature of the absorber stack is causing a shadowing effect. |
(d) Cross section view of the simulated aerial image in resist (bulk image); the shadowing effect results in a different imaging properties for horizontal (H) and vertical (V) lines, visible as pattern shift and CD differences (H-V bias). |
This study uses a large experimental CD dataset that was initially generated for optical proximity correction (OPC) model calibration and validation. Figures 1a and 1b provide the high-level process conditions for the resist stack properties and exposure parameters. The basic geometry is illustrated in Figure 1c, showing the multi-layer mask blank (40 pairs of molybdenum/silicon (MoSi) bi-layers) and the structured absorber stack, which consists of three different material layers. For all simulations, the layer thicknesses were as given by the mask shop, and material properties used n/k refractive values from the CXRO website [2]. The topographic nature of the absorber stack in combination with the oblique incident of the light onto the mask (6-degree incident angle) is causing a shadowing effect, which results in different imaging properties for horizontal (H) and vertical (V) lines, visible as pattern shift and CD differences (H-V bias), as shown in Figure 1d.
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| Figure 2. Typical FEM data set for a specific feature, in this case 32nm dense lines & spaces, vertical orientation. The x markers indicate the experimentally determined CD results, averaged over 5 independent SEM measurements. The solid lines represent simulation results based on the calibrated resist model. |
A key factor for running an effective calibration, yielding in a predictive model, is the selection of test patterns forming the calibration data set. In this case, the data set consists of 12 different focus exposure matrices (FEMs) varying in line width (nominal 32, 36, and 40nm), pitch (isolated and dense) and pattern orientation (vertical and horizontal) to ensure a good coverage of the test pattern parameter space. The calibration considers a subset of matrix points along the focus and exposure ranges: for this experiment, -0.15μm to +0.15μm in 7 steps, and 17 ±4mJ/cm² in 9 steps, respectively. Each CD data point is based on the average of five independent measurements, which usually fall within a 2nm CD range. Figure 2 shows a typical example of measured FEM data points for a 32nm dense line with vertical orientation (markers), as well as the simulation results using the calibrated resist model (solid lines).
Model calibration highly scalable for multiple cores
The Resist Calibrator module of the lithography simulation software was used to perform the entire calibration, optimizing a sub-selection of the available resist model parameters in order to match simulation and experimental data. These free parameters included diffusion- and kinetic-related coefficients, as well as parameters impacting the aerial and bulk images, such as the zero-focus offset to adjust for the exposure-tool-dependent zero-focus plane.
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| Figure 3. Scalability of computational calibration run time vs. the number of active CPU cores at 3 GHz clock speed: Even on a four core CPU, a calibrated model can be obtained within a single day — trading convergence criteria against computation time. |
A highly efficient optimization algorithm and parallelization techniques enable fast turnaround time on model building. Moreover, it is possible to balance the computational time against convergence. For this specific dataset, convergence occurred very fast, allowing a typical model error of 0.9 to 1.1nm. The EUV resist model calibration set up described herein achieved a typical computation time of between two and 10 hours, where parallelization techniques can be applied to reduce the calibration time. This allows several different nominal setups to be investigated within a single day. Figure 3 shows the calibration’s excellent scalability under shared memory operation as a function of the numbers of cores for two convergence conditions.
Assessing the quality of a resulting resist model requires investigating the fitting quality of the calibrated model by predicting the CD results of an independent validation data set. We used the weighted CD root mean square deviation (RMSD) to quantify the results.
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| Figure 4. Inspection of CD deviation for all calibration data points. a) The maximum CD deviation between measurement and calibrated model is less than 2 nm for process conditions near the center of the process window (PW; focus range -0.05 to 0.05μm, dose range 15 to 20 mJ/cm); b) Visual SEM top down image inspection on an outlier (e.g. here: 32nm horizontal dense line, 14 mJ/cm², -0.1μm) shows that metrology artifacts and large CD range of calibration data points are responsible for the large observed deviation. c) For reference, the SEM top down image of a 32nm horizontal dense line at nominal best process condition (17 mJ/cm², 0.0μm) is shown. |
After parameter optimization, the RMSD of the calibration dataset is 1.1nm when all weights are set to 1. As seen in Figure 4, near-best-process conditions (focus range 0.05 to 0.05μm, dose range 15 to 20mJ/cm², exposure latitude 28%) yield a 2nm maximum CD deviation, which is comparable to the CD range for the input data of a given data point. For process conditions at the process window edge (focus ±0.1μm or 13, 14 and 20mJ/cm²) the CD deviation is found to be higher. Large deviations between experiment and model may reflect issues not with modeling quality, but rather with the data-collection process indicating CD metrology issues. Here, SEM top-down images should be used to validate experimental data points and exclude metrology artifacts (Figure 4b) by comparing them to reference measurements (Figure 4c).
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| Figure 5. Prediction of resist profiles of a 40nm half pitch line for two different calibrated models. a) Only measured CDs are used as calibration data set. b) A single resist height measurement data point e.g. based on SEM cross section is additionally included, resulting in the desired amount of resist loss. c) For comparison the corresponding experimental data is shown. |
Results detail optimal calibration performance
Resist profiles. Figure 5 illustrates the simulated resist profile for a 40nm half-pitch pattern using two different resist models: 5a) no profile tuning performed during calibration, and 5b) including resist profile height information obtained from a single data point through a cross section image. During model calibration, relevant parameters impacting the resist profile shape, e.g., acid top-out diffusion or surface inhibition effects, were co-optimized to ensure that calibrated resist models would reflect real resist loss following the patterning process. The resulting simulated resist profile shapes match experimental data both qualitatively and quantitatively very well, as shown in Figure 5c. The reported simulated CD corresponds to the line width obtained at the bottom of the resist profile.
Flare modeling. The predictive power of a calibrated resist model can also be demonstrated by validating the model against data obtained under different exposure conditions. IMEC’s TM08 allows the investigation of flare effects by providing all test pattern within areas representing three different flare levels, low (4.3%), mid (6.3%) and high (8.3%), based on the point spread function (PSF) provided by the exposure tool supplier [3]; within each environment, the flare level is controlled by the dummy fill pattern density. With the resist model calibration being carried out on data obtained in the mid flare regime, Figure 6a shows that the CD values of data points obtained in the high flare and low flare regime can equally well be predicted, yielding RMSD results of around 1nm for all conditions. For comparison, the RMSD values are also calculated for the nominal design CD and the experimental data anchored at mid flare level and horizontal orientation. This demonstrated the improvement in accuracy when using simulation based on a calibrated resist model. However, this also indicates that significant effects such as flare or shadowing need to be properly taken into account in the modeling process on which the calibration is based.
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| Figure 6a) RMSD values for groups of validation data (flare level, orientation). The calibrated model achieves a RMS ~1nm or below for each sub-set. For reference, the RMS is also calculated by directly comparing nominal design CD and experimental wafer CD (nominal design) (b) CD deviation through pitch for the validation data for both, nominal line width and corrected line width based on mask CD metrology (data for medium flare level only shown). Especially for small pitch ranges below 100nm mask error correction turns out to be mandatory. |
Mask metrology error and through-pitch validation. Figure 6b shows an example for a through pitch validation, demonstrating that mask-linewidth knowledge can significantly affect the quality of a resist model calibration or validation. In case the validation is carried out based on nominal mask CD information, the simulation results are on target for the isolated lines, but show a systematically too-wide mask CD for dense lines (dark markers). However, running both calibration and validation based on corrected masks CD data, obtained after an individual mask metrology step, significantly smaller deviations between simulated and measured wafer CDs are observed across the entire pitch range (light markers).
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| Figure 7. Intra-die CD uniformity (CDU) for 32nm dense lines (horizontal H and vertical V). a) The experimentally observed signature could be reasonable well be modeled by considering mask CD, dose, focus and shadowing effects. b) The quantitative agreement between experiment and models is very good and RMS is found to be 0.3nm. |
Prediction of CD uniformity behavior across the exposure field. The physical nature of the models used here in EUV lithography process modeling also allows the assessment of related effects or data obtained with a different reticle. In this example, the individual contributors to the CD uniformity budget across the exposure field are investigated. Based on the calibrated resist model described above, simulations were carried out taking new setup parameters into account, such as different absorber stack properties of a new test reticle, individual mask CD error corrections, azimuth angle on the mask (depending on the position in the field), and the intensity signature of the EUV tool across the exposure slit. Figure 7 compares the experimental and simulated CD data for a 32nm dense line pattern for the various field positions. The RMSD is around 0.3nm, with 1nm maximum deviation between simulation and experiment. This agreement confirms the relevance of the contributors mentioned above to CD uniformity, as well as demonstrates the high accuracy of the experimental methodology, and the predictive power and the portability of the calibrated resist model.
Conclusion
Advanced technology nodes, down to 16nm and beyond, are likely to utilize EUV lithography for printing critical features. The engineering challenges associated with the EUV process, limited access to first-generation exposure and processing equipment, and the high cost involved in running experiments make lithography simulation a perfect tool to support process, equipment, and material development. To make the most of simulation technology, lithographers need calibrated resist models with predictive accuracy. The work described in this article demonstrates the readiness of an effective and efficient model calibration methodology enabling the rapid generation of accurate and predictive EUV resist models. The application examples prove the readiness of such calibrated physical resist models to enable accurate EUV lithography simulation.
The availability of calibrated resist models in physics-based lithography simulation tools is an important milestone paving the way for EUVL to volume production. The rigorous simulation approach delivers three dimensional resist profile information, which is crucial to the early assessment of the quality of compensation strategies for EUV specific effects in mask synthesis and manufacturing applications.
References
[1] Bienert, M. et al. , “Imaging budgets for EUV optics: Ready for 22 nm node and beyond,” Proc. of SPIE Vol. 7271 72711B-1 (2009)
[2] CXRO website: http://www.cxro.lbl.gov/
[3] Meiling, H. et al., “Performance of full field EUV systems,” Proc. of SPIE Vol. 6921 69210L-1 (2008).
Ulrich K. Klostermann received his doctor’s degree in Physics from the University of Regensburg (Germany), and is Corporate Application Engineer at Synopsys GmbH, Karl-Hammerschmidt-Strasse 34, D-85609 Aschheim/Dornach, Germany; ph.: +49 89 993 20116; email: [email protected]
Thomas Mülders received his doctor’s degree in Physics from the RWTH University in Aachen (Germany) and is Senior R&D Engineer at Synopsys, GmbH, Aschheim, Germany.
Thomas Schmöller received his diploma in Physics from the University in Erlangen (Germany) and is CAE Manager at Synopsys, GmbH, Aschheim, Germany.
Wolfgang Demmerle received his doctor’s degree in Physics from the Technical University of Munich (Germany) and is Product Marketing Manager at Synopsys, GmbH, Aschheim, Germany.
Gian F. Lorusso received his PhD in solid state physics from the University of Bari (Italy) and is Researcher at IMEC, Leuven, Belgium.
Erik Hendrickx received his PhD in physical chemistry from the University of Leuven (Belgium) and is Senior Researcher at IMEC, Leuven, Belgium.
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