by Tom Cheyney, Senior Contributing Editor, Small Times

Although double-patterning immersion and extreme ultraviolet (EUV) lithography may be the next-generation approaches currently favored by the semiconductor industry for scaling down the technological roadmap, several other technologies have made significant progress and could emerge as alternatives, both for future chipmaking needs as well as for high-density patterned disk media and other nanomanufacturing applications.

At the SPIE Advanced Lithography conference, presentations on electron-beam direct write (EBDW), nanoimprint (NIL), and other potentially disruptive patterning technologies drew strong attendance and elicited spirited discussion. Seagate‘s Xia-Ming Yang talked about experimental results that underscore the challenges of fabricating high-resolution master templates for bit-patterned media (BPM), the leading candidate to replace the current magnetic recording head technology.

E-beam clustering: Benefits and concerns

Electron-beam lithography, although the sole method for achieving the potential precision and resolution needed, suffers from very slow write-time throughputs that can stretch on for days, according to Yang. Other issues include e-beam tool availability, photoresist and metrology limitations, and difficulties in uniformly patterning and accurately placing the small dots that make up the magnetic BPM nanoarrays.

Once the master is fabricated, thousands of disks would be replicated from it using UV nanoimprint techniques. Despite the obstacles, Yang said that the EBDW and NIL combination “is probably the only way to go for manufacturing,” because of single-digit-nanometer-scale resolution capabilities, throughput, and cost requirements. But for the technology to achieve production worthiness, “a rotating-stage electron beam with high beam current is urgently needed for template mastering.”

TSMC‘s Burn Lin, credited with being a prime mover behind the semiconductor industry’s adoption of immersion lithography, said, during a panel discussion on massively parallel tools for nanotechnology, that multiple electron-beam direct-write systems — with their superior depth-of-focus and elimination of optics, mask CD, and overlay costs — could provide a better solution than EUVL for next-generation chipmaking requirements.

For EBDW schemes to achieve the required throughput, “obviously” they need to be clustered, Lin said. “Let’s say that I’m clustering five of the 20 wafer/hour tools. If one of them goes down, you lose only 20%; you have the other 80% going,” he explained. “If you have an [EUV] scanner going down, you lose the throughput altogether. If you cluster the [e-beam tools], there’s a chance that you can share your intrafield or interwafer data, so in this way you are saving the cost of your data processing unit.” Data rates can thus be slowed because tasks are done in parallel, he noted. “You don’t have to push for the state-of-the-art of the data transmission rate.”

Acknowledging the “real challenges” in multiple EBDW, Lin listed several concerns. “You have to worry about the brightness of the source, so you can maintain your throughput. You have to worry about those massively parallel electron optics, you have to worry about contamination of the optics, and you have to worry about data rate and the cost of electronics.”

“Not for IC lithography,” but still useful

One quite different but potentially disruptive technology, described by Zyvex Labs’ John Randall in a panel presentation: scanning tunneling microscopy (STM)-based hydrogen depassivation lithography, used in conjunction with atomic layer deposition and epitaxy processes. “Let me say right off the bat, this is not for IC lithography,” he said, acknowledging that throughput will be “abysmally small.” Still, he noted that there are useful applications, such as creating 3D top-down controlled structures in silicon, and perhaps expanding to other material systems.

“We’re using the limit of a thin resist, a monolayer of hydrogen, and just getting electron desorption of hydrogen from a silicon surface,” explained Randall. “You can drop down into tunneling range and vibrationally excite the single silicon hydrogen bond and in fact pop off individual hydrogen atoms” — which, he said, could in principle enable “absolute perfection” in lithography.

Noting that a single STM tip will be very slow, Randall said the work will focus on going parallel, using MEMS-based closed-loop nanopositioners (currently in development at the National Institute of Standards and Technology), “at first in a moderately parallel way, with [scanning probe] arrays where each individual scanner has three dimensions, three degrees of freedom, and closed-loop positioning capabilities.”

Admitting that this “will be very tough,” Randall noted that “we can look back to the last century and pull out some old tricks.” One such ploy would be “taking advantage of the silicon lattice for the in situ fiducial grid, to keep very good precision — in fact, absolute precision — not only in critical dimension but in pattern placement.” — T.C.

by M. David Levenson, Editor-in-Chief, Microlithography World

(Fourth in a four-part series)

Avoiding unprintable structures will be essential for manufacturing 45nm and smaller circuits, and that was reflected in a series of papers on design for manufacturing and design rule restrictions, some of them quite aggressive.

Avoiding unprintable structures will be essential for manufacturing 45nm and smaller circuits, and that was reflected in a series of papers on design for manufacturing and design rule restrictions, some of them quite aggressive. Keynote speaker Andrew Kahng of UC San Diego introduced the idea of “design for equipment” (DfE), where designers learn to accommodate specific patterning and metrology capabilities. The most dramatic example was presented by a collaboration of NXP semiconductors and ASML which found a way to make 45nm logic cells using a 0.93NA 248nm scanner. They key was a very constrained grating like layout. However, the area of the cells increased ~15% compared to a more typical layout for high-NA immersion production.

The idea of a 1D grating-like design was taken to an extreme, perhaps, by Mike Smayling and Tela Innovations, who showed how libraries of standard cells could be converted to 1D layouts and snapped together. Simulations using the Brion Tachyon system revealed much improved process latitude, and many Tela designs were actually smaller than their 2D predecessors.

In his keynote for the DfM sessions, Lars Liebmann of IBM foretold an era of “hard DfM” where all challenges would have to be addressed through computation. That differed from the recently past time of “soft DfM” where marginal improvements were occasionally made by optimizing geometries, but much more of the progress resulted from improved tooling. That time is over. From now on, according to Liebmann, all tradeoffs will have to be integrated into one seamless design and process flow. To begin getting the industry to speak the same language, Liebmann announced a project within the Silicon Integration Initiative to capture and regularize DfM terminology and mentioned nine other DfM related programs at Rensselaer Polytechnic Institute.

The increased apparent importance of computational lithography launched something of an arms race among OPC and EDA companies. It began, as these things do, with Brion/ASML announcing an improved Tachyon monolith for faster OPC optimization. Gauda, a stealth start-up, decloaked to tout its method of cheap commodity graphical processor units for OPC, for only $300,000. Mercury Computer Systems announced that its cell-processor based blade accelerator (CPA) had been qualified to run Mentor Graphics’ nmOPC for 45nm production at IBM. Previously, IBM had been using BlueGene for heavy-duty litho simulation. The smallest Mercury 25U dual cell-based blade system (with 14 blades) runs at 1 teraflop for $250,000, according to Jim McKibbin of Mercury. On a network, it looks like just another node. Since the Cell can be reprogrammed using software (unlike an FPGA) and is intrinsically parallel (unlike x86’s), Mentor and Mercury believe the system is more flexible than other commercial computational lithography hardware.

No one outside Intel knows what it is using for its production and pixelated mask designs, and rumors of even faster kludges could be heard in the hallways. So, while there is no new wavelength or exposure tool, there seem likely to be new litho computers and applications. — M.D.L.

Click here for all the separate analyses from this package of SPIE writeups: a list of what’s still needed to enable 32nm generation chips printed with double patterning technology; problems, yet promise, in development of EUV; litho projects (e.g. phase-shift and high-index immersion) that are falling behind the curve, and others that need a boost (e.g. imprint); and clever new technologies added to the equation, and what’s sparked an “arms race” among OPC and EDA firms.

by Bob Haavind, Editorial Director, Solid State Technology

Feb. 26, 2008 – While 193nm immersion lithography has taken the industry to 45nm it will get progressively tougher to move below that. Lithographers will struggle with shrinking margins, more metrology and process control, along with extensive computation, plus double exposure for critical layers which multiplies their problems.

The SPIE Advanced Lithography Conference in San Jose, CA, is exploring this road ahead. Below 40nm, lithography becomes much more sensitive to stepper variation, and computational optimization will be required, according to Martin van den Brink, EVP, ASML, in a plenary talk. Lithography uniformity becomes critical, and metrology will be very difficult, especially with double exposure.

“Stepper controls are not well used today,” he said. It is possible to adjust dose point-by-point across the wafer, he suggested, but only with a tremendous amount of computation. Angle-resolved scatterometry feedback loops in production with a DoseMapper recipe might provide optimization. There also must be increased feedback from manufacturing to design, van den Brink added.

While EUVL continues on track for 22nm, he believes that memory makers will make strong use of double-patterning before going to EUV. Overlay and CD control using application-specific scanner tuning with fast, integrated metrology feedback will help make this possible, according to van den Brink. The process will also require pattern-split software.

D. Mark Duncan, president/CEO of Micron, agreed in his plenary talk that double patterning will be needed for future memory cells, but as the shrink continues, he foresees accelerating patterning costs. Going to 3D will forestall the move below 32nm for a time, he suggested.

Pushing NA higher for immersion lithography using new lens materials and a higher index-of-refraction fluid, could help reduce the challenge. But this will not be an option for 22nm, pointed out Toshikaya Umatata, GM of development headquarters for Nikon Precision, in a presentation a day earlier.

“High index does not match with the Roadmap,” he stated. Instead, at 22nm, EUVL will be the only candidate for general patterning, he added.

Micron’s Duncan did an analysis that supported this view. “I am confident that EUV is at the end of the Roadmap,” he stated. He sees EUV as the route to lowering rising patterning costs in the 2010-2012 timeframe. Duncan pointed out that chipmakers have to make massive bets on new factories, spending $3B on a new fab, much more than for an auto assembly plant, for example. Only an offshore rig, at $1.5-$2B, comes close. Yet, Duncan showed that the incremental gain in dollars/die would be shrinking significantly over the next few nodes.

ASML’s van den Brink took note of this investment concern in discussing the push toward higher productivity exposure tools. An analysis shows that acceleration is much more critical than scan speed, he explained. Right now, he said, an immersion tool can move at 600mm/sec, but to boost productivity further, the goal is to push that beyond 1m/sec, with lower defects and even tighter metrology overlay capability, moving from 4nm down to 2nm. Current 193nm immersion tools reach an NA of 1.35 without new lens materials and higher-index fluids, which is scalable down to 38nm, he said. Then double patterning, and eventually EUVL, will be needed.

While some experimental EUV tools are in operation, the technology will not be suited for volume production until an entire infrastructure is in place, pointed out Ben Eynon, associate director of SEMATECH’s lithography division in Albany, NY (assigned from Samsung). He reviewed the EUV infrastructure status at a pre-conference session organized by KLA-Tencor.

A major concern is an X-ray source that can deliver sufficient power to the wafer to meet reasonable throughput goals. Current sources can deliver 6W to an intermediate focus point, but 180W will be needed. “We need two orders of magnitude improvement, and that is a big challenge,” he said.

One source candidate is a discharge-produced plasma (DPP), but this involves a heavy heat load and does not scale well. More promising, according to Eynon, is a laser-produced plasma (LPP), using droplets of tin. The burst power needs to be focused, but the scalability is promising, he said.

EUVL will also require a resist that provides high resolution, allows adequate throughput, and minimizes line-edge roughness (LER). Right now, candidate resists that meet one requirement fail at the others, so improved materials will be needed to meet all three together.

Reflective reticles are essentially mirrors that must be flawless, Eynon explained. Any flaw on the glass substrate is greatly amplified after depositing 80 alternate layers of silicon and molybdenum over a 10hr period — any pit or particle would build up, making the reticle useless. Methods are being developed to remove any particles over 4nm high, and each layer may be smoothed out as deposition proceeds to minimize potential flaws. The eventual target is about 1 defect every 5 blanks or so, Eynon said.

For production, an EUV aerial imaging tool will be needed, he said, but the market will be so small that SEMATECH will need to help in the development.

“EUV still looks more cost-effective than double exposure, if we can develop it in a reasonable time,” Eynon explained. “That’s why we’re still pushing.” — B.H.