Category Archives: SEMI

By Debra Vogler, SEMI

The demand for smartphones and other portable devices that need efficient power management is driving the analog IC market. Additionally, growth is fueled by the Internet of Things (IoT) and the MEMS/sensors devices that enable it. To explore the supply chain opportunities within the analog sector, including MEMS/sensors, SEMI introduced the Analog and New Frontiers Program at SEMICON West 2016. This program — part of the Extended Supply Chain Forum — will feature four, hour-long sessions, each focusing on a different supply chain challenge or area of interest within the analog sector. One of the featured speakers will be Dr. Peter Hartwell, senior director of Advanced Technology at InvenSense. Dr. Hartwell’s pre-show interview provides a provocative look at supply chain challenges facing MEMS/sensors manufacturers.

Perhaps the most significant challenge facing manufacturers of MEMS/sensors is commoditization of sensors and where the profits end up. “The windfall is going to the people enabling the applications at the top,” Hartwell told SEMI. “Especially with mobile devices and IoT.” He pointed out that if there isn’t a way for value capture at the lowest levels – i.e., the companies that enable the systems and devices that create the IoT experience – he predicts a plateau of innovation. “We won’t have the resources to push technology forward, so as a sensor company, we are trying to find ways to move further up the value chain to extract some of that value.”

Moving up the value chain, however, requires sensor companies to become more aware of system considerations. Design convergence is one way to accomplish this. “We think of design convergence as SiPs (System in Package) or SoCs (System on a Chip),” said Hartwell. “We start to put together our sensors with other capabilities, whether that means having processing power in our package or looking at different kinds of sensors that come together.”

He speculates about a time when there will be a single-chip IoT device, i.e., a one-chip device comprising sensors, storage, radio, power management, and perhaps even energy harvesting. “Maybe that’s where the convergence goes.” Still, in the end, the challenge becomes how the industry gets the money back to the bottom of the supply chain. “We’re inching up towards where that money is by building those systems and understanding what it takes to make them.”

The fabless model for MEMS/sensors

Aside from the commoditization conundrum, Hartwell sees another supply chain opportunity arising if the industry embraces a truly fabless business model. Such a model would be based on companies that only design the devices with the process kits arising from different companies. The fundamental question with that scenario, Hartwell notes, is how the various MEMS/sensors houses differentiate themselves.

Hartwell noted that InvenSense embraces the fabless model — the company has a Shuttle program with its foundry partners, TSMC and GLOBALFOUNDRIES. The InvenSense Shuttle gives MEMS developers the opportunity to fabricate their designs on the patented InvenSense Fabrication MEMS-CMOS integrated platform. Though competitors are not able to take part in the Shuttle program, it is available to universities and start-up partner companies. That said, Hartwell noted that the company keeps its ‘cards pretty close to the vest.’ So the challenge is how to open up that model while retaining differentiation when fabs and foundries tend to want to wring out cost from process development by using as much standardization as possible.

“The million dollar question,” said Hartwell, “is could we ever get to the point where the foundry tells the sensor companies what to do — the EDA companies would love to see this happen because it would lead to standardization of design tools and simulators.”

Opportunities for test and the digital interface

Test and packaging are two more opportunity areas for the supply chain. Hartwell pointed out that most MEMS/sensors companies do their own testing using their own test infrastructure. “It’s one differentiator that we haven’t been willing to give up,” said Hartwell. “So this is an opportunity for someone to come in and turn over the apple cart.”

With the proliferation of sensors that need to interface with a multi-chip system comes the challenge of having to connect using more and more pins. And though the industry has solutions for a digital interface to the sensor world, additional work needs to focus on making that interface robust. Hartwell explained that multiple interrupts and digital lines are needed and it gets complicated when you have five, six, or seven sensors in a system. “There are just not enough pins,” said Hartwell. “So we’re seeing a change in the wiring and the interface will have to be something new to solve the integration problem, which has become nontrivial.” He further observed that IoT is driven by four attributes: size, cost, power, and performance. “To get to the promise of IoT, it will take breakthroughs to get to a trillion sensors. You will have to reduce size, cost, power and performance, and some of those by one or two orders of magnitude.”

Wringing out costs with packaging (or, “no” package)

Hartwell minces no words when it comes to tackling size and cost in MEMS: packaging is MEMS. “This is the biggest opportunity to take out size and cost,” Hartwell told SEMI. “The influence of packaging on the transducer can’t be ignored. Packaging hurts the size, it hurts performance, and it’s something for which I don’t want to pay. It’s a huge opportunity for a shift.”

For Hartwell, the crux of the challenge is how to take a single piece of silicon that has a 6-axis sensor system, and then test it, trim it, ship it, and put it into whatever system it’s going into without changing its trim. While chip-scale packaging could be the opportunity the MEMS industry needs, he wants to keep the options open for other ways to break the paradigm.

What’s clear is that ample business opportunities exist for the supply chain within the MEMS/sensors sector to get rid of cost and size, address the test challenge, get rid of the package, and finally, new ways to handle and assemble parts.

To learn more, attend the Analog and New Frontiers Forum (part of the Extended Supply Chain Forum) at SEMICON West. The forum will be held on Wednesday, July 13, in four, hour-long sessions on the Keynote Stage, North Hall, Moscone Center. Check the SEMICON West 2016 website for more details and a list of confirmed speakers for each of the sessions.

TOKYO – November 4, 2015 – SEMI today announced further details on SEMICON Japan, bringing innovation to Tokyo Big Sight on December 16 through 18. SEMICON Japan, already the largest and most important gathering of the semiconductor manufacturing industry, has increased exhibition and programing in the high-growth Internet of Things (IoT) applications and technologies with its World of IoT pavilion. SEMICON Japan will also, for the first time, feature the Innovation Village, showcasing high-tech startups that bring the potential for new driving forces and new ideas for the future growth of the microelectronics supply chain.

Held in conjunction with SEMICON Japan, the World of IoT is a “show-within-a-show” and is the only exhibition showcase and conference in Japan to cover the complete Internet of Things supply chain, from silicon to system. Global key IoT industry players will showcase their applications and technologies including:

  • Alps Electric
  • Amazon Web Services*
  • Dassault Systems
  • Hitachi
  • IBM Research-Tokyo
  • Intel
  • Toshiba Healthcare Company
  • Toyota Motor
  • Tesla Motors*

*Amazon Web Services and Tesla Motors will have their booth at a SEMICON show for the first time ever.

The IoT conference programming will also feature speakers from the IoT key players including:

  • Amazon Japan – Kazufumi Watanabe, Vice President of Hardlines
  • Cisco Systems – Kazuhiro Suzuki, Managing Director, Cisco Consulting Services
  • Fujitsu – Chairman and Representative Director, FUJITSU LTD
  • Google – Shinichi Abe, Managing Director, Google for Work, Japan
  • IBM Japan – Toshifumi Yoshizaki, IBM Executive Staff, Watson
  • Microsoft Japan – Madoka Sawa, MTC Lead, Microsoft Technology Center
  • Nissan Motor Company – Haruyoshi Kumura, Fellow
  • Rakuten – Masaya Mori, Executive Officer and Representative, Rakuten Institute of Technology

Innovation Village is a new feature at SEMICON Japan that includes 20 emerging startups in an interactive exposition showcase arena. Attendees to the Innovation Village will gain key insights into new technologies and products, advanced research solutions, investment opportunities, as well as technology transfer and partnerships opportunities. The Innovation Village program will include start-up pitches and a “speed-dating” format for matchmaking between start-ups and venture capitals and corporate venture capitals.

Osamu Nakamura, president of SEMI Japan said “The World of IoT and Innovation Village bring new and fresh ideas, technologies, and partnership to SEMICON Japan visitors and exhibitors that are moving forward together to the IoT era.”

Platinum sponsors of SEMICON Japan 2015 include Applied Materials, Disco, and Tokyo Electron. Gold sponsors include Advantest, ASE Group, Daihen, Ebara, Hitachi Chemical, Hitachi High-Tech, JSR, Lam Research, Screen Semiconductor Solutions, and Tokyo Seimitsu.

For complete information of exhibits and programs, visit


At SEMICON Europa, attendees and exhibitors will delve into the technologies that shape the future of the microtech, nanotech, medtech and cleantech industries. Representing the entire supply chain from materials to electronic systems and services, 35 major European start-ups will participate in the Innovation Village and present their new technologies at SEMICON Europa.  The largest and most important semiconductor event in Europe, SEMICON Europa  will be held 7-9 October in the Grenoble location for the first time. The new three-day Innovation Village program will be the stage for emerging innovators, industry leaders, strategic investors, and venture capitalists to discuss the needs of the industry’s innovation engine. Attendees will gain insights on technology, capital, partnership, and collaboration strategies necessary for mutual success.

Innovation Village consists of a start-up exhibition (7-9 October), Silicon Innovation Forum (7 October) and Innovation Conference (8 October). As part of the Silicon Innovation Forum, all selected start-ups will have the opportunity to “pitch” to investors and SEMICON Europa visitors. The pitch session will be followed by a start-up panel discussion  “Fundraising for the Future Champions of European Electronics,” led by Jean-Pascal Bost of SATT-GIFT with panelists: Jacques Husser (Sigfox), Eric Baissus (Kalray), Serguei Okhonin (ActLight) and Mike Thompson (Hotblock Onboard).

The Innovation Conference, sponsored by Fidal Innovation, will bring together notable names in European innovation to discuss current practices and relevant funding issues facing semiconductor and high-tech start-ups today. Keynote speakers will include Nicolas Leterrier (Schneider Electric) on Innovation Practices and Dan Armbrust (Silicon Catalyst) on Lean Innovation. Christine Vaca (Gate1) will act as the conference chair.

“For the inaugural SEMICON Europa in Grenoble, our team was intent on developing a program that would highlight the strength of the local and the European ecosystems in innovation and new technology,” explains Anne-Marie Dutron, director of the SEMI Grenoble office. “At Innovation Village, visitors will discover the creativity of 35 European start-up companies, presenting their products, partnership and investment opportunities.”

Participating start-ups were chosen by a selection committee which included ten of the most recognizable venture firms in the industry: Applied Ventures LLC, Robert Bosch Venture GmbH, TEL Venture,3M Ventures, CEA Investissement, Samsung Ventures, Air Liquid Electronics, ASTER Capital), VTT Ventures, and  Capital-E.

Start-ups include ActLight (Switzerland), BlinkSight (France), BluWireless Technology (UK), Calao-Systems (France) and Silicon Line (Germany). For more information about Innovation Village, participating start-ups or about the Innovation Conference, please visit the SEMICON Europa website:

All events in Innovation Village, including the three-day start-up exhibition, Silicon Innovation Forum and Innovation Conference will be available at no charge for all SEMICON Europa guests and visitors. The event will be co-hosted by SEMI Grenoble and Gate1. The mission of GATE1 is to support the creation of new technology-driven businesses by capitalizing on the proximity of numerous university laboratories and research centers. GATE1 offers programs for technology maturation, business incubation and business acceleration.

SEMI today announced that SEMICON West 2014 will feature Bob Metcalfe, professor at the University of Texas at Austin, as the Silicon Innovation Forum’s keynote speaker.  The Silicon Innovation Forum (SIF) is where strategic investors and key decision makers are introduced to new and emerging early stage companies looking for support in developing the future of microelectronics. SIF returns to San Francisco at SEMICON West 2014 (July 8-10, Moscone Center).  Coordinated by SEMI, SIF is organized by leading strategic investment groups in the global semiconductor industry including: Applied Ventures, Intel Capital, Micron Ventures, Dow Chemical, TEL Venture Capital, Samsung Venture Investment, and BASF Venture Capital.

Metcalfe, who will keynote at SIF, is a professor of Innovation and Murchison Fellow of Free Enterprise in the Cockrell School of Engineering at the University of Texas at Austin.  Metcalfe was an Internet pioneer at MIT, Harvard, and Stanford, and then he invented Ethernet in 1973 at Xerox Palo Alto Research Center (Parc). He founded the 3Com Corporation in 1979.   More recently, Metcalfe was a general partner of the venture capital firm Polaris Venture Partners near Boston.

As silicon is ubiquitous in our lives, the objective of the SIF ( is to bring together early-stage technology companies and prospective investors from the venture capital and the high-tech industry investment communities, providing a forum for companies to share their technologies and plans with investors to identify new business opportunities. “Innovation and new ideas need investment; traditional venture capital and private funding of advanced semiconductor technology development has significantly declined in recent years, threatening the future of microelectronics innovation and the industry as a whole,” said Denny McGuirk, president and CEO of SEMI.

The Silicon Innovation Forum will be held Tuesday July 8 from 9:15 – 6:00pm in room 134 of the Moscone Center. Following is a snapshot of the program agenda:

“Investor Pitch” Session: Unique semi-private period for SIF exhibitors and investors only; SIF showcase exhibitors will have the opportunity to present directly to a panel of top investors.
General Session: Open to all SEMICON West 2014 attendees. Includes the keynote by Metcalfe on Innovating with Startups; a Strategic Investor Panel; and “Game-Changer Presentations.”
Innovation Showcase and Reception: An exclusive networking session for investors and SIF exhibitors; registration is required for qualified investors and partners for a fee.
Attendees to the Silicon Innovation Forum will include entrepreneurs engaged in silicon innovation, early- to mid-stage growth companies with novel capabilities, investment professionals from the angel, venture, corporate and institutional communities, R&D, purchasing, supply chain managers and manufacturing senior executives from the microelectronics industries.

For information on exhibiting at the Silicon Innovation Forum held at SEMICON West 2014, contact Ray Morgan, SEMI Americas at [email protected] or visit

SEMI ISS: Scaling innovation

February 3, 2014

By Ira Feldman, Feldman Engineering Corp.

Don’t pop the champagne just yet! Although plenty of good news was shared at the 2014 SEMI Industry Strategy Symposium (ISS) there was the sobering outlook of possible limited long-term growth due to technology issues as well as economic projections. Noticeable was the lack of news and updates on key industry developments.

This is the yearly “data rich” or “data overload” (take your pick) conference of semiconductor supply chain executives. The majority of the attendees and presenters are from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. Keeping the pressure on for advanced technology were the “end customer” attendees and presenters – semiconductor manufacturers.

The official theme was “Pervasive Computing – An Enabler for Future Growth” and the presentations made it clear that pervasive computing will greatly increase the demand for semiconductors. However, as discussed in context of very high volume applications such as the Internet of Things and the recent TSensors Summit, such explosive growth will only occur at a sufficiently low price point for these semiconductors and micro-electromechanical systems (MEMS) based sensors.

A major focus of ISS is economics: both the global trends that drive the semiconductor industry and the cost of new technology. Unlike past years, much of the discussion about new technology centered on economics rather than “will it work.” Past discussions about 450mm wafers, extreme ultra-violet (EUV) photolithography, and 3D transistor structures focused on the soundness of these technologies, not the economics.

The question that is being asked of technologists with increasing frequency is: “When will Moore’s Law end?” The cost reduction necessary to keep pace with Moore’s prediction that the minimum cost per transistor will be achieved when the number of transistors on a semiconductor device doubles every two years has primarily been achieved through shrinking the size of the transistors (“scaling”). Many smart people predicted the end of transistor scaling was upon us, hence the demise of Moore’s Law, only to be proven wrong as scaling continued.

Numerous speakers including Jon Casey (IBM) and Mike Mayberry (Intel) stated that scaling will continue below the 10 nm process node perhaps to 5 or 7 nm. However, the question raised by both the speakers and the audience was at what cost will this scaling be achieved. Rick Wallace (KLA-Tencor) reminded us that the demise of the Concorde supersonic plane was the economics and not the technology. In drawing a parallel to the challenge of continued scaling, Mr. Wallace said, “Moore’s Law is more likely to be killed in the board room than in the laboratory.” Therefore, we really need to look to the product managers and executives as well as the technologists for the answer.

The development on 450mm silicon wafers continues via the G450C consortium and Paul Farrar (G450C) provided a progress update. Their current estimates show 450mm ready for production in the range of late 2017 to mid-2020. Meanwhile Bob Johnson (Gartner) showed projected mid-2018 intercepts for Intel and Taiwan Semiconductor Manufacturing Company (TSMC) capability and first true production fabs in 2019-2020. Many of the equipment companies expressed concerns about their return on investment (ROI) for developing 450 mm equipment especially with a limited market. The weakness of demand can be summed up by Manish Bhatia (SanDisk) who said SanDisk/Toshiba didn’t want to build the last 300 mm fab nor were they in the running to build the first 450 mm fab. It appears as though many customers and suppliers share a “wait and see” attitude even though there are still many years of hard work required to launch 450mm.

No formal update on extreme ultra-violet (EUV) photolithography was presented this year although concerns about throughput and cost were mentioned by several speakers. These concerns are part of the fundamental economics of scaling which will require EUV and/or multi-patterning (multiple passes through the photolithography patterning modules for each layer of the semiconductor device instead of the single pass typical of older process nodes) to achieve smaller dimensions. ASML’s last presentation to ISS was in 2012 shortly before they became the “sole” developer of EUV so I hope there will be a public update later this year. For a while, EUV appeared to be a prerequisite for 450 mm development based upon process node intercept but the G450C plan of record (POR) is 193 nm immersion photolithography. G450C will start “investigating” EUV in the second half of 2016. Is this another code for “wait and see”?


Ivo Bolsens (Xilinx) reviewed the challenges and costs in developing next generation application specific integrated circuits (ASICs) and application specific standard product (ASSP). In particular he shared the staggering increase in the cost of the non-recurring engineering (NRE) to develop leading edge semiconductors. (Shown in the chart above.) In less than three years, the estimated NRE cost has jumped from $85 M for a 45 nm design to over $170 M for 28 nm. Included in these NRE estimates are the cost of the design work, masks, embedded software (IP licenses), and yield ramp-up cost. The data presented shows an exponential growth for NRE for each new process node. Rough extrapolation would place 14 nm at $340 M and 7 nm at $680 M respectively. Good news, scaling will continue. Bad news, products may not be able to afford it.

With all this dark and murky news about the future, what was the good news from SEMI ISS? Innovation. The undercurrent of almost every presentation was: since we cannot guarantee that future scaling will provide the savings needed, we need to look at alternative materials, device structures, computation models, system architectures, etc. to continue on the expected cost reduction slope. The list includes a wide range of technology from “More than Moore” (system in packaging, 2.5D, 3D packaging, etc.) to 3D FinFET transistors to carbon nanotubes (CNT) to optoelectronic interconnects, and beyond.

Mr. Wallace in his opening keynote discussed the prerequisites for innovation and shared his concern that some companies have become “too big to innovate”. Even more importantly, if the semiconductor industry wants to remain relevant and attract the best young talent we need to be the “magic behind the gadget.” The Tuesday afternoon sessions closed out with Mark Randall (Adobe Systems) who described his efforts to drive grass-roots innovation by empowering any employee to innovate with no strings attached. Young Sohn (Samsung Electronics) provided his keynote “Innovation in a Connected World” at the banquet describing their work to move from communication devices (smartphones, tablets, etc.) to something that does more to improve lives.

Yes, “innovation” has become an industry buzzword that is often overused. Having seen where these companies say they need to go it is clear many understand it is time to innovate or die. They realize that profitable scaling won’t last forever. Difficult strategic decisions need to be made – marketers and engineers cannot / will not change the direction of their companies by themselves. Enabling innovation and making bold strategic changes requires executive leadership.

Meanwhile, consumers will expect the continuation of Moore’s Law – or at least the end result of continually lowered cost and/or higher performance – without giving a thought to the industry’s inability to continue cost effective scaling or other technical mumbo-jumbo. We still need to continue to make the magic happen!

As always, I look forward to hearing your comments either below or directly. Please don’t hesitate to contact me to discuss your thoughts. For more my thoughts, please see

Ira Feldman ([email protected]) is the Principal Consultant of Feldman Engineering Corp. which guides high technology products and services from concept to commercialization. He follows many “small technologies” from semiconductors to MEMS to nanotechnology engaging on a wide range of projects including product generation, marketing, and business development.

Blog Review October 14 2013

October 14, 2013

At the recent imec International Technology Forum Press Gathering in Leuven, Belgium, imec CEO Luc Van den hove provided an update on blood cell sorting technology that combines semiconductor technology with microfluidics, imaging and high speed data processing to detect tumorous cancer cells. Pete Singer reports.

Pete Singer attended imec’s recent International Technology Forum in Leuven, Belgium. There, An Steegan, senior vice president process technology at imec, said FinFETs will likely become the logic technology of choice for the upcoming generations, with high mobility channels coming into play for the 7 and 5nm generation (2017 and 2019). In DRAM, the MIM capacitor will give way to the SST-MRAM. In NAND flash, 3D SONOS is expected to dominate for several generations; the outlook for RRAM remains cloudy.

At Semicon Europa last week, Paul Farrar, general manager of G450C, provided an update on the consortium’s progress in demonstrating 450mm process capability. He said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers with a 1.5mm edge exclusion zone, they have seen significant progress in wafer quality, and automation and wafer carriers are working.

Phil Garrou reports on developments in 3D integration from Semicon Taiwan. He notes that at the Embedded Technology Forum, Hu of Unimicron looked at panel level embedded technology.

Kathryn Ta of Applied Materials connects how demand for mobile devices is driving materials innovation. She says that about 90 percent of the performance benefits in the smaller (sub 28nm) process nodes come from materials innovation and device architecture. This number is up significantly from the approximate 15 percent contribution in 2000.

Tony Massimini of Semico says the MEMS market is poised for significant growth thanks to major expansion of applications in smart phone and automotive. In 2013, Semico expects a total MEMS market of $16.8 B but by 2017 it will have expanded to $28.5 B, a 70 percent increase in a mere four years time.

Steffen Schulze and Tim Lin of Mentor Graphics look at different options for reducing mask write time. They note that a number of techniques have been developed by EDA suppliers to control mask write time by reducing shot count— from simple techniques to align fragments in the OPC step, to more complex techniques of simplifying the data for individual writing passes in multi-pass writing.

If you want to see SOI in action, look no further than the Samsung Galaxy S4 LTE. Peregrine Semi’s main antenna switch on BSOS substrates from Soitec enables the smartphone to support 14 frequency bands simultaneously, for a three-fold improvement in download times.

Vivek Bakshi notes that a lot of effort goes into enabling EUV sources for EUVL scanners and mask defect metrology tools to ensure they meet the requirements for production level tools. Challenges include modeling of sources, improvement of conversion efficiency, finding ways to increase source brightness, spectral purity filter development and contamination control. These and other issues are among topics that were proposed by a technical working group for the 2013 Source Workshop in Dublin, Ireland.

By Lara Chamness, senior manager, market analysis, SEMI

Given the industry’s anemic performance during the first part of the year, a number of analysts have recently downgraded their 2013 semiconductor revenue forecasts to low-single digits, while forecasting stronger growth in 2014. SEMI believes that the semiconductor materials market will trend with the device market, resulting in an increase of one percent this year and a seven percent increase in 2014, resulting in a materials market approaching $50 billion in 2014.

Looking at materials trends by region, Japan has traditionally been the largest semiconductor materials consuming region owing to its significant fab base and packaging presence. Over the past four years, manufacturers in the region rapidly adopted a fab-lite strategy or have consolidated many of their fabs and packaging plants. During this same time, companies based in Taiwan invested heavily in advanced packaging and foundry operations.

In the 2009 downturn, the materials market contracted 22 percent in Japan, while falling only 12 percent in Taiwan. Immediately out of the downturn, all regional materials markets enjoyed strong gains and by 2011 the Taiwan market surged ahead Japan, resulting in Taiwan becoming the largest semiconductor materials consuming region in terms of revenue. Rest of World, primarily SE Asia, represents the third largest market for semiconductor materials given the dominance of packaging in the region. For this year and the next, Taiwan will strengthen its lead, with Rest of World’s materials market to exceed Japan’s next year (Figure 1) due to continued strength in its packaging materials market.

Figure 1. Semiconductor materials market forecast by region. Source: SEMI Materials Market Data Subscription, August 2013.

Figure 1. Semiconductor materials market forecast by region. Source: SEMI Materials Market Data Subscription, August 2013.

It is interesting to note that in spite of many Japanese device manufacturers opting for a fab-lite strategy and/or consolidating, Japan still represents one of the largest regional markets for fab materials. This should not be surprising considering that fabs located in Japan currently account for about 22 percent of global IC fab capacity, followed by South Korea with 21 percent, Taiwan with 19 percent and North America with 15 percent (Source: SEMI World Fab Forecast database, August 2013). As a result, the wafer fab materials market roughly mirrors IC fab capacity (Figure 2).

Figure 2. 2013F wafer fabrications materials market by region. Source: SEMI Materials Market Data Subscription, August 2013.

Figure 2. 2013F wafer fabrications materials market by region. Source: SEMI Materials Market Data Subscription, August 2013.

Given current growth expectations for the semiconductor market, SEMI is forecasting that semiconductor materials will increase 1 percent this year and 7 percent in 2014. Taiwan now dominates the semiconductor materials market as the result of its aggressive foundry and advanced packaging presence. Japan still represents a significant portion of the global materials market owing to its historical manufacturing strength but it is expected that Rest of World, primarily SE Asia, will surpass the Japan market next year as the Rest of World region grows at a stronger rate due to continued strength in its packaging materials market.

To learn more about semiconductor materials and key market trends, register to attend the SEMI Strategic Materials Conference, which will be held at the Santa Clara Marriott, in Santa Clara, California on October 16-17. For more information about SEMI, visit

by Debra Vogler, SEMI

In advance of the 2013 SEMICON West TechXPOTs on lithography and nonplanar transistors beyond 20nm, SEMI asked some of the speakers and industry experts to comment on the challenges they wanted to highlight. Many of the inputs focused on the need for precision in the processes used to form transistors, as well as how EDA can contribute to mitigating variability.

Likely enhancements on the logic roadmap below 20nm are a move to FinFET, improved FinFET implementation, high mobility channel, and gate all around (GAA) structures, noted Adam Brand, senior director, Transistor Technology Group at Applied Materials. He told SEMI that, “The increased complexity of the FinFET, high mobility channel, and GAA devices in combination with continued scaling requires more precision in structure formation and improved materials to address structure formation and parasitic effects.”

The key steps for maintaining the structural integrity of the fin are precision etch, void-free STI fill, recess, and precisely tailored corner rounding through dummy gate oxidation. Dummy gate oxidation addresses the challenge of ensuring that electric fields can be avoided in the corner explained Brand, who will present at SEMICON West 2013 ( “The dummy gate serves two purposes,” said Brand. “It’s a structural element and it’s there when you do the transistor formation so it can serve roles such as being the etch stop for the gate etch. It’s also able to play a role in shaping the fin.” The fin can be shaped by changing the oxidation rate depending on the amount of oxidation needed for the side vs. for the corner.

Precision again comes into play when forming the gate — precision CMP is required to control the dummy gate and replacement metal gate height. The dummy gate material must also be easily removed. “Advanced CVD materials offer more choices in materials for differentiating selective removal,” said Brand. “Implant-based precision material modification (PMM) has been effective in changing selectivity to obtain better structure control.” He noted that in the past, CMP had not played a role in directly affecting the geometry of the transistor, but now, it is playing a much more direct role in determining the size of the transistor features. For example, in the replacement metal gate step, CMP is used to polish the metals used for the replacement gate structure and it’s also used for the self-aligned contact polish. “So now, you’re polishing the gate at least three times in order to form it, and you need very precise gate height control because it affects the overall stack height and contact height.”

Further complicating transistor scaling is that the 3-D structure adds complexity in strain-related mobility enhancement. “Source/drain stressor shaping is needed to optimize strain and control unwanted increase in the Miller capacitance,” said Brand.  “Lower k dielectrics are also needed to manage the Miller capacitance.” He further explained that when strain is implemented in a FinFET, each source/drain area is a separate fin — as opposed to when strain is being implemented on planar devices. “When you grow the source/drain [in a FinFET], it grows both horizontally and vertically, so when you scale the pitch of the fins, there’s the challenge that eventually those source/drain stressors come very close to each other and they might merge.” The solution, therefore, has to allow the stressors to grow without having them merge between the transistors and still obtain the amount of strain that is wanted. The solution must also address the Miller capacitance. 

The SOI value proposition changes below 20nm

Gary Patton, VP at IBM’s Semiconductor Research and Development Center, told SEMI that in order for the full benefit of the FinFET to be realized below 20nm, a dielectric isolation scheme is necessary to counter the uniformity and variability challenges. “The arrival of the FinFET era has brought about a fundamental paradigm shift in the SOI value proposition such that the advantages of SOI-based innovation now extend well beyond just device performance as in the planar case,” said Patton.  Indeed, Soitec, and others, such as STMicroelectronics, are betting that SOI-based technology will be used as a bridge enabling the industry to get the performance benefits of a fully-depleted transistor while staying with a planar transistor all the way from 28nm down to 14nm, or perhaps even sub-14nm.

To those who question the added cost of going with an SOI-based platform, Patton said that the cost of dealing with the isolation challenge offsets the cost of using SOI substrates. “Offset costs are due to both additional process steps required for bulk, and increases to die area,” said Patton. “An STI isolation module must be added for bulk FinFETs, as well as a series of masking steps and implants for isolation-leakage control and latch-up avoidance. Estimated additional processing costs of bulk isolation offsets the cost advantage of bulk substrates over SOI.” He also pointed out that die area increases are driven by the need for well contacts, and I/O guard-rings (latch-up avoidance). “We also anticipate the overall die yield to be challenging for the bulk FinFET process due to variability and the need for matching performance of critical circuit paths in a chip.”

Another consideration for proponents of SOI-based technology is the issue of process variability. “A buried oxide layer (BOX) in SOI fins is responsible for three areas of improvement in variability over bulk-isolated FinFETs,” Patton told SEMI. “First, the top silicon layer is terminated by the buried oxide, is proven to be extremely uniform in thickness, and defines the height of the fin both physically and electrically, since any fin over etch does not contribute to the fin height.” He further explained that the source and drain are completely separated by the gated channel, unlike in a bulk FinFET, where there is a continuous path for leakage, requiring a highly doped punch-through stop.

“The non-abrupt nature of doping introduces a non-uniform doping profile, and hence, turn-on current, between the top and bottom of the fin, further eroding the FinFET advantage.” Patton noted that a more practical consideration is the slope or taper of the fin itself. “From an electrical point of view, the ideal fin would be perfectly vertical and of uniform thickness from top to bottom. In a bulk fin process, a degree of taper must allow for the subsequent oxide fill and etch-back, and also to accommodate a reduced spacer over-etch budget (vs. an SOI fin). The fin taper introduces further non-uniformity to the FinFET, which reduces switching speed.”

EDA tackles variability

Reducing/mitigating process variability is ever more critical to yield as the industry scales transistors below 20nm, and much can be done in the design arena to help. For example, EDA considerations can mitigate “noise” in the optical system [lithography] that is a source of variability.

Mike Rieger, group director, R&D, Silicon Engineering Group at Synopsys, uses communication theory to analyze certain aspects of a lithographic system. He told SEMI that when there are optical systems [lithography] without tuning, i.e., a “plain vanilla” system — all the spatial frequencies in the visible limit are present. Conversely, when the design is friendly to specific spatial frequencies and you then try to print that design with an optical system that is friendly to all spatial frequencies, there are other frequencies that leak through. This “leakage” causes a lowering of the contrast in the optical image. “With the lower contrast, the image is more susceptible to other sources of variation like defocused variation, or dose variation, and that translates into your printed features having more variation in their dimensions,” said Rieger, another speaker at the upcoming SEMICON West (

Rieger added that, if you can prevent the unwanted frequencies from even being passed through the optical system, the net result is that the contrast is improved. Additionally, by tuning these frequencies, the diffraction orders in the stepper (the rays of light used to form the image) are manipulated. “You can eliminate the zero order ray. This zero order ray reduces contrast and it also limits the maximum frequency that you can image.” The tuning process – also known as source mask optimization (SMO) – really isn’t the end game, noted Rieger. “It’s source design optimization that is the end game. You tune the configuration of your design to be consistent with the optimization of the source.”

Regarding the parallel paths the industry is taking – extending optical lithography while developing EUVL — Rieger is realistic in his assessment of what EDA can bring to the table. “We’re going to be using 193i for the foreseeable future — it will be years before 193i is replaced,” said Rieger. But, “Optical lithography on a single exposure is maxed out in terms of the density it can print, so if you want to get more transistors per chip or more details per chip, you must do a couple of things.” Those are: tuning the optics, which comes at a cost, and using multiple exposures. “To get an effective result, the whole process of the tuned optics and the multiple exposures must be comprehended in the physical layout software, and some of the things that need to be done go beyond what you can accomplish with the traditional rule-based constraint that you put on the layout.”

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In a significant announcement during the SEMICON Japan 450mm Transition Forum that sheds new light on the availability of 450mm wafer processing lithography capability, Kazuo Ushida, president of Nikon Precision Equipment Company, said that the company plans to ship high-volume manufacturing (HVM) lithography tools in 2017 through a joint development effort with a chip maker.  Nikon plans to have ArF immersion 450mm prototype tools in 2015-16.

Other 450mm-related news during SEMICON Japan came from Opening Keynote speaker Kasumasa Yoshida, representative director and president of Intel, K.K., who confirmed Intel’s new 450mm Japan Metrology Center (JMC) in Tsukuba. 

Ushida said that requirements for 450mm lithography include higher throughput, improved overlay accuracy, and improved imaging performance. The industry’s expectation for high-volume 450mm EUV lithography insertion in 2018 will likely be delayed due to insufficient light source progress, mask infrastructure and EUV photoresist development challenges.  Furthermore, Uchida said that the very steep curve of EUV technology improvement required is not realistic in the timeframe.

Lithography has been a serious concern among other wafer process equipment tool providers, who have been reluctant to invest in 450mm research and development ahead of a viable advanced node patterning solution.  Other equipment companies have been interested in a 450mm litho solution for process development reasons and also as an assurance that chip makers will actually be ready to implement a complete manufacturing line in the timeframe that tool development is being requested.

Uchida’s pledge aligns with the G450C roadmap. G450C vice president and general manager Frank Robertson, also speaking at SEMICON Japan, said that the consortium plans for nano-imprint litho and pitch doubling capability over the next two years and “real” 193 immersion litho capability for tool demonstrations at the unit process level by mid-2014. 

Robertson said that G450C has now negotiated a full set of wafer process and metrology tools with the exception of lithography. In addition to 14nm tool demonstrations, G450C is focused on providing test wafers. Test monitor 450mm wafers are expected to be available in 2Q13, prime wafers in 2Q14 and epi wafers in 1Q15. G450C is giving priority to consortium members and the participating tool makers. They will also provide 450 test wafers to others via a wafer loan program.  Robertson pointed to a wafer loan request process on the G450C website.

According to economic analysis from Akira Minamikawa, vice president, IHS iSuppli Japan, NAND memory and microprocessors warrant the larger wafer size, but DRAM will not require 450mm manufacturing.  Minamikawa estimates that twenty 450mm fab lines (to as many as 50 “at the most”) will be built in a ten-year period.  He contrasts that figure to 160 fab lines for 300mm and 240 8” fab lines that were built in a similar timeframe.

The need for innovation and collaboration to achieve the cost and time objectives was a common observation from G450C, Nikon and TEL representatives speaking at the Forum.  Each speaker pointed to the important role of SEMI Standards in achieving a successful transition and the need for chip makers, consortia and equipment companies to collaborate in new ways.

Tokyo Electron Limited (TEL) VP and general manager Akihisa Sekiguchi commented that equipment makers face inordinate challenges in the 450mm transition. Concurrent 300mm/450mm R&D and prolonged 450mm startup impose significant financial risk and he warned that it may take years for equipment makers to see an ROI. TEL’s proposal is to unify its various internal platforms for 450mm, and establish an open platform alliance to share previously proprietary information with the supply chain.  Concepts for harmonizing facility connections have been well-received by the G450C as a means to reduced installation costs and complexity.

Intel’s new 450mm Japan Metrology Center (JMC) in Tsukuba was referenced in an earlier industry presentation at SEMICON West and operational since July, but has not been publically announced.  Yoshida said that mission of the new facility is to support the 450mm network by providing “quick turn” metrology, improved supplier R&D velocity and a link to the G450C activity in Albany, New York.

Yoshida said that the semiconductor industry is spurred by silicon innovation and penetration.  He referenced smartphone demand, which is expected to grow at a 24 percent compound annual growth rate over the next several years, and tablets with a 53 percent CAGR, as key market drivers.  He further commented that 15 billion intelligent connected devices will be present by 2015 and contribute to an estimated 35 trillion GB of data traffic. He said that the combined market drivers potentially yield semiconductor industry sales with greater than 50 percent upside by 2020 — meaning a worldwide market of about $450 billion. He anticipates that Intel products will represent a 25-26 percent share of the total and therefore the company requires aggressive investment to increase capacity.

The next SEMI 450mm Transition Forum will occur at SEMICON Korea on January 30, 2013.

by Paula Doe, SEMI Emerging Markets

Materials experts from across the supply chain who gathered at the Strategic Materials Conference 2012 in San Jose in October discussed key materials needs for micromanufacturing outside the CMOS mainstream, as OLEDs and GaN-on-silicon power semiconductors come to market, and alternatives like graphene, CNTs, and self-assembling polymers get closer to commercial application.

Large OLED displays are coming, and counting on materials breakthroughs

OLED adoption in larger displays is surely coming, driven by business necessity, argued James Dietz of Plextronics. Most of the major display makers are seeing operating losses from their LCD business, and OLEDs look like the best option for higher-value, differentiated products to improve margins. The OLED displays look significantly better, and they may potentially open new markets for lighter or flexible or more rugged displays, or for dual-view products. OLEDs’ ultra-fast switching speeds could allow different viewers with different glasses to watch different programs at the same time on the same screen. Moreover, though OLEDs are more expensive now, the variable costs for a 55-in. OLED TV made on an 8G line will be quite comparable to those for a similar LCD. And the OLED costs have far more potential to come down further, by developments like simplifying the layer stack and introducing wet processes that use lower cost equipment with higher utilization of the expensive materials.

But the nature of the market also means new challenges for suppliers. Anxious to avoid another experience like the commoditization of the LCD sector, display makers intend to keep their processes and complex OLEDs materials stacks to themselves this time, which makes process integration of different materials and equipment difficult. The device makers are investing in developing their own materials, making exclusive contracts with equipment and materials suppliers, and doing their own process integration. Integration is also being driven by some materials suppliers like DuPont Displays. But the familiar semiconductor model of the material and tool supplier working together to deliver a process to the customer is not the rule. "We see a gradual transition from all vapor to more solution layers," says Dietz. "OLEDs will enter the TV market in the next three years, and will have solution process steps by 2015."

The 55-in. OLED TVs announced for 2012 now look more likely to come out in only very small volume — a few thousand units in 2012 — and initial prices of ~$9000 will limit sales. But OLED TVs will start to see real growth by 2014-2015, helping to push OLED displays to a $25 billion market by 2017, reports Jennifer Colegrove, VP of emerging display technology at NPD DisplaySearch. She says ten new AMOLED fabs are planned to be built or updated in the next three years. OLED materials, now about a ~$350 million market (include the OLED organic materials but not substrates), should grow at close to the same 40% CAGR of the overall market, to reach $1-2 billion in 2014. But breakthroughs are still needed in oxide and amorphous silicon backplanes, color patterning technology, lifetime of blue materials, encapsulation materials, reduction of materials usage, and of course integration, uniformity and yields of all these things.

OLED display revenues will grow to about $35B in 2019, up from $4B in 2011, with CAGR ~40%. (Source: NPD DisplaySearch, Q3’12 Quarterly OLED Shipment and Forecast Report)

Solution processing is critically important to bringing down the cost of large screen OLEDs, argued John Richard, president, DuPont Displays, as the current production methods which rely on thermal evaporation with fine metal masks are proving costly to scale to 8G substrates. "We developed an alternative process using soluable materials to bring down cost," he notes. Wet processes reduce capital needs and cut material waste to reduce costs significantly, but still need ever better lifetimes and efficiencies of the OLED materials, particularly for blue. A major Asian display maker has licensed the DuPont technology, and plans to scale it up to 8G. The process uses largely pre-existing tools to slot coat the hole injection and transport layers, and pattern the surface with wetting and non-wetting lanes, before nozzle printing stripes of red, green and blue emitters using custom tool developed with Dai Nippon Screen.

The rest of the stack — the electron transfer layer, the electron injection layer, and the metal cathode — is then deposited by thermal evaporation. Richard says coating and printing processes can use significantly less material than vapor deposition, as it avoids losses in the chamber, on the mask, and during alignment and idling. DuPont reports printed blue emitter lifetime is up to 30,000 hours — or 8 hours a day of video for 15 years — before degrading to half brightness. Next issues include optimizing the cost of synthesis and starting materials, and reducing operating voltage for better device efficiency.

Graphene and carbon nanotubes get closer to commercial applications

Next-generation energy storage presents materials opportunities as well. One key enabler for improving both supercapacitors and batteries could be graphene, especially with better sources for consistent quality material at reasonable cost. Bor Jang, CEO of Angstron Materials, reported that his company has engaged a contract manufacturer in Asia to start volume production of as much as 30 tons of graphene next year, using Angstron’s technology that claims good control of structure and properties. "That will bring down costs by an order of magnitude," says Jang. First application will likely be performance enhancers for lithium-ion battery electrode materials, and then for improved electrodes for supercapacitors. Angstron has announced demonstration of a graphene-based supercapacitor with energy density comparable to a nickel hydride battery.

"We think supercapacitors is a market to invest in," said Chris Erickson, general partner at Pangaea Ventures, a somewhat unusual venture fund that invests particularly in materials and green technologies. "We think it will reach $1 billion in the near future." Erickson is also enthusiastic about the potential for dynamic window glazing using vapor-deposited coatings and ITO to adjust to control the shading on windows, for dramatic energy savings of up to 30% in energy consumption in a building, according to NREL — and buildings reportedly use 49% of total energy in the US.

Nantero reported major progress from its long effort in controlled processing and performance for its carbon nanotube thin film, targeting low-cost, low-power non-volatile memory. CTO and co-founder Thomas Reuckes said the company is now lithographically patterning films of its spin-coated aqueous solution of carbon nanotubes, as roughness, adhesion and defectivity are now suitable for semiconductor processing. Metal impurities are down to <1ppb in liquid form, wafer-level trace metals to <1E11 atoms/cm2 . Reuckes reported production of working and yielding 4Mbit CNT memory arrays, and showed results of reliability data. The company just announced a joint development program with imec to manufacture, test, and characterize the CNT memory arrays in imec’s facilities for applications in next generation <20nm memories.

GaN for power semiconductors needs higher purities than LED market

Power semiconductors made on GaN on silicon are being released to the market now, and, given time, could potentially address some 90% of the what IMS Research projects will be a $25 billion (silicon-based) power semiconductor market for MOSFET and IBGTs by 2016, suggested Tim McDonald, VP for emerging technologies at International Rectifier Corp. GaN theoretically offers much better specific on-resistance to breakdown voltage tradeoff than Si or SiC. The key to wide adoption is for GaN on Si based solutions to achieve 2-4× performance/cost compared to silicon.

To achieve the necessary low costs, IR uses compositionally graded layers of AlyGaxN grown on the silicon to ease the thermal and lattice mismatch of the GaN film to the silicon wafer. IR claims 80% yields, with warp and bow controlled enough to run on a standard 150mm CMOS line. GaN on silicon is moving more quickly to market for power semiconductors than for LEDs, as it brings better performance, not just potentially lower prices. It also helps that threading defects do not have the same impact on performance–plus IR has been developing the technology for six or seven years already.

The power market needs higher purity materials and cleaner tools for better yields on its larger die, compared to the LED market. It also prefers larger diameter wafers for lower costs. Demand for gas sources and MOCVD tools should scale with volume, and the tools need to be optimized for larger wafers and become more automated, with perhaps some 2,000-3,000 tools needed for the whole market over the next two decades. Packaging may move from wire bonding to soldered or sintered contacts, and will adopt other means of reducing stray packaging-related inductance and resistance.

The LED market will see only a few more years of significant growth, argued Jamie Fox, lighting and LEDs manager for IMS Research-IHS. Revenues from displays including TVs are leveling off from their fast ramp, as the markets mature, and as LEDs get both brighter and cheaper, driving down both units needed and cost per unit. The LED lighting market will continue its fast climb to near ~$6 billion over the next several years, but then as more lamp sockets are replaced by the longer lasting LEDs (and CFLs), there will be less need for replacements, and the market will slow. Slower adoption near term, however, would mean less saturation later.

Cree’s Mike Watson, senior director of marketing and product applications, countered by pointing out the potential for innovation that solid state technology brings to lighting, noting how digital technology has transformed markets like telephones and cameras into new industries for digital communications and digital imaging. "Semiconductor technology keeps changing industries by innovation," he noted. "Why do we keep thinking of it as just replacement?

Directed self-assembly for higher resolution lines and holes

Another of the more innovative materials alternatives on the CMOS side is directed self-assembly for next-generation patterning, which seems to be making rapid progress. AZ Electronic Materials CTO Ralph Dammel reported that block copolymers, with similar molecules together in blocks instead of randomly dispersed, tended to arrange themselves with the similar chain sections together, conveniently lining up into cylinders that look similar to lithographic contact holes, or into lines similar to lithographic lines and spaces. Wafer surface patterning with topography or chemicals can control the placement of these self-assembled patterns, on top of standard 193nm immersion lithography. Work with IBM Almaden suggests the process can provide better CD uniformity for quadruple patterning at lower cost than the spacer pitch division process. Other work shrinks contact holes, while improving the CD variation compared to the resist prepatterns. The company is now providing large-scale samples for in-fab process learning, with implementation perhaps as early as 2014, though design for self-assembly needs further development work.