Category Archives: LEDs

Dec. 17, 2003 — Quantum Dot Corp. has launched two additions to its line of nanocrystal-based fluorescent labels, according to a news release.

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The Qtracker 655 Kit is the first in a new line of labeling reagents designed for introducing nanocrystal-based fluorochromes into live cells. The kit is designed for long-term studies of cells, and can be observed in cells for a week or more. The Qdot 705 Streptavidin Conjugate is for ultrabright, near infrared biodetection, and can penetrate deeply into tissues, gels and animals for biomedical analysis.

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Quantum dots — nanoscale bits of semiconductor material — glow in distinctive colors depending on their size. They have many potential uses, from lasers to solar cells. The Hayward, Calif.-based firm is concentrating on biological detection.

DEC. 16–SAN JOSE, Calif– Attorneys for IBM Corp. are trying to block testimony about chemical exposure levels in cleanroom models simulating the company’s former disk drive manufacturing plant here.

Plaintiffs hope to demonstrate the levels of chemical exposure at the plant were high enough to have caused cancer in two former IBM workers.

Robert Morris, an expert in cleanroom ventilation began a second week of testimony on Dec. 15 on model cleanrooms he helped create to simulate working conditions at the plants in and around the 1970s. Morris is president and chief executive of Flow Safe Inc., a Denville, N.J.-based manufacturer of airflow control systems.

During cross-examinations, lawyers from both sides battled over details about the size, layout and ventilation schemes of the cleanroom models.

Morris says the design of the computer company’s cleanrooms did not guarantee a fresh air supply.

Plaintiffs Alida Hernandez and James Moore allege IBM withheld information about their medical conditions due to chemical exposure while working at the plant and that the exposure led to later cancers.

Cree stakes new GaN claim


December 15, 2003

December 15, 2003 – Cree Inc., Durham, NC, says it has developed new gallium nitride power transistors with much higher power densities than previously achieved.

The GaN HEMTs produce CW power density of 32 W/mm with 55% power-added efficiency at 4GHz, and 30W/mm with 50% efficiency at 8GH, almost triple the power and five points higher than current transistors. The new design was developed as part of a program with DARPA.

Fabless startup wins business


December 15, 2003

December 15, 2003 – Kenet Inc., Reading, MA, a fabless semiconductor company for mixed-signal devices, has won a contract with the Defense Advanced Research Projects Agency (DARPA).

Under the deal, Kenet will work on “monolithic integration,” or putting all functionality onto a single chip, for use in applications such as radar and wireless communications.

The company, led by John Fan (chairman), Gerry Sollner (president, CEO), and Michael Anthony (CTO), was formed in April 2002 based on technology developed in MIT’s Lincoln Laboratory.

Isonics gains wafer patent


December 12, 2003

December 12, 2003 – Isonics Corp., Golden, CO, has been awarded a US patent for its method of lowering the temperature of semiconductor devices built onto the wafer surface.

The patent, “Semiconductor wafers with integrated heat spreading layer,” involves covering wafers with a layer of high-thermal conductivity, isotopically-pure materials including silicon, germanium, SiGe alloys (including strained silicon), GaAs, AlGaAs, GaN, InP, or any combination thereof.

The technology is aimed at creating wafer structures enabling higher power output for devices such as lasers and LEDs.

December 1, 2003 – Worldwide semiconductor sales continued to rebound in October, posting the eighth consecutive monthly increase and largest month-to-month gains since 1990, according to data from the Semiconductor Industry Association (SIA).

Worldwide semiconductor sales rose to $15.43 billion in October, a 6.8% increase from the $14.45 billion in September and 23.3% higher than October 2002. While October is typically a strong month, “this exceeds historical norms,” stated SIA president George Scalise. “This growth cycle is dynamic and broad-based, drawing strength from all geographic markets, all product sectors, and all end-markets.” So far in 2003, chip sales have grown 16.4% from last year, and SIA reaffirmed projections of double-digit growth in 2003 and 2004.

Leading the growth were DRAMs and microprocessors, which were up 8.0% and 6.6%, respectively. Wireless technologies also showed robust growth — flash grew 12.7% and digital signal processors grew 9.3% in October — thanks in part to renewed momentum in China, where 5 million new cell phone subscribers are added per month. Seasonal demand for electronics devices helped boost optoelectronics (up 5.2%) and standard cells (up 6.3%). Scalise also noted a revised US GDP growth of 8.2%, driven by strong consumer spending and an upwardly revised 18.4% increase in business spending on computers and software.

Geographically, all markets reported month-to-month growth slightly higher than in September, led by Europe and the Americas. All geographic markets also expanded their year-on-year growth, led by the Asia-Pacific region (31.0%), Japan (24.8%), and Europe (20.8%), with the Americas also posting a double-digit gain. For the moving three-month average, all markets showed better double-digit growth than in the September period: Americas 15.0%, Europe 19.7%, Japan 12.4%, and Asia-Pacific 22.9%.

LSI to sell storage business


December 4, 2003

November 17, 2003 – LSI Logic, Milpitas, CA, plans to spin its storage systems business into an independent storage systems company, separate from its semiconductor business. The new company, based upon LSI’s wholly-owned subsidiary, LSI Logic Storage Systems Inc., will be led by current president Tom Georgens, with customers including IBM, StorageTek, NCR’s Teradata division, and SGI. An IPO is tentatively planned for 1H04 for the new company, which in 3Q03 reported revenues of $104 million.

AMD unveils chip plant plans


December 4, 2003

November 21, 2003 – It’s official: AMD’s new 300mm fab will be built in Dresden, Germany, next to its existing Fab 30 facility. The $2.4 billion Fab 36, the first new chipmaking facility in Europe in years, is scheduled to begin volume production in 2006.

The deal, which would generate as many as 1400 jobs in the region, reportedly includes up to $1.5 million in government-backed funding, including $500 million in grants and loans from the regional Saxony and German governments, $700 million in bank loans and government-guaranteed credit, and $320 million in equity funding from Saxony and a group of European investors led by M+W Zander.

“The time is right to expand our manufacturing capacity in order to effectively meet future demand,” said AMD president and CEO Hector Ruiz, citing increased customer demand and expanding opportunities for AMD’s 64-bit processors, including a recent deal with Sun Microsystems.

On Nov. 4, Intel Corp. announced that Intel Fellow Robert Chau would present results of the company’s high-k/metal gate transistor development at the International Gate Insulator Workshop in Tokyo, Japan, on Nov. 6. The new high-k gate materials are needed to reduce current leakage as device dimensions shrink and transistor gate dielectrics become thinner. Two days after the announcement, Intel updated its data with better results for NMOS high-k /metal gate transistors.

For five years, Chau has led a dedicated team that worked on solving the problems inherent in the search for new gate dielectric materials and integrating them with metal gate electrodes.

According to Ken David, director of components research at Intel, the most significant advancement that eliminated of voltage pinning and phonon scattering was selecting the correct materials for the gate electrodes. Intel had an internal model of what caused these problems; when the correct materials were selected, the problems disappeared.

In his workshop presentation, Chau presented experimental evidence of phonon scattering in high-k materials and cited the possibility that metal gate electrodes may be able to screen the high-k SO phonons from coupling to the inversion channel charge carriers and reduce the mobility degradation problem.

The metals — which remain confidential — must have work functions that match the properties of the polysilicon material they are replacing. The metals will be used in combination with the new high-k gate dielectrics for both PMOS and NMOS transistors.

On Nov. 4, the company presented a transistor curve taken from an 80nm NMOS transistor built with the new process and materials that had an I[on]=1.5mA/micron and an I[off]=43nanoamps/micron, at a drain voltage=1.3V. On Nov. 5, the company released updated performance data for its high-k metal gate NMOS transistor: a drive current of 1.66mA/micron, I[off]=37nA/micron (Vcc=1.3V).

David declined to identify the high-k material that was selected, and also did not identify the supplier of the ALD equipment expected to be used in production. He did say there were no special manufacturing challenges to overcome in order to use ALD to make the new transistor. The company does not currently use ALD in its manufacturing processes, but the process technology also is being evaluated for other steps in the company’s manufacturing flow.

Because Intel has what David described as a fairly large materials group that works closely with R&D to ensure that selected materials will be available when needed, he foresees no problems with availability. David also characterized any changes to the manufacturing process as “cost neutral” — essentially changing out one type of tool for an ALD system. He added that some process steps would be going away (e.g., growing oxides, polysilicon deposition).

According to Intel’s roadmap, the new transistors are expected to be in production by 2007 at the 45nm technology node — when it expects to use 193nm/high-NA lithography. David noted that by 2007, Intel anticipates its microprocessors will contain around 1 billion transistors. A Pentium 4 microprocessor has 55 million transistors. — Debra Vogler, Senior Technical Editor

Dec. 2, 2003 — A team led by DuPont scientists have discovered a way to sort and assemble carbon nanotubes that could overcome an obstacle to developing highly sensitive medical diagnostics devices, miniature transistors and other nanoelectronic devices, according to a news release.

Nanotubes of different electronic types randomly clump together when they are fabricated, making it difficult to produce them with consistent conductivity. The researchers say the new sorting method uses single-stranded DNA and a type of chromatography to separate metallic and semiconducting nanotubes, allowing for uniform conductivity.

The team, whose work appears in the current issue of the journal Science, included scientists from DuPont Central Research & Development, the University of Illinois and Massachusetts Institute of Technology.