Category Archives: Semicon West

By Pete Singer, Editor-in-Chief

A new roadmap, the Heterogeneous Integration Technology Roadmap for Semiconductors (HITRS), aims to integrate fast optical communication made possible with photonic devices with the digital crunching capabilities of CMOS.

The roadmap, announced publicly for the first time at The ConFab in June, is sponsored by IEEE Components, Packaging and Manufacturing Technology Society (CPMT), SEMI and the IEEE Electron Devices Society (EDS).

Speaking at The ConFab, Bill Bottoms, chairman and CEO of 3MT Solutions, said there were four significant issues driving change in the electronics industry that in turn drove the need for the new HITRS roadmap: 1) The approaching end of Moore’s Law scaling of CMOS, 2) Migration of data, logic and applications to the Cloud, 3) The rise of the internet of things, and 4) Consumerization of data and data access.

“CMOS scaling is reaching the end of its economic viability and, for several applications, it has already arrived. At the same time, we have migration of data, logic and applications to the cloud. That’s placing enormous pressures on the capacity of the network that can’t be met with what we’re doing today, and we have the rise of the Internet of Things,” he said. The consumerization of data and data access is something that people haven’t focused on at all, he said. “If we are not successful in doing that, the rate of growth and economic viability of our industry is going to be threatened,” Bottoms said.

These four driving forces present requirements that cannot be satisfied through scaling CMOS. “We have to have lower power, lower latency, lower cost with higher performance every time we bring out a new product or it won’t be successful,” Bottoms said. “How do we do that? The only vector that’s available to us today is to bring all of the electronics much closer together and then the distance between those system nodes has to be connected with photonics so that it operates at the speed of light and doesn’t consume much power. The only way to do this is to use heterogeneous integration and to incorporate 3D complex System-in-Package (SiP) architectures.

The HITRS is focused on exactly that, including integrating single-chip and multi­chip packaging (including substrates); integrated photonics, integrated power devices, MEMS, RF and analog mixed signal, and plasmonics. “Plasmonics have the ability to confine photonic energy to a space much smaller than wavelength,” Bottoms said. More information on the HITRS can be found at:

Bottoms said much of the technology exists today at the component level, but the challenge lies in integration. He noted today’s capabilities (Figure 1) include Interconnection (flip-chip and wire bond), antenna, molding, SMT (passives, components, connectors), passives/integrated passive devices, wafer pumping/WLP, photonics layer, embedded technology, die/package stacking and mechanical assembly (laser welding, flex bending).

Building blocks for integrated photonics.

Building blocks for integrated photonics.

“We have a large number of components, all of which have been built, proven, characterized and in no case have we yet integrated them all. We’ve integrated more and more of them, and we expect to accelerate that in the next few years,” he said.

He also said that all the components exist to make very complex photonic integrated circuits, including beam splitters, microbumps, photodetectors, optical modulators, optical buses, laser sources, active wavelength locking devices, ring modulators, waveguides, WDM (wavelength division multiplexers) filters and fiber couplers. “They all exist, they all can be built with processes that are available to us in the CMOS fab, but in no place have they been integrated into a single device. Getting that done in an effective way is one of the objectives of the HITRS roadmap,” Bottoms explained.

He also pointed to the potential of new device types (Figure 2) that are coming (or already here), including carbon nanotube memory, MEMS photonic switches, spin torque devices, plasmons in CNT waveguides, GaAs nanowire lasers (grown on silicon with waveguides embedded), and plasmonic emission sources (that employ quantum dots and plasmons).

New device types are coming.

New device types are coming.

The HITRS committee will meet for a workshop at SEMICON West in July.

We hope you had a productive and enjoyable time at SEMICON West.  Despite the lackluster marketplace, this year’s SEMICON West achieved a 15 percent increase in unique visitors and over an 18 percent increase in R&D titles.  We were also happy to see such strong attendance at the keynotes, executive panels and TechXPOT stages, confirming our claim that SEMICON West delivers the most well-informed and influential speakers (and audience) in the industry.

Read more news from SEMICON West 2013

One of the strongest programs at SEMICON West 2013 was the materials program produced by the Chemical & Gases Manufacturer Group (CGMG), a SEMI special interest group.  This session, entitled, “Materials Growth Opportunities at Both Ends of the Spectrum” attracted over 450 people, more than any dedicated materials session we’ve ever had at SEMICON West.  And it’s no surprise. Innovations in materials are driving leading-edge semiconductor development.  Material markets are growing as the result of opportunities for both large geometry devices such as wide bandgap and printed electronics, and nano-scale devices at sub 22nm and beyond.

As much as materials took center stage at SEMICON West, the subject is simply too big and dynamic to cover in-depth at SEMICON West.  For the real “deep dive” into the critical trends and opportunities in advanced electronic materials, you must attend the SEMI Strategic Materials Conference (SMC), held October 16-17 at the Santa Clara Marriott in Silicon Valley, California.  SMC is the only executive conference in the world dedicated to advanced electronic materials.

SMC provides valuable forecasting information and serves as a forum for collaboration among all sectors of the advanced materials supply chain. This year’s program will feature powerhouse keynote speakers including:

 Luc Van den hove, president and CEO, imec

Gregg Bartlett, chief technology officer, GLOBALFOUNDRIES

Laurie E. Locascio, Ph.D., director, Material Measurement Laboratory, National Institute of Standards and Technology, and co-chair of the US government’s ambitious and essential Materials Genome Initiative

Other top-tier speakers will address market forecasts, materials developments in memory and logic, packaging materials trends, and materials-enabled “Beyond CMOS” devices.  Speakers will also address emerging materials opportunities and challenges in printed electronics, wide bandgap power devices, and MEMS.   The conference will also explore regulatory threats to the microelectronics industry and directly confront the increasingly difficult collaboration challenges between manufacturers, process equipment companies and diverse materials suppliers.

Last year’s conference sold out and attendees are encouraged to register early to ensure participation.

For additional information, please visit,

Thank you for making SEMICON West such a great success and hope to see you at the Strategic Materials Conference, if not before.

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about an ASML presentation from Semicon West. This is a follow up to a previous post: "Dimensional Scaling and the SRAM Bit-Cell."

I just downloaded the ASML presentation from Semicon West2013 site – ASML’s NXE Platform Performance and Volume Introduction. Slide #5  – IC manufacture’s road maps – says it all.

Embedded SRAM will scale from 0.09µm² at 22-20nm node to 0.06µm² at 11-10nm node. In other words only 30% reduction instead of the 4x reduction expected of historical dimension scaling, to roughly 0.02µm² !!!

In our previous blog that followed ISSCC 2013 we saw some early indication of this slowdown.  Yet we were still surprised to realize how bad it really is. This might explain why after resisting IBM and other pushes for embedded DRAM, Intel announced few month ago that its Haswell processor will incorporate embedded DRAM after all.

Another point from this ASML slide is the adaption of monolithic 3D by the NAND Flash vendors. We believe this is a start of a trend, and that logic vendors has now one more reason to follow it.

Part 1 of this blog covered International Technology Roadmap for Semiconductors (ITRS) updates to System Drivers, Design, Modeling and Process Simulation, Process-Integration Device and Structures (PIDS), and Front-End Processing, as presented in a session on the last day of SEMICON/West 2013.

SEMATECH’s Mark Neisser provided a sobering overview of the challenges associated with extending Lithography technology to pattern device structures below a half-pitch of 20nm. The ITRS Lithography International Technology Working Group (ITWG) works with pitch and half-pitch ranges as lithographically determined and so do not have an exact correspondence to “nodes.” ArF light sources at 193nm wavelength have been extended as far as possible using immersion, and all so-called “next-generation lithography” (NGL) technologies have problems, such that it’s unsure if any will be ready at the decision points needed insertion into future chip-making lines. Today, we can look at anticipated  half-pitch ranges needed for proposed device structures and determine which proven technologies could be used:

  • 30-20nm half-pitch is the limit of ArF Double-Patterning,
  • 19-15nm half-pitch is estimated as the limit of EUV Single-Patterning,
  • 14-11nm half-pitch is estimated as the limit of ArF Quadruple-Patterning, and
  • 10-8nm half-pitch corresponds to the estimated limit of EUV Double-Patterning at the current NA.

“The industry needs an alternative to Quadruple-Patterning,” opined Neisser, “and the price-per-bit won’t necessarily go down.”

Front End Processes (FEP) needed for future chip-making were reviewed by Joel Barnett of Tokyo Electron. The FEP team is in flux, and Barnett solicited new team members. “Really what’s driving FEP these days is new materials for both logic and memory,” explained Barnett. New materials raise unpredictable integration challenges, for deposition, etch, cleaning, and metrology. We need to know the correlation between electrical properties and materials structures, and how can interfaces be engineered. Continued scaling of High-Performance finFET logic devices is challenging in all aspects:  EOT, junctions, mobility enhancement, new channel materials, parasitic series resistance, and contact silicidation. Fin pitch has now been set by consensus with the PIDS and Lithography ITWGs to be 0.75 of M1 pitch.

Emerging Research Devices (ERD) that could replace standard CMOS FETs were discussed by An Chen of GLOBALFOUNDRIES with an emphasis upon novel memory technologies. One surprise was the removal of “nano-mechanical memory” from tracking in the main ERD table due to lack of progress. Resistive-RAM (RRAM) is now anticipated to move into commercial manufacturing in 2018, and the ERD ITWG plans to start tracking 4 different RRAM technologies in a new table: conductive-bridge RAM (CBRAM), metal-oxide bipolar filament, metal-oxide unipoloar filament, and metal-oxide bipolar interface effect. Unlike conventional Flash many emerging memory devices need a “select device,” and while transistors provide the best performance 2-terminal devices are more easily scaled. On the logic side, ERD anticipates new devices with “learning capabilities” to be developed in the long-term such as neuromorphic chips.

Emerging Research Materials (ERM) that could be needed to integrate new functionalities into integrated circuits were shown by C. Michael Garner, now with Stanford and Garner Nanotechnology Solutions. Alternate-channel materials such as Ge and III-V compounds seem destined to be used in future CMOS, and the best results to date combine Ge pMOS with III-V nMOS. However, integration cost and complexity would be reduced if only one new material could be coaxed into use as the alternate-channel, and so there is continuing work on Ge nMOS and III-V pMOS transistors. Contacts are important for all new materials, so the engineering of atomic-interfaces will be critical for future devices.

“A few people have demonstrated that providing a very thin barrier counter-intuitively lowers contact resistance,” shared Garner.

Click here for more news from SEMICON West 2013.

In the afternoon of the last day of SEMICON/West 2013, a session was devoted to updates from the International Technology Roadmap for Semiconductors (ITRS) Front End of Line Technologies. Representatives from the different International Technology Working Groups (ITWG) provided highlights from the work now happening on the 2013 update.

Andrew Kahng of U.C. San Diego provided two presentations on challenges associated with future ICs:  System Drivers and the Design. Systems today are clearly driven by System-on-Chip (SoC) and mobile. The size of a typical mobile phone SoC is expected to double from ~50 mm2 to ~100 mm2 due to increased  integration of new functionalities such as Graphics Processing Units (GPU), memory controllers, and input/output (I/O) interfaces. Overall power for such a chip in the distant future would consume >200W of power compared to today’s ~8W unless new technologies are employed. Some future drivers such as medical and defense are now in question; will these segments develop unique devices and processes or will they simply ride on the progress of mainstream commercial IC development.

“The latter scenario is looking more likely now,” said Kahng.

Constant area-factors allowed prior node scaling to be 2x, however since 2009 the real scaling has been 2E(2/3)x or ~1.6x due to an “IC Design Gap.” This gap is due to overheads from non-core blocks and additional overheads from PIDS effects on the area needed for cores. Design cost for a SoC consumer portable chip in 2011 were $40M, helped by commercial EDA software advances over the last decades. Today only at most 2.4 percent of the logic in an SoC is turned on at any time, which is how the power can be kept to ~8W.

Modeling and Process Simulation challenges were covered by Lothar Pfitzner of Fraunhofer IISB, with understanding that the overarching goal of this ITWG is to use virtual cycle-of-learning to lower R&D costs. To do so there are different models needed in different conceptual domains, “based on quantitative physical understanding of processes, devices, circuits, and systems,” explained Pfitzner. “Both short-term and long-term challenges remain in modeling of chemical, thermo-chemical and electrical properties of new materials.”

PIDS updates on logic, DRAM, and Non-Volatile Memory (NVM) were provided by Mustafa Badaroglu of Qualcomm. PIDS mission is to forecast device technologies likely to be used 15 years in the future of main-stream manufacturing. With Denard-scaling now part of history, the specifications for future transistors using either FD-SOI or multi-gate (such as finFET) technologies require TCAD simulations of source-to-drain tunneling, band structure effects due to strong confinement, as well as crystallographic orientation and strain. The current target is an overall eight percent power reduction per year in logic, but parasitics dramatically limit device performance, and gate-length scaling is endangered by increased tunneling.

A 2013 survey recently done by the Japan PIDS regional group provides a consensus on when new devices are expected to reach volume manufacturing. For DRAM cells there has been a slight relaxation of the planned half-pitch, and  the cell size transition from 6F2 to 4F2 planned for 2016 (delayed by two years from the last ITRS update), and vertical transistors are likewise planned for 2016. RRAM is now planned as mainstream technology in 2018, and is projected to catch-up with the bit density of 3D Flash in 2021; however, development of a selector diode in a 3D architecture remains a challenge. The Purdue University TCAD tools (NanoHub) will continue to be developed to better project device characteristics, and new websites within NanoHub will be created to allow free public access to the tools.

Part 2 of this blog will cover ITRS updates on Lithography, Front-End Processing, and Emerging Research Materials/Devices.

Click here for more from SEMICON West.


SEMICON Taiwan is set to open in September amidst an improving global and regional outlook for 2013 and 2014 that sees Taiwan remaining the largest and strongest market for semiconductor manufacturing. SEMICON Taiwan 2013, to be held September 4-6 at the Taipei World Trade Center Nankang Exhibition Hall, will spotlight the latest developments in processes, equipment, materials, and emerging market opportunities in microelectronics manufacturing from more than 650 exhibiting companies and more than 110 speakers from the world’s leading technology companies and research organizations.

Bucking the global trend of contraction in semiconductor spending, Taiwan has continued to build its position as the leading market for semiconductor equipment through the first half of 2013. According to the Worldwide Semiconductor Market Statistics report published by SEMI and the Semiconductor Equipment Association of Japan (SEAJ), spending on semiconductor equipment in Taiwan in the first quarter of 2013 rose to US$ 2.8 billion, 31 percent above Q4 2012 and 60 percent higher than the first quarter of 2012. The latest SEMI Consensus Forecast projects the Taiwan equipment market will rise more than 9 percent in 2013 and another two percent in 2014 to reach $10.6 billion, maintaining Taiwan’s status as the world’s largest equipment market.

"While the global market is looking towards recovery in 2014, Taiwan is building its strength and growing now," said Terry Tsao, president of SEMI Taiwan. "New electronic products and technologies, including mobile devices and 3D printing, are creating entirely new opportunities for microelectronics and driving the need to push the limits of Moore’s Law to enable the next generation of innovations. The technologies, companies, and people that will get us there are the highlight of SEMICON Taiwan."

In addition to the company exhibits and product displays, SEMICON Taiwan 2013 will feature more than 50 hours of technical and business forums, including presentations from global and regional industry leaders ASE, GLOBALFOUNDRIES, IBM, Micron, STMicroelectronics, TSMC, and Qualcomm among others. Scheduled sessions include the SEMICON Taiwan Executive Summit, the IC Design Summit, Market Trends, Memory Executive Summit, CMP Forum, Lithography/Mask Symposium, Advanced Packaging Symposium, Green Manufacturing, and sessions on MEMS and LED manufacturing.

Complementing the technical and business programs at SEMICON Taiwan, the third SiP Global Summit, Taiwan’s leading conference focused on advanced packaging and test, will feature speakers and participation from leading companies including Amkor, SPIL, SPTS, Nanya, PCB, Unimicron, Teradyne, Qualcomm, Yole Développement, SUSS MicroTec, and Senju sharing their insights and solutions for accelerating volume 3D IC production. In addition to support from the SEMI Taiwan Packaging and Test Committee, the SiP Global Summit is also coordinated in conjunction with the Fraunhofer Institute, I-Shou University, and the Industrial Technology Research Institute (ITRI).

Coventor, Inc., a supplier of virtual fabrication solutions for semiconductor devices and micro-electromechanical systems (MEMS), shared the SEMulator3D 2013 software platform at SEMICON West 2013. Conventor says the SEMulator3D 2013 brings physical accuracy and predictive modeling capabilities to process development and integration. This milestone release expands the value of ‘virtual fabrication’ to the broader semiconductor ecosystem in order to reduce silicon learning cycles and the billions of dollars spent reaching manufacturing readiness.

SEMulator3D 2013 release comes at a particularly critical time for semiconductor companies grappling with the complexities of integrated 3D front-end-of-line (FEOL) manufacturing processes such as Tri-Gate and High-k/Metal Gate logic, as well as advanced 3D memory technologies. Fabless design teams also face tremendous challenges migrating their intellectual property (IP) into these new technologies. SEMulator3D 2013 responds to such evolving requirements with an advanced virtual fabrication platform that makes it possible for foundry and fabless development teams to effectively collaborate at the physical process level.

“With new silicon architectures ramping quickly, IBM is introducing new manufacturing technologies that will keep us on the cutting edge of chip-making for server microprocessors, systems-on-chips and specialty silicon for consumer applications,” said Gary Patton, vice president, IBM Semiconductor Research and Development Center. “Tools such as Coventor’s SEMulator3D Virtual Fabrication platform have allowed us to speed our end-to-end technology development in 22nm and beyond, enabling a faster time to market for our customers who depend on IBM innovation to create the latest servers, smart phones, GPS systems, routers and other devices.”

At the core of the new SEMulator3D 2013 platform is a physics-driven modeling paradigm for addressing physical process behavior that makes virtual fabrication more predictive and provides new opportunities for replacing actual silicon learning cycles with faster, less costly virtual cycles. In addition, virtual metrology innovations and the automation of virtual experiments enable process developers to perform virtual fabrication operations in hours or days instead of the months required for actual silicon learning cycles.

“Time and complexity challenges are the two constants in semiconductor design and manufacturing, and the growing trend toward 3D integrated technologies like FinFETS has introduced unprecedented levels of pain in both areas. SEMulator3D 2013 addresses the need for more efficient, automated approaches to process modeling, as well as the need for greater levels of collaboration by both ends of the development process. The net result is a dramatic reduction in the time and cost required to leverage the most advanced manufacturing techniques required to keep pace with Moore’s Law and fuel even more innovation across the electronics industry,” according to Dr. David Fried, chief technology officer at Coventor.

SEMulator3D 2013 features a new surface evolution engine and seamlessly combines the benefits of advanced physics-driven and high-speed behavioral (‘voxel’) predictive modeling in a single, easy-to-use platform. Voxel modeling is a fast, robust digital approach capable of scaling to the requirements of integrated processes and large silicon areas. Surface evolution is a more analog approach capable of modeling a wide range of physical process behavior.

Coventor’s unique deployment of surface evolution facilitates a major step forward in modeling reactive ion etching and selective epitaxial growth, a key technique for creating channel stress in advanced planar and FinFET technologies. With SEMulator3D 2013, users can model etching of multi-material stacks with multiple types of etch physics, such as redeposition (passivation), sputtering (physical etching), and etch bias (lateral or chemical etching). They can also model the growth rates of major silicon plane families to predict the faceted shapes and structural ramifications of selective epitaxial growth.

The SEMulator3D 2013 platform incorporates advanced technologies and tool enhancements that enable automatic process variation analysis with parallel modeling and virtual metrology to significantly increase user productivity. A new spreadsheet-driven Expeditor tool for batch processing enables massively parallel parameter studies. The addition of new virtual metrology steps into the virtual fabrication process provide for in-line, local measurement of critical dimensions, mimicking actual metrology operations. Tool upgrades include an enhanced Materials Editor for hierarchical grouping of materials, which greatly simplifies process deck development and maintenance.

SurplusGLOBAL, Inc. participated in Semicon West 2013. SurplusGLOBAL CEO, Bruce Kim forecasted the increase in demand in the Asia Secondary Equipment Market.

Bruce Kim, CEO  of SurplusGLOBAL, has participated in Semicon West for the past 7 years and stated, “We are more optimistic about the growth in the Asian Secondary Semiconductor Equipment Market in the years to come.”

Secondary semiconductor equipment addresses both environmental and cost concerns within the industry. The secondary equipment market size has experienced continuous growth over the past three years. In 2012 the market size was estimated to be around 3 billion US dollars, with 200mm wafer capturing 90% of this market. In 2013, demand of 300mm wafer equipment is expected to capture an increased share of the demand.

With the growth in demand, distribution and services are becoming more critical every year. The number of Fab facilities in the United States and Europe continues to experience decline, while in Asia there has been continued investment in the China, Taiwan and South Korean markets. The Asian market accounts for approximately 80% of the semiconductor equipment market. The Asian secondary equipment market has been experiencing continued growth and global, financially stable traders such as SurplusGLOBAL are well positioned to lead the supply of this equipment.

The market has been very slow for last two years in Asia since the second half of 2011.  Most of the Asian players enjoyed the market recovery in Year 2010 and the 1st half of 2011.  After then, utilization rates at Foundries plummeted to levels, LED fabs suffered from slow demands and price pressures. The sales revenues of Asian dealers and refubishers have declined up to 70 percent.  These days we can see several ongoing expansion plans mainly from Taiwan and China Foundries as well as a few new Fab plans in China.  LED Fabs are resuming the purchase of tools.  Analog and Power device makers are adding bottleneck tools.  The demands of Fab tools from packaging companies are increasing.   

Bruce Kim commented “The major market drives are Foundries who want to expand their capacity or build new Fabs mainly in Taiwan and China. There are increasing demands of secondary equipment in mature technology including not only 8 inch silicon wafer, but also LED, packaging and MEMS."

To date, this demand has been driven by both 200mm FAB front and backend tools. We project starting growth of 300mm FABs in Asia. Powerchip sold hundreds of 300MM tools in the 1st Half to many Asian Fabs.  GLOBALFoundries acquired a thousand of Fab tools from Promos and sold many of them to China new fab recently. Bruce Kim mentioned,   “300mm Fabs have difficulty in purchasing secondary equipment because of insufficient support from equipment suppliers, so SurplusGLOBAL expects it will take considerable time for the  300mm secondary equipment market to take off.”

SurplusGLOBAL locates, sells and stocks thousands of systems annually and has established an extensive global network of end users, refurbishers and brokers. SurplusGLOBAL specializes in semiconductor manufacturing equipment acquired from the leading chip manufacturers in the United States, Europe and Asia covering Fab, ATE and PCB/SMT capital equipment segments.

cyberTECHNOLOGIES GmbH announced the addition of White-Light Interferometry (WLI) to its suite of production-proven CT SERIES non-contact surface metrology systems at SEMICON West 2013. WLI significantly broadens the range of use cases and applications of the existing CT SERIES, CT 100, CT 300 and CT x50T product lines and allows the user to not only scan large areas or samples, but also to zoom in on very small areas of interest for sub-nm analysis.

The new WLI modules can be installed either by itself or concurrently with the existing point sensors and provides the user with the ability to measure a broad range of applications, from surface topographies and printed structures on the order of several hundred micrometers down to sub-nanometer resolution surface roughness measurements, in a single system.

“Our customers want to take advantage of our superior user interface and automation capabilities not just in scanning applications but also for use cases where sub-nanometer resolution is required, “ said Frank Kemnitzer, head of product management at cyberTECHNOLOGIES GmbH. “With the WLI module installed, they can now select between different measurement technologies and adapt the measurement system to their requirement at hand. All within the same easy to use interface, the same advanced analysis capabilities, without learning how to use another system.” The systems were designed with modularity and versatility in mind and the addition of the new WLI sensors further broadens their range of applications.

Be it for quick, individual measurements on a single or multiple samples or the automatic inspection of complete production runs, cyberTECHNOLOGIES’ SCAN SUITE makes it simple and easy for the user to get accurate results.

Multiple systems with WLI  have been installed at leading manufacturers in Europe, Asia and North America.

At SEMICON West 2013, Boston Semi Equipment (BSE), LLC announced the expansion of its semiconductor front end and back end equipment businesses in Tempe, Ariz. into a new and larger facility. The new location provides space for the company’s increasing workforce, a test floor for the reconfiguration of current generation semiconductor test equipment and customer test cell optimization, a temperature controlled environment for front end fab tool inspections and increased storage space for the company’s inventory of ready-to-ship semiconductor manufacturing equipment.

 “Our company has continued on a steady growth path since its founding in 2010,” stated Bryan Banish, Boston Semi Equipment CEO. “Our new location increases the company’s capacity to reconfigure and refurbish equipment to support our expanding business. We are able to configure and work on more systems in parallel, reducing our already short lead times and increasing our ability to quickly deliver large orders to meet our customers’ capacity requirements.”

 “Semiconductor manufacturers have come to rely on Boston Semi Equipment when they need to add capacity,” added Colin Scholefield, EVP Boston Semi Equipment. “We have established a reputation for quick response to their capacity needs. Whether they need equipment from OEMs or reconfigured equipment from the secondary market, BSE has the solution. This new facility will definitely aid us in keeping up with the increasing demand for our equipment solutions.”

Boston Semi Equipment currently has operations in Burlington, Mass., Tempe, Ariz., the Philippines, Japan, Taiwan and Singapore, providing products and services for both front and back end semiconductor processes.