Category Archives: Semicon West

Solid State Technology and SEMI announced the recipient of the 2013 “Best of West” Award — Mentor Graphics — for its Tessent TestKompress with Cell-Aware ATPG.  The award recognizes important product and technology developments in the microelectronics supply chain. Held in conjunction with SEMICON West, the largest and most influential microelectronics exposition in North America, the Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact.

The Mentor Graphics Tessent TestKompress with Cell-Aware ATPG significantly improves on the standard process for testing digital integrated circuits and reduces failure escape rate by detecting defects at the transistor level that are missed by traditional automatic test pattern generation (ATPG) techniques. The Mentor Graphics booth is in the North Hall, Booth #6243. Their winning entry was entered in the “Silicon Test Solutions, Facilities & Software” category.

The Best of West Award winner was announced during SEMICON West on Wednesday, July 10, 2013 at 1:00pm.

Leaders of research consortia from around the world sat down to share updates and insights with SEMICON West attendees on Wednesday morning. In a panel led by SEMI President Karen Sevala, four executives from SEMATECH, CNSE, CEA-Leti and imec discussed their companies’ focus and progress on lithography, 3D stacking and ICs, memory and logic and more.

Lithography was a huge project and priority to three out of the four consortia represented and was the first topic brought to the panel by Sevala.

“Lithography is one of the highest priorities of our industry,” said Luc Van den hove, CEO of imec.

Van den hove said that he was very positive about EUV, confident that it was going to be available very soon. Daniel Armbrust of SEMATECH echoed Van den hove’s sentiments, reinforcing the importance of EUV’s availability for the continuation of Moore’s law.

“EUV must happen,” Armbrust emphasized to the crowd. SEMATECH’s EUV program, he said, has been focused on taking the manufacturing technology and making sure it’s ready for high volume production.

“The technology is in relatively decent shape,” Armbrust said. The challenge, he explained, is defect performance.

3D stacking and TSVs were also a hot topic. Michael Liehr of CNSE said, while important, 3D has been slower to take off than expected.

“The cost and implementation are still a lot more extensive than typical packaging solutions,” Liehr said. “We hope that this technology will lead to a leap in performance.”

Van den hove shared that imec believes that 3D stacking and ICs are very important technologies, and that the consortia started their programs about ten years ago.

“One of the biggest challenges with this technology is that we have two worlds that need to meet,” said Van den hove, in an effort to encourage industry collaboration.

Concerning memory and logic, Armbrust said that SEMATECH has been moving to 3D structures and focusing on the 7nm node, which has inevitably led to changes in device structure.

“The most promising candidate,” said Armbrust, “is replacing silicon with a material that provides III-V compounds.”

 

SEMI honored 14 industry leaders for their outstanding accomplishments in developing standards for the microelectronics and related industries. The SEMI Standards awards were announced at a reception held during SEMICON West 2013.

The 2013 SEMI International Standards Excellence Award, inspired by Karel Urbanek, is the most prestigious award in the SEMI Standards Program. Yesterday, it was awarded to Dr. Larry Hartsough of UA Associates.  Hartsough has been actively involved in SEMI Standards for over 20 years, serving in a variety of leadership positions. With over 30 years’ experience in the industry in the areas of thin-film deposition, equipment design and plasma processing of materials, he was instrumental in the development of cluster tool and 300mm interface Standards for semiconductor equipment. Additionally, Hartsough’s expertise in patent litigation was invaluable in guiding the Physical Interfaces and Carriers Committee on intellectual property issues. Long-term, committed leaders like Hartsough provide continuity and excellence to the SEMI Standards Program. The Award recognizes the leadership of Karel Urbanek, a SEMI Board of Directors member who was a key figure in the successful globalization the Standards Program.

In addition, the recipients of four major North American SEMI Standards awards were announced:

The Merit Award recognizes Standards Program Member major contributions to the semiconductor, PV, and related industries through the SEMI Standards Program.  Award winners typically take on a very complex problem at the task force level, gain industry support, and drive the project to completion. This year, seven Program Members were presented with the Merit Award for their contributions to the semiconductor, PV, 3D-IC, and HB-LED industries: 

  • Contribution to the PV Industry: Existing SEMI test methods did not provide the ability to measure a broad range of trace elemental impurities in silicon feedstock for solar cells. Through the International PV Analytical Test Methods Task Force, Hugh Gotts (Air Liquide Electronics U.S.) led the development of SEMI PV49-0613, Test Method for the Measurement of Elemental Impurity Concentrations in Silicon Feedstock for Silicon Solar Cells by Bulk Digestion, Inductively Coupled-Plasma Mass Spectrometry.
  • Contribution to the HB-LED Industry: The 150mm sapphire wafers used for manufacturing HB-LED devices are thicker than standard silicon wafers used in the semiconductor industry— making it difficult to use the same cassettes and standards. SEMI HB-LED Equipment Automation Task Force leaders, Jeff Felipe (Entegris) and Daniel Babbs (Brooks Automation) led the development of SEMI HB2-0613, Specification for 150mm Open Plastic and Metal Wafer Cassettes Intended for Use for Manufacturing HB-LED Devices. This cassette standard also enables standardization of load ports and transport systems, resulting in both direct and indirect cost savings throughout the whole supply chain.
  • Contributions to the 3DS-IC Industry: Establishing common understanding and precise communication between stakeholders is important in any manufacturing supply chain, including 3DS-IC. North America 3DS-IC Inspection & Metrology Task Force leaders, David Read (NIST) and Victor Vartanian (SEMATECH), led the successful development of the first 3DS-IC standard published by SEMI, SEMI 3D1-0912: Terminology for Through Silicon Via Geometrical Metrology. It provides consistent terminology for metrology issues important to through silicon vias (TSV), including: pitch, top CD, top diameter, top area, and more. Read and Vartanian were also responsible for the successful development of two other 3DS-IC SEMI Standards — SEMI 3D4 (Bonded Wafer Stack Metrology) and SEMI 3D5 (TSV Metrology).
  • Ilona Schmidt (Corning) was the key developer of SEMI 3D2-0113, Specification for Glass Carrier Wafers for 3DS-IC Applications.  SEMI 3D2 describes dimensional, thermal, and wafer preparation characteristics for glass starting material that will be used as carrier wafers in a temporary bonded state.
  • Contribution to the Semiconductor Industry: Manufacturing equipment is complex, which makes it susceptible to operating errors due to electromagnetic interference (EMI).  SEMI E33 provides recommendations to help assure that manufacturing equipment will operate reliably without failures caused by electromagnetic interference (EMI).  This desired characteristic is generally known as electromagnetic compatibility (EMC). Last year SEMI E33 went through an extensive revision led by technical expert Vladimir Kraz (BestESD Technical Services).

The Leadership Award recognizes Program Members’ outstanding leadership in guiding the SEMI Standards Program.  Since the formation of the HB-LED Technical Committee in late 2010, Julie Chao (Silian Sapphire) and David Joyce (GT Advanced Technologies) have led the Wafer Task Force in defining the physical geometry of wafers used in HB-LED manufacturing.  Their efforts resulted in SEMI HB1-0113, Specifications for Sapphire Wafers Intended for Use for Manufacturing High Brightness-Light Emitting Diode Devices— SEMI’s first HB-LED standard. As task force leaders, Chao and Joyce fostered industry collaboration, travelling to global SEMI events and attracting new key stakeholders, ensuring global input and consensus.

The Honor Award, given to an individual who has demonstrated long-standing dedication to the advancement of SEMI Standards, recognized Richard Allen (NIST/SEMATECH). From his involvement in the Microlithography/Micropatterning Committee to his current leadership in the 3DS-IC and MEMS/NEMS Committees, Allen has been a long-standing and active participant in the SEMI Standards Program.  He joined the 3DS-IC committee shortly after it was formed in late 2010 as serves as committee chairman. He also leads the Bonded Wafer Stacks Task Force, Inspection & Metrology Task Force and Thin Wafer Handling Task Force). His contributions have been instrumental in the publication of four SEMI 3DS-IC Standards to date.

The Corporate Device Member Award recognizes the participation of the user community. This year, three Program Members were presented with the Corporate Device Member Award for their contributions to EHS and 3DS-IC. This year’s Corporate Device Member Awards were presented to Paul Schwab (Texas Instruments), Urmi Ray (Qualcomm), and Raghunandan Chaware (Xilinx).  The award is presented to individuals from device manufacturers.

As co-leader of the S8 Ergonomics Task Force, Paul Schwab (Texas Instruments) provided end-user perspective in the revision of SEMI S8, Safety Guideline for Ergonomics Engineering of Semiconductor Manufacturing Equipment. Schwab significantly improved the Supplier Ergonomics Success Criteria (SESC) checklist criteria, making the Document easier to use by the industry.

Another example of the importance of end-user input was in the development of SEMI’s third 3DS-IC Standard – SEMI 3D3-0613, Guide for Multiwafer Transport and Storage Containers for 300mm, Thin Silicon Wafers on Tape Frames. North America 3DS-IC Thin Wafer Handling Task Force Leaders Urmi Ray (Qualcomm) and Raghunandan Chaware (Xilinx) played integral roles in the development of SEMI 3D3-0613, providing vital end-user perspective for shipping thin wafers on tape frames so that they arrive undamaged at their final destination.

The SEMI Standards Program, established in 1973, covers all aspects of microelectronics process equipment and materials, from wafer manufacturing to test, assembly and packaging, in addition to the manufacture of photovoltaics, flat panel displays and micro-electromechanical systems (MEMS). Over 3,700 volunteers worldwide participate in the program, which is made up of 23 global technical committees. Visit www.semi.org/standards  for more information about SEMI Standards.

 

 

At Leti Day during SEMICON West, Leti Lithography Program Manager Serge Tedesco highlighted different lithography options for advanced technology nodes. Dr. Tedesco suggested that an “optical forever” solution using 193nm immersion lithography in combination with a pitch-multiplication strategy could well provide lithography solutions to very advanced nodes on the industry’s technology roadmap.

Nevertheless, this option will face cost issues, and maskless lithography (ML2) and directed self assembly (DSA) could be very effective as complementary techniques that provide significant cost reductions on some critical levels.

To support their development, Leti created two industrial programs, IMAGINE for ML2, and IDeAL for DSA. Tedesco presented the roadmaps and technical status for both programs, which include large consortiums of industrial partners: IMAGINE around MAPPER Lithography tools, and IDeAL around Arkema’s block copolymer materials for DSA.

Tedesco also noted that Leti’s goal with both programs is to set up the necessary infrastructure to support the industry’s transition toward these complementary technologies.

Biography Dr Serge Tedesco:

Serge Tedesco joined CEA-Leti in Grenoble to take charge of e-Beam lithography, and consequently all advanced lithography activities. Since 2003 he has managed CEA-Leti’s lithography strategy and programs as lithography program manager. Dr. Tedesco has authored or co-authored more than 110 papers in the field of lithography and is a program committee member of the major International lithography conferences. He has been involved in numerous European projects, both as project leader and expert.

CEA-Leti and EV Group (EVG) have launched a three-year common lab to optimize temporary- and permanent-bonding technologies related to 3D TSV integration and all direct bonding heterostructures. 

The lab, which continues more than 10 years of collaboration between the two organizations, is focusing on hardware, software and process development.

“Temporary and permanent bonding equipment and process solutions are key product offerings for EVG,” said Markus Wimplinger, EVG’s corporate technology development and IP director. “This project leverages CEA-Leti’s global leadership in wafer-bonding research and EVG’s unparalleled expertise in developing wafer bonding equipment and process technology.”

“Like all common labs that Leti creates with its partners, this project is designed to produce specific, practical solutions that address current and future market requirements,” said Laurent Malier, CEA-Leti CEO. “This collaboration is targeting results that will make 3D TSV integration more efficient and cost effective and open new areas of wafer bonding using covalent bonding at room temperature.”

“Bringing these approaches to high-volume manufacturing with reliable wafer bonding requires innovative fabrication processes,” said Fabrice Geiger, head of Leti’s Silicon Technology division. “The new equipment and process technology developed within the common lab will allow exciting possibilities, especially for heterogeneous materials stacks, that require very low-temperature wafer bonding.”

Leti is an institute of CEA, a French research-and-technology organization with activities in energy, IT, healthcare, defence and security. Leti is focused on creating value and innovation through technology transfer to its industrial partners. It specializes in nanotechnologies and their applications, from wireless devices and systems, to biology, healthcare and photonics. NEMS and MEMS are at the core of its activities. CEA-Leti operates 8,000-m² of clean room space on 200mm and 300mm wafer platforms. It employs 1,700 scientists and engineers including 320 Ph.D. students and 200 assignees from partner companies. CEA-Leti owns more than 2,200 patent families.

EV Group (EVG) is a supplier of equipment and process solutions for the manufacture of semiconductors, microelectromechanical systems (MEMS), compound semiconductors, power devices, and nanotechnology devices.  Key products include wafer bonding, thin-wafer processing, lithography/nanoimprint lithography (NIL) and metrology equipment, as well as photoresist coaters, cleaners and inspection systems.  Founded in 1980, EV Group services and supports an elaborate network of global customers and partners all over the world.

Click here for more announcements from SEMICON West 2013 or follow us on Twitter.

SEMICON West 2013 included a robust set of technical and marketing presentations on the general theme of developing new semiconductor devices in the session “Lab to Fab: From R&D to High Volume Manufacturing” held 1:30-3:30PM on July 9. Ably moderated by Paula Doe, the session included presentations on modeling, experimenting, and prototyping new materials and structures such that they can profitably moved into high-volume manufacturing (HVM). Two of the presentations that described not just technologies but new fundamental methodologies for R&D came from Coventor and Intermolecular, small innovative companies based in Silicon Valley.

Dr. David Fried, CTO of Coventor, presented how the company’s “SEMulator3D” software modeling product based on “voxels” allows for advanced physics-based modeling of unit-processes, integrated-processes, device structures, and even device electrical parameters. The modeling starts with unit-processes such as depositions, etches, and epitaxial growth at the nanometer-scale. However, unlike TCAD and other device models, this software can also extend across length scales to provide full-wafer maps of physical parameters.

Fried explained how the model is built on data extracted from publicly available leading device information, such as the cross-section SEMs in Intel’s seminal IEDM paper on 22nm finFETs. The model is “behavioral” since it can predict the effects of changes in dynamic process conditions, and can therefore be used to do “virtual fabrication” of targeted devices. “You can do some interesting explorations,” explained Fried, “like what if you had a defect on a fin that was used to grow an epi-layer?” He showed how the complex interactions of different growth rates in different crystalline directions on 3D structures could be predicted by the software, and that the predicted structural shifts  appear to match the SEM cross-sections shown in the literature.

This modeling software can thus be used as a “virtual metrology” tool that can mimic real in-fab metrology. It can replace slow out-of-fab destructive characterization, and can provide local virtual measurements of structural parameters. It can be used to study the effects of incoming geometric parameters as well as process variations on the final structure. For example, the Cu cross-section area of a BEOL interconnect layer can be predicted, in contrast to unit-process models/controls that merely create wafer-uniformity-maps of  Etch, Cu-barrier/seed PVD, Cu-ECD, Cu-CMP, and other process steps.

Combinatorial R&D

Dr. Raj Jammy, Sr. VP & GM Semiconductor Group, Intermolecular, Inc.—most recently a SEMATECH VP—discussed the need for new ways of doing R&D now that the integration of new materials dominates device enhancements. As semiconductor technology has evolved to smaller and smaller device geometries, the number of new materials used on CMOS chips continues to increase. Consequently, the cost of discovering and integrating new materials into complex devices structures continues to increase.

New materials are needed for 3D FinFETs (alternate-channel materials), 3D Flash Memories and ReRAM (storage cells), and 3D packaging (through-silicon vias and through-mold vias), and all  use complex processes with unpredictable interactions. Developing and optimizing these new materials leads to high costs for R&D and even higher costs to integrate into HVM.

Intermolecular has created High Productivity Combinatorial (HPC™) tools for PVD, CVD, ALD, and wet-processing steps that allow for multiple site-isolated experiments to be done on a single 300mm wafer. When combined with throughput-match characterization tools using an automated database into what the company terms an application-specific “HPC workflow,” everything from an initial design-of-experiments (DOE) to full HVM integration can be done in 3-6 months instead of the 3-5 years needed by conventional R&D approaches.

HPC workflows can accelerate R&D in the early stages of materials exploration such that an entire cycle-of-learning can occur in just 4 hours. HPC workflows can also be used with short-loop flows through a customer’s fab to allow for a 3-4 week cycle-of-learning.

As an example of this methodology’s ability to accelerate learning, Jammy showed how hundreds of experimental parameters had to be explored in developing a germanium (Ge) MOS cap for CMOS integration. Variations in the substrate, surface cleaning, High-K stack, metal electrode, and post-treatment all play significant roles in determining the final device parameters. All these factors had to be co-optimized iteratively, and the project was accomplished in <3 months.

IMI started in 2004 with SanDisk and ATMI, and has since added Guardian Corp., Toshiba, IBM, First Solar, GlobalFoundries, Epistar, Micron as customers.

 

When Ajit Manocha, GlobalFoundries CEO, polled his audience during his keynote address on Tuesday at SEMICON West 2013, nearly 60 percent of the audience believed that the biggest challenge facing the semiconductor industry was the economy. However, during his presentation, Manocha seemed to suggest otherwise.

The technology business is booming, according to Manocha, who shared with SEMICON attendees that the mobile business is forecast to be double the size of the PC market in 2016. The mobile business drives many new requirements, said Manocha, including power, performance and features, higher data rates, high resolution multicore processors and thinner form factors.

This incredible growth is driving new dynamics, said Manocha, and pushing the industry to the new technology node each year, which is presenting the industry with what Manocha deems the Big Five Challenges. Manocha believes these challenges are: cost, device architectures, lithography and EUV, packaging and the 450mm wafer transition.

Cost, said Manocha, continues to be the underlying challenge of the entire industy, because, without focusing on wafer cost, even in good times, a company can enter into what he called “profitless prosperity.” Unfortunately, with the introduction of a new technology node each year, advanced technology costs are rapidly rising.

“Fab cost alone escalates 40 percent year after year,” said Manocha.

To keep wafer costs down, what Manocha believes the industry needs for success is a new foundry model altogether. His model, which he calls Foundry 2.0, hinges on industry collaboration rather than wafer price competition. By encouraging the industry to work together on products and meet the same goals, the industry can see a faster rate of change and tap into global R&D talent.

“The best solutions rarely originate from an insultated team,” he said. “It’s critical that we understand what customers need.”

SEMI recognizes GLOBALFOUNDRIES CEO

Click here for more news from SEMICON West or be sure to follow us on Twitter.

What do you think? Tell us in the comment section below.

At SEMICON West 2013, Element Six today announced it has expanded its global manufacturing capabilities of microwave chemical vapor deposition (CVD) synthetic diamond by 60 percent compared to last year. Driven by growth in the company’s semiconductor and optical business segments, Element Six has effectively ramped production capacity to meet emerging demand for thermal management solutions including gallium nitride (GaN)-on-diamond substrates and high-power resistant optical windows for Extreme Ultraviolet (EUV) lithography systems.

“Our bookings have seen a 30 percent increase in compound annual growth over the last two years, and we attribute the majority of our expansion to new applications in the semiconductor market,” said Adrian Wilson, head of the technologies division at Element Six. “We are seeing more interest from packaging designers and manufacturers as the industry comes to recognize the numerous properties and benefits of synthetic diamond, which offer our customers a distinct competitive advantage to further differentiate and strengthen their solutions for a greater return on investment.”

Element Six has expanded its high-volume manufacturing capabilities across its facilities in Silicon Valley, California, and Ascot, United Kingdom—the latter already serving as the world’s largest CVD diamond manufacturing site. The three key areas of production supported at the built-out sites include:

  • CVD diamond thermal material—delivering thermal conductivity between 1000 to 2000 W/mK, synthetic diamond is integrated into semiconductor modules to serve as an effective heat spreader—driving to more than a 20 degree temperature decrease to quadruple a device’s lifetime.
  • Synthetic diamond optical windows—an enabler for Laser Produced Plasma (LPP) EUV lithography system, Element Six’s large CVD synthetic diamond optical windows (71-80mm in diameter) withstand the power levels necessary to produce EUV light—reducing system downtime and improving wafer throughput.
  • GaN-on-diamond wafers—one of the world’s most thermally conductive materials, GaN on free standing polycrystalline CVD diamond is up to five times more conductive than copper at room temperature—enabling rapid, efficient and cost-effective heat extraction that lowers operating temperature and overall system level costs, and increases the power of RF devices. GaN-on-diamond technology earned a Compound Semiconductor Industry Award for its ability to achieve up to a three-fold improvement in heat dissipation, while preserving RF functionality.

To further consolidate and strengthen the company’s innovation capabilities, Element Six also opened its new Global Innovation Centre (GIC), based in Harwell, near Oxford, this month. Building on Element Six’s 50 years of R&D heritage, the GIC will enable the company to rapidly design, manufacture and test market-ready solutions in one location.

For those interested in learning more about synthetic diamond’s diverse properties, semiconductor applications, and the company’s research and development efforts, please visit Element Six’s booth #5750 at SEMICON West.

 

Dow Corning announced Monday that it is among the newest member organizations to join imec, a leading research center for the advancement of nano-electronics. The announcement signals expanded opportunities for both organizations to combine their expertise toward the development and broader adoption of 3D integrated circuit (IC) packaging technologies, wherein IC chips are stacked in vertical 3D architectures.

“This move is a natural and strategic step for Dow Corning and imec, as we both believe collaborative innovation is as critical to industry leadership as native expertise,” said Andrew Ho, global industry director, Advanced Semiconductor Materials at Dow Corning. “Our access to imec’s world-class resources and expertise will not only help us further refine our unique temporary bonding solution, it will allow imec to leverage that solution to advance integration of the 3D IC packaging process that they’ve been developing for years.”

Yet, before 3D IC fabrication can see broader adoption, it will require innovative advances in materials and processing technologies.

One of the key challenges imec is tackling is the bonding of the device wafer to a carrier wafer, prior to wafer thinning, and the safe debonding of the thin wafer after completion of backside processing. This was Dow Corning’s goal when designing its Temporary Bonding Solution, aims at simple processing using a bi-layer concept comprising an adhesive and release layer. The technology also enables room-temperature bonding and debonding processes based on standard manufacturing methods.

Together with imec, Dow Corning will explore its temporary bonding CMOS-compatible solution for 3D Through-Silicon-Via (TSV) semiconductor packaging. The collaboration will aim to further expand the technology’s ability to achieve simple, cost-effective bonding-debonding techniques compatible with standard manufacturing processes.

“Imec’s precompetitive programs are an essential platform for industry leaders to share the risk and cost of advanced research. As one of the semiconductor industry’s most proven pioneers in advanced silicone-based solutions, Dow Corning brings valuable materials and processing expertise to imec’s global network of innovators – as well as a key enabling technology for TSV fabrication,” said Eric Beyne, program director 3D System Integration at imec. “We look forward to collaborating closely with our newest member organization as we drive the next stage of 3D integration, and help ensure compatiblity of the proposed thin wafer carrier solution with advanced, sub-10-nanometer CMOS device technologies.”

Imec exhibits at SEMICON West, July 9-11, 2013 at booth 1741, South hall.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has achieved strong revenue growth and expanded its headcount for the first half of 2013.  The company attributes this success to continuing demand for its flexible process solutions designed to address high-volume manufacturing (HVM) needs across multiple markets–including 3D-ICs, MEMS, power devices and compound semiconductors.  EVG’s latest technology innovations that address these and other markets will be showcased this week at SEMICON West 2013 at the Moscone Convention Center in San Francisco.  In addition to unveiling a series of new solutions, EVG also reports that it continues to expand its wafer processing services and process development consultation capabilities worldwide as part of the company’s long-term growth strategy. 

"2013 has been a strong year for EV Group as we continue to invest in new technologies and capabilities to support our customers’ ability to ramp next-generation devices to volume production quickly and cost-effectively at high yields," said Dave Kirsch, vice president and general manager of EV Group North America.  "This requires not only leading-edge process equipment but also world-class global support and process development services. EVG’s local teams work hand in hand with our corporate headquarters to provide increased flexibility and capability for our customers.  That includes our ability to offer small-scale and pilot-production services at our global applications labs, which is a key differentiator for us and a key value proposition for customers."

Expanding sales growth and global customer support operations

During the first half of 2013, EVG achieved approximately 10 percent growth in sales and more than 10 percent increase in employees. To support its customers’ roadmaps, EVG continues to invest aggressively in research and development–approximately 20 percent of sales–in several key efforts, including 450-mm tool development. Among these efforts, EVG has invested in new state-of-the art cleanrooms and application labs with in-house process demo capability on fully automated systems at its corporate headquarters in Austria, as well as its regional headquarters in Japan and North America. 

VLSIresearch recently recognized EVG’s customer service and support, ranking it at one of the 10 Best Focused Suppliers in Chip Making Equipment. EVG was also ranked in first place in the "Other Silicon Wafer Fab Equipment" category for the company’s wafer bonding solutions. 

Leadership in wafer bonding

Already a leading supplier of HVM wafer bonding solutions, EVG recently unveiled several new platform developments in both fusion bonding and temporary bonding/debonding applications.  Yesterday, EVG unveiled the latest version of its EVG 40NT automated measurement system, which features improved specifications to achieve the highest wafer-to-wafer alignment accuracies needed for the production of next-generation 3-D integrated image sensors and stacked memory devices.  The EVG40NT is seamlessly integrated with EVG’s GEMINI FB automated production fusion bonding system to enable a closed-loop control system that facilitates customers’ ramp to volume production across multiple markets and applications.  Last week, EVG also introduced its LowTemp debonding platform, which features three high-volume-production room-temperature debonding process types and is supported by a supply chain of seven qualified adhesive suppliers to enable greater manufacturing flexibility.

Expertise in lithography and resist processing

Building upon the company’s expertise in lithography, EVG also recently unveiled the EVG120 automated resist processing system, which integrates spin/spray coating and wet processing to provide a highly flexible system that maximizes productivity and cost of ownership.  The EVG120 is ideally suited for a wide variety of markets and applications, including high-topography coating and spray coating for MEMS, thick-film resists and bumping for advanced packaging.  It is also suited for passivation, dielectrics and thick-film processing for compound semiconductor devices.

Rounding out EVG’s latest developments in wafer surface preparation, the company also recently announced the CoatsClean wafer cleaning solution, which combines process, equipment and formulation technology to deliver an innovative, low-cost-of-ownership approach to single-wafer photoresist and residue removal.  Co-developed with Dynaloy, CoatsClean is designed to address thick films and difficult-to-remove material layers for the 3D-IC/through-silicon via (TSV), advanced packaging, MEMS and compound semiconductor markets.

Presentations at SEMICON West 2013

Attendees interested in learning more about the company and its latest developments are invited to visit EVG’s booth #819 in the Moscone South Hall at SEMICON West as well as attend the company’s presentations during the show’s technical program.  Markus Wimplinger, corporate technology development and IP director of EVG, will present "High Resolution In-line Metrology Module for High-Volume Temporary Bonding Applications at the SEMATECH Workshop on 3D Interconnect Metrology on Wednesday, July 10 from 11:20 – 11:40 a.m. at the Marriott Marquis in San Francisco. In addition, Dr. Thorsten Matthias, business development director at EV Group, will present "From Sensor Fusion to System Fusion" at the TechXPOT session "MEMS and Sensor Packaging for the Internet of Things" on Thursday, July 11 from 12:10 – 12:30 p.m. in the Moscone North Hall.