Category Archives: Semicon West

by James Montgomery, news editor, Solid State Technology

July 16, 2009 – Improve a process, save money and eliminate waste, with no loss of performance or efficiency, and go green at the same time. They’re the reasons Nano Green Technology was awarded SEMI’s 2009 Best of West award Wednesday (July 15) at SEMICON West, for its technology that replaces the traditional SC-1 or SC-2 etch-based cleaning process with a megasonics-based solution that relies on water. SST also takes a snapshot of the other Best of West finalists: Alchimer, Gore, IMEC, and K-Patents.

The company’s CCS-1000 (CCS stands for “critical cleaning system”) combines deionized (DI) water with a “slight amount” of ammonia gas as a seed (a $300 Evian-bottle-sized amount lasts a year) to form molecularly-activated clusters (trademarked and branded as IMACS, for “ionized molecularly-activated coherent solution”), which go out and seek charged particles, explained Michael Olesen, manager of applications and technology, in an interview with SST. An SC1 process has to etch through the boundary layer to pry loose particles from the material surface (causing roughening), and during rinse these particles are likely to fan out and reattract and reattach to the surface anyway. The water “clusters” in Nano Green’s DI water solution seek out, attract to, and hold the particles so they can be rinsed away, with no worry about redistribution and reattachment to the surface.

The technology is applicable to any tool platforms for all types of cleaning in batch (RCA, post BOE, pre-sacrificial oxide, pre poly gate, post metal, gate oxide) or single-wafer processing (pre metal etch, poly gate, pre-photoresist, post-CMP, pre diffusion.

The system’s benefits are striking: removal efficiency said to be equal to or better than SC-1 processing, with pre 99.0% for nitride particles (the company showed data to back up claims). There are virtually no chemicals or special handling costs, no loss of topography (no reaction with native oxides), no VOCs or metallic ions, “dramatically” reduced megasonics energy (thanks to the charged clusters), and no waste treatment — in fact, Nano Green president Jacob Mor told SST that customers are encouraged to flush the DI out in the drain where it captures garbage residues there, too. Considering the volumes of scale in a DI-based technology like this (potential 1M gallons/day through a fab), payback can be achieved in as little as five months, he noted.

The company, which first got a thumbs-up from Infineon and IMEC at the 2007 Surface Preparation and Cleaning Conference (SPCC), has five tools in the field, Mor said — one has been qualified and now in use at TSMC; another customer is in qual at 32nm (and later 22nm); another is in final eval at 37nm for final clean and post-CMP; and the company is in final discussions with Intel for use in both its fab and photomask operations. The system is also being explored by a hard-disk drive manufacturer, and a fifth tool is now shipping out in the field to an unidentified end-user. Market spread in the near-term will be ~75% semiconductors, ~15% HDD, and ~10% TFT/LCD. The company is also interested in the PV sector too — where presumably the “green” message will resonate even more strongly — but Mor indicated this won’t happen in the short-term.

Nano Green’s business model is in three phases, Mor explained to SST. Phase one is “industry recognition,” getting installs at handpicked users like Intel and TSMC. Once users are on board, Phase Two is to license the technology to the toolmakers. Phase Three, he said, will be to “build a farm” for end users to offer the technology directly. Once the company builds its valuation to ~$250M, he said (now at ~$12M, with a second funding round about to close), the goals are in the short-term, possible M&A, or longer-term, pursuing an IPO. — J.M.

Nano Green was one of five Best-of-West finalists. The others had compelling stories of their own:

Alchimer, AquiVia. This electrografting technology, which encompasses three process steps before filling a through-silicon via (TSV) with metal, seeks to replace dry steps with wet deposition of insulator, barrier, and copper seed layers in high-aspect ratio TSVs. The technology uses standard plating tools, and is independent of via depth — dry can’t go higher than ~5:1 AR; Alchimer CTO Claudio Truzzi told SST that in-house 18:1 AR has been achieved. It also offers a 10× better tolerance for “scalloping.” Truzzi noted that relative cost-of-ownership benefits for the eG wet process vs. a dry process (on new equipment) can exceed 50%. Next step for Alchimer is to expand the technology beyond its French headquarters to regional “application lab” capabilities. The company is fresh off a $10M round of funding, and is in final negotiations with an anonymous “Top-Tier” manufacturer to utilize their technology.

W.L. Gore, Filters for semiconductor applications. These 20nm-100nm-rated cartridge filters for chemicals, dilute chemicals, and ultrapure water in wet process tools incorporate a new high-flow ePTFE (expanded polytetrafluoroethylene) filtration media, which when rapidly stretched under the right conditions creates a very strong, microporous material with higher void values. It allows a drop-in retention upgrade from 100nm to 30nm, enabling cleaner recirculation baths and reduced processing times. Glowing quotes from a happy end-user shown to SST were a bit over-the-top, but the company showed slide after slide backing up claims with data, showing how replacing a 0.05μm ultrapure water filter with its 20nm ePTFE hydrophilic filter reduced particles by 55%-61% for particles ≥0.05μm and 0.1μm, pressure drop declined >90%, and nonvolatile residue rinse time went from several days to <3hrs.

IMEC, Slim-Cut. This method addresses a top challenge of crystalline Si solar photovoltaics: kerf-free wafering of substrates as thin as 50μm. A metallic layer is screenprinted on top of a thick c-Si wafer and high-temp annealed in a belt furnace; when the wafer cools, the difference in metal/silicon thermal expansion coefficients induces a stress in the substrate, which expands into a crack close to and parallel with the wafer surface. The top layer of Si and attached metal layer snap off, and the metal layer is etched away from the silicon foil, leaving an ultrathin silicon foil — and the remaining substrate can be reused to peel off further layers.

K-Patents, PR-33-S refractometer. This digital refractive index (RI) measurement technology promises to increase wafer throughput and cut down chemical costs from supplies down to fab in-line and tool in-situ chemical concentration control.

July 15, 2009: Semiconductors are at the heart of what is deemed “nanotech” in the electronics manufacturing world, having been working at the submicron level for years. Some areas in this sector are right in Small Times‘ wheelhouse: MEMS is a prime example, and analytical equipment also is a broad area of overlap. We generally tend to let sister publication Solid State Technology do the technical heavy-lifting for leading-edge semiconductor manufacturing discussions, though.

But a presentation from lithography tool supplier ASML yesterday at the annual SEMICON West in San Francisco, CA, caught our ear, because it crosses both areas. The company’s concept of “holistic lithography” is taking shape with two new products and a heavily customized package, one of which is a new illumination technology that uses a programmable array of thousands of micromirrors (instead of the traditional illuminator and diffraction optical element) to condition and shape the light with greater flexibility to create increasingly complex patterns. The result is a much more flexible and powerful way to shape light in multiple different complex ways to improve device patterning, improve process windows, and extend use of immersion lithography tools as far as possible until the long-awaited extreme ultraviolet (EUV) tools are ready for volume manufacturing.

So there you have it — extending the current leading-edge semiconductor technology capabilities, brought to you by MEMS devices. — J.M.

by Debra Vogler, senior technical editor, Solid State Technology

July 14, 2009 – Norcimbus FCIV Inc. has introduced its NBlend variable flow gas mixing system at SEMICON West. The new system allows manufacturers to transition away from using specialty gas cylinders and achieve cost savings by blending their own specialty gases in-house, implementing a facility’s existing bulk gas supply infrastructure. The company says its new system has been demonstrated to achieve a return-on-investment (ROI) in as little as 60 days (see the ROI calculation and comparison of a sample fab set-up in the figure below).


Sample ROI calculation and illustration. (Source: Norcimbus)
CLICK HERE to view larger image

Typical savings achieved by the NBlend system over one 24-hour period, with a 60 day ROI for a 40 slpm system: For the set-up shown in the figure, the system replaces 10 specialty gas cylinders; accuracy has a standard deviation <0.05% with a variable gas flow to accommodate actual fab demand over the 24-hour period. The system adjusts with fab gas requirements, instead of providing gas at a fixed rate and venting the excess to maintain performance levels. Cost savings are greater and ROI faster on higher flow systems; the system can accommodate up to 250 slpm.

The system’s closed-loop feedback and analysis capabilities enable it to maintain an extremely tight specification on the blended gases of ±0.3% accuracy ratio, according to the company. Mass flow controller (MFC)-based systems must mix continuously at a set flow rate, which results in the venting of excess gas. Norcimbus’ system measures the actual blend and performs the mixing in real-time, allowing gas to be delivered as needed and eliminating wasted materials.

Key to the NBlend’s capabilities, according to Norcimbus operations manager Brian Ebert, is an expansion on existing gas mixing technology — combining an MFC mixing system, surge tank, concentration analyzer, and a proprietary Power Purge V controller. The system is designed to mix two gases to an adjustable ratio and supply a variable flow up to 250 slpm continuously, while the concentration analyzer monitors and adjusts the blend ratio to maintain the concentration set point. In particular, the controller has been designed for continuous system monitoring, and the safe delivery and purging of ultra high purity (UHP) process gas systems. — D.V.

July 14, 2009 – SEMATECH’s Bryan Rice gives a positive assessment of EUV and offers hope for getting companies to open their checkbooks for mask inspection infrastructure funding. It’s no longer a matter of “if” but “when,” he says — and see news below of an imminent 100W source.

Key stakeholders have indicated they’re prepared to embrace EUV, and “the technology people have been primed” — but they’re still not ready to hand over big investments until funding is apparent. Rice is hopeful that after this week’s SEMICON West, the industry will “be in a position to maybe see the light at the end of the tunnel” for when money to fund EUV will become available.

July 14, 2009 – KLA-Tencor has taken the wraps off three new tools for defect wafer inspection and review: the 2830, the Puma 9500, and eDR-5210.

A key feature of the 2835 brightfield inspection tool is a broadband illumination source that allows selection of different wavelengths, a capability that can be used to suppress noise, or enhance the signal from defects — important capabilities to help find killer defects at the 32nm node, explained Brian Trafas, KLA-Tencor COO, in a briefing for SST just before SEMICON West. As system sensitivity improves to see small killer defects, those signals can be dwarfed by sources of noise, including color variations, grainy surfaces, low contrast pattern, and even a “noisy” previous layer.

Another area of focus with the new system is increased available light intensity, through a redesigned laser-pumped plasma source (called Power Broadband). “By improving the source, we’re able to make the pattern brighter, which gives improved contrast of pattern features relative to the underlying surface,” Trafas said. Another improvement is flexible imaging — selectable nodes and custom apertures in the illumination and collection channels, to enhance defect edges or suppress graininess, he noted.


KLA-Tencor’s 2830 Series. (Photo: Business Wire)

The Puma 9550 combines high-NA collection optics with a higher-power laser, enabling apertures, a new image acquisition system, and innovative algorithms, that together provide a >30% increase in sensitivity-at-throughput vs. the previous-generation darkfield inspection tool. New sensors are faster, a new laser scans at higher speeds, and the collection optics incorporate both darkfield and brightfield scattered light. “With the new and enhanced illumination and collection optics, they can now capture smaller defects at higher throughputs while preserving sensitivity at advanced nodes,” Trafas noted.


KLA-Tencor’s Puma 9500 Series. (Photo: Business Wire)

In the eDR-5210, KLA-Tencor redesigned the electron optics column, notably relocating the top and bottom detectors above the lens to move the working distance of the column much closer to the substrate. “By improving that effective working distance, we’ve been able to improve the resolution of the system to 1.9nm, and at the same time, we’ve been able to in a single detector, acquire both brightfield and darkfield information,” which allows collection of data in a single pass and provides a throughput advantage, Trafas said. “We’ve been able to get better resolution while acquiring topographic information in the same scan. This is a big improvement for a SEM review platform.” — D.V., J.M.


KLA-Tencor’s eDR-5210. (Photo: Business Wire)

(July 13, 2009) WILSONVILLE, OR &#151 Mentor Graphics Corporation’s Walden C. Rhines, Ph.D., will present the keynote at Semicon West 2009 in San Francisco, CA, this week. The chairman and CEO of the design software company will talk about the myths and realities of the global semiconductor industry on July 15, at 10 am.

Who: Dr. Walden C. Rhines, Chairman and CEO, Mentor Graphics Corporation
Keynote: “World Semiconductor Dynamics: Myth vs. Reality”
When: Wedndesday, July 15, 10-10:45 am
Where: Novellus Theatre at the Yerba Buena Center for the Arts (across from Moscone Center).

In his keynote address, Rhines explores some of the issues confronting the EDA industry in today’s tough economic environment and presents historical data and trends of the semiconductor industry with some surprising conclusions.

For more information, visit www.mentor.com.

by Debra Vogler, senior technical editor, Solid State Technology

June 29, 2009 – In a pre-SEMICON west technology briefing, SEMATECH’s director of lithography, Bryan Rice, gave a sobering assessment of the readiness of EUV mask infrastructure. Currently, there are no commercial suppliers committed to building solutions for high-volume manufacturing (HVM) mask blank inspection, mask defect inspection, and patterned inspection. He estimated the costs to fund each effort at >$50M for the first two, and >$100M for the last category. These HVM solutions will be needed by 2013.

SEMATECH is taking on the fundraising task for these HVM solutions by forming an international consortium to obtain funding from a variety of public and private sources: governments, suppliers, semiconductor manufacturers, and other research consortia. A workshop held at SEMICON West will discuss the funding problem. Additionally, SEMATECH has committed most of its lithography budget to mask infrastructure over the next four years.

The inspection tools available today are primarily aimed at 32nm, noted Rice, and SEMATECH has those tools available, but moving toward the 22nm hp the gaps in EUV inspection tools become apparent. To address the short-term need for a pilot line (by 2011), “SEMATECH is funding a supplier to build an optical substrate inspection (at-wavelength) tool,” said Rice. The same goes for an aerial image tool (at wavelength) for defect review, he noted. — D.V.


Mask infrastructure gaps. (Source: SEMATECH)

April 27, 2009 – Extending work with EUV and SRAMs from last summer’s 32nm achievement, European R&D consortium IMEC now says it has developed the “world’s first” functional 22nm CMOS SRAM cells made using EUV lithography, including the first metal layer.

Results presented at last year’s SEMICON West only used EUV to print the contact holes in 32nm SRAMs; now IMEC used an ASML EUV alpha tool to pattern both the contact (~45nm size) and metal-1 layer (60nm width, 46nm spaces). Overlay performance is “good,” IMEC said, adding that a single-patterning approach “further strengthens the case for EUV as a cost-effective solution.”

The cells, made with FinFETs, have a density of 0.099μm2, 47% smaller than the 32nm cell reported last year. For the FEOL process IMEC used a high-k/metal gate (HK+MG) FinFET platform: HfO2 dielectric, TiN as the metal gate, and NiPt for the source/drain. Minimum active FIN pitch is 90nm. FinFET layers were printed using ASML’s 1900i immersion litho tools, with metallization of contact holes done with Applied Materials contact processing modules for inter-layer barrier Ti and TiN before tungsten fill and chemical mechanical polishing. The work also was supported by research and on-site participants from IDMs, foundries, and equipment and materials suppliers, as well as support and funding from the EC program PULLNANO.


Figure 1. The ASML EUV tool at IMEC. (Source: IMEC)

“This SRAM cell integration shows that EUV photo process technology is making excellent progress as a cost-effective single patterning approach. We believe that EUV remains a candidate for use in the later stages of the 22nm technology.”

Editor’s Take:

In an e-mail exchange, IMEC researchers offered more specifics on the progress made to create the 22nm SRAMs with EUV. Resolution has improved from 35-40nm down to 25-30nm in the past six months, and line-edge roughness (LER) has moved from 5-6nm down to 4nm, with resist sensitivities of around 15-20mJ/cm2 “quite common now.” The goal of 22nm resolution will require more development in optics toward higher NA and off-axis illumination, though, capabilities not present on the current ASML alpha tool — but which they promise will be in the preproduction tools due in 2010. Target resist sensitivity of 10mJ/cm2 “seems achievable in time,” they add.

Two big sticking points for EUV development still need work: optics and resists (and the associated problem of LER). For optics, Zeiss is working “full-speed” and “many mirrors have been polished for the preproduction tools,” IMEC noted.

For resists, IMEC says “steady progress is being made.” Chemically amplified resists are required to strengthen the relatively weak EUV illumination, but balancing sensitivity, LER, and resolution needs has proven tricky. “Many different resist chemistries are being explored today to overcome these limitations but will need time to mature,” IMEC told SST.


Figure 2./B> 22nm SRAM array after metal-1 patterning (with EUV litho) and etch. (Source: IMEC)

The biggest problem is LER, which needs to be <2nm, well below the 4-5nm reported here (and the 5-6nm by SEMATECH/Albany which also has printed 22nm lines using an EUV microstepper). IMEC told SST that smoothing the resist lines as a post processing step may be required, and it is investigating this.

Perhaps more than anything, IMEC urges, the newest 22nm results should be viewed as a way to “strengthen the confidence of the industry that EUV will become the choice for 22nm and beyond,” and thus spur more investments to develop and ready the required infrastructure. — J.M., D.V.

By Hank Hogan

It wasn’t springtime but this year’s SEMICON West was nonetheless green. The signs included a push toward recycling, conservation, and solar power. The latter was especially evident, since Intersolar North America ran concurrently with SEMICON West for the first time this year. Intersolar took over the third floor of one hall while SEMICON West sprawled across the rest of San Francisco’s Moscone Center.

Of course, all of these green trends were driven by a desire for that other form of green. During a panel discussion at the beginning of the show, Paula Mints, principal analyst for the photovoltaic service market research program at Navigant Consulting (Palo Alto, CA), pointed out that the solar industry has been expanding rapidly for a long time. “The photovoltaic industry has grown at a compound annual growth rate of 34 percent for the past 30 years,” she announced.

That trend should continue for years to come. The photovoltaic market is in the tens of billions of dollars but only accounts for a fraction of a percent of the electricity generated worldwide.

The potential of solar is attracting attention. Applied Materials formed a business unit to service the industry, but it’s not the only company to do so. Air Liquide, for example, has ALUX, a range of turnkey offerings that includes supply and purification of materials, as well as abatement of waste. It’s all intended to help photovoltaic manufacturers scale up production, and the suite of services includes those designed to boost module efficiency and yield.

“We also can do failure analysis to pinpoint component problems,” said Hugh Gotts, director of research and development of Air Liquide

by Debra Vogler, Senior Technical Editor, Solid State Technology

August 28, 2008 – USJ formation at 32nm was the focus of the West Coast Junction Technology Group’s meeting on the final morning of this year’s SEMICON West. But many presenters also discussed what lies ahead at the 22nm node. Ultratech’s Jeff Hebb, VP of product marketing, and chairman/president/CEO Art Zafiropoulo provided additional insight to SST about the company’s WCJTG talk on laser spike annealing.

The basic theory of LSA operation is the use of a long-wavelength, p-polarized “line beam” incident on a wafer at Brewster’s angle (to minimize pattern effects). The wafer is scanned under the beam — dwell time determined by the stage speed — and real-time peak temperature measurement is done with a feedback loop to the laser. “We come in at a certain angle and polarization that makes the wafer very uniform to the laser,” noted Hebb. “That allows us to do these processes without using any coatings or absorber layers, and with the LSA system, you can vary the dwell time easily and go to low dwell times.”

Pattern effects using LSA have been debated for some time. Hebb presented data illustrating the suppression of pattern effects using LSA (see Figs. 1-2), and how P-polarization and the Brewster angle make cross-die absorptivity uniform to ~1%.

Fig. 1: Suppression of pattern effects using LSA. The long wavelength (10.6μm) is much greater than the length scale of devices and films (100nm). (Source: Ultratech, WCJTG)
Click here for full-size image

Fig. 2: Measured reflectance of real die confirm suppression of pattern effects for LSA, enabling higher peak temperatures and increased device gain. (Source: Ultratech, WCJTG)
Click here for full-size image

As far as extending LSA to 32nm and beyond, the company looked at a number of options including high-k/metal gate (HK+MG), FinFETs, and stress techniques. For example, with stress techniques (SiGe in particular), “going to the low dwell time is critical so you don’t end up with excessive wafer warpage or stress defects,” said Hebb. “And we also looked at HK+MG and showed how pattern independence holds true — it still works for HK+MG integration schemes.” He added that an IBM paper presented at this year’s VLSI Symposium showed that LSA didn’t have negative effects (see Fig. 3).

Of particular interest in Fig. 3 is the notation that the data refers to IBM’s gate first process, an approach Zafiropoulo said was “very extendible.” He also believes that, although Intel has proven it can make a gate-last approach work, it will be “extremely difficult, if not close to impossible” for other chipmakers to make gate-last a production technology. “We think IBM’s approach of gate-first is probably the way the world should go — and will go,” he said.

Fig. 3: 32nm low-power transistor with high-k/metal gate (Hf-based high-k/single-metal gate-first process) shows LSA is compatible with HK+MG process at 32nm. LSA is used for USJ with no negative impact and only <3% total added cost. (Source: IBM Alliance, VLSI Symposium 2008)

Also referenced by Hebb at the WCJTG meeting were recent papers by Freescale Semiconductor in which LSA was used to do a high-k annealing to improve the properties of a dielectric. Extending beyond 32nm with alternate device structures, Hebb said that good results were already demonstrated with ultrathin SOI, “so we think there shouldn’t be any issues with FinFETs. We think LSA is easily extendible to 32nm.”

The work Hebb presented at the WTJCG meeting was entirely focused on sub-melt LSA — i.e., the temperature is kept below the melting point of silicon — and this technology is likely going to be used all the way down to 22nm. However, according to Zafiropoulo, there may come a time when the industry will need an LSA process that occurs at a higher temperature, as high as the melting point of silicon. “We have the melt technology running in our alpha systems in our lab today,” he said, noting that a few customers have used that system. “Based on what we have been told, we think melt technology will be useful below 22nm.” As an aside, Zafiropoulo told SST that the company delivered a production system for melt-LSA to a US government agency back in 1996 — and even though a system implementing melt technology today would be different, he maintains that the company understands that technology very well should it ever be needed.

Regarding the market outlook for LSA, Zafiropoulo told SST that usage at the 65nm node is growing, with the company having penetrated 16 of the top 18 companies in the logic sector, many of which have moved into production this year. And the company is seeing an even larger transition from development to production at 45nm; he anticipates that in 2009 the company will see a sharper increase in 45nm orders. — D.V.