Category Archives: Semicon West

BlueShift shifts gears


August 7, 2007

by Ed Korczynski, Senior Technical Editor

BlueShift Technologies, the startup led by former Brooks Automation execs that decloaked from stealth-mode a year ago with support from Intel’s VC arm, is now confidently touting its business model combining modular hardware and software, with a handful of shipments now to show for its efforts.

Besides claiming throughput and cost advantages for certain applications, the company’s QuickLink linear vacuum handling systems are modular for rapid delivery. For example, the vacuum robot has four major sub-assemblies and approximately 20 parts total, so it can be assembled in 30 minutes. “You don’t have to engineer to build your system, you configure,” said Marty Petraitis, VP of sales and marketing. The result is 4-week lead times.

The software architecture is likewise modular in terms of I/O, memory management, and threading, so customers can configure custom handling in <30 minutes. Modules can be configured with integrated metrology and in-situ particle-removal -- an example of the latter is "nanodroplet" kinetic cleaning technology from EHD, which was shown on the floor at this year's SEMICON West.

Smaller original equipment manufacturers (OEM) can gain much faster time-to-market for their vacuum-based thin-film PVD, CVD, and etch chambers by using BlueShift for the vacuum robotics, the company claims. “We’ve been able to get these guys into their first alpha- and beta-tools within three months,” informed Petraitis.

The first customer is an OEM, and three linear modular vacuum systems have been shipped since May of this year with a fourth to be shipped by end of August, all going into multiple DRAM fabs of one Korean IDM, Petraitis told WaferNEWS. In principle, an IDM could choose BlueShift as the backbone of a multi-station system using different process chambers from different OEMs.

PARTICLES


August 1, 2007

compiled by Carrie Meadows

Cymer signs EUV supply agreement with ASML
At SEMICON West 2007, Cymer, Inc., which provides excimer laser light sources used in semiconductor manufacturing, announced its selection by ASML Holding NV as the extreme ultraviolet (EUV) source supplier for the lithography systems vendor’s EUV scanners. The multi-year, multi-unit EUV source agreement has the first shipment scheduled for late 2008.

Pharma software gets set to go wireless

Software provider Pharmacy OneSource, Inc. has partnered with FreshLoc Technologies and its national distributor WTH Healthcare Networks to interface the FreshLoc wireless environmental monitoring sensors for temperature-sensitive processes with Simplifi 797, a web-based application for tracking USP Chapter <797> compliance. “Most pharmacists see collecting temperature and humidity values as critical to safety and quality in sterile compounding, yet would much rather have it done automatically and wirelessly,” says Keith Streckenbach, executive vice president of Pharmacy OneSource.

NQA closes certification acquisition

Leading ISO 9001, ISO 14001, TS 16949, and AS9100 registrar National Quality Assurance, USA (NQA), a joint venture company of National Technical Systems, Inc., has acquired TRA Certification, an Elkhart, IN-based ISO certification organization. Terms of the transaction were not disclosed.

Teamsters support protection from diacetyl exposure

The Teamsters Union is supporting legislation introduced by Rep. Lynn Woolsey (D-CA) that will compel OSHA to take immediate action to protect food-processing workers from exposure to diacetyl, a chemical that has been link to a form of irreversible lung disease, commonly referred to as “popcorn lung” due to the chemical being used in the artificial flavoring in microwave popcorn. The legislation would require OSHA to issue an interim final standard within 90 days of its introduction to minimize exposure to diacetyl. A final rule would need to be issued within two years covering all workplaces where workers are exposed to this chemical.

In video interviews at SEMICON West, Dave Gross of AMD pleads AMD’s case for collaboration to maximize the effectiveness of R&D dollars. Alain Diebold (U. at Albany) summarizes unresolved metrology issues at 45nm and discusses the future at 32nm. And John Allgair (ISMI assignee from AMD) outlines the group’s current plans as it gears up for a larger presence in Albany and expand its metrology program — look for intentional defect array wafers to be ready for mass production in 2-3 months.

Dave Gross, director, global manufacturing systems technology, 300mm engineering, AMD
– CLICK HERE for the 300kbps version
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– (SEE ALSO: SEMICON WEST REPORT: Do lean principles apply to semi manufacturing?)


Alain Diebold, Empire Innovation Professor of Nanoscale Science, College of Nanoscale Science and Engineering, U. at Albany
– CLICK HERE for the 300kbps version
– CLICK HERE for the 100kbps version


John Allgair, metrology program manager, AMD assignee to the International SEMATECH Manufacturing Initiative (ISMI)
– CLICK HERE for the 300kbps version
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– More “SST on the Scene” video interviews from SEMICON West…

by Ed Korczynski, Senior Technical Editor

With High-k (HK) dielectrics and metal-gates (MG) now being ramped into CMOS production at Intel and IBM, much of the excitement at this year’s SEMICON West centered around manufacturing technologies needed for these new materials. Much of the discussions in equipment supplier-sponsored seminars and panels centered on the challenges of working with these new materials — particularly the tricky setup of affordable in-line metrology for these new ultra-thin materials.

Aida Jebens, Senior Economist at VLSI Research, reviews her firm’s industry weather forecast for SST On the Scene, which shows a “cooling” and cloudy outlook for display equipment and “flat” for chip tools, though next year’s forecast looks to be improved. She also shares thoughts on the renewed debate over a 450mm wafer-size transition, and what has to happen on all sides to pull through — and what’s already being done.

– CLICK HERE for the 100kbps version

– CLICK HERE for the 300kbps version

by Debra Vogler, senior technical editor

A few weeks ago, before the bustle of SEMICON West, Silterra announced an extension of its JDP with IMEC to create a foundry-compatible 90nm CMOS process technology, with the intent to further scale to 65nm. A 110nm derivative will also be developed in parallel. A 130nm process, the fruit of a previous joint effort, is already in production at Silterra. WaferNEWS caught up with Silterra president and COO, Tzu Yin Chiu, to get the latest on the foundry’s plans.

SEE ALSO:
– IMEC looks to the future
– IMEC extends 3D system integration program
– IMEC updates 32nm litho progress

“Our goal is to have the 110nm node, which is a cost-reduction version of the 130nm process, ready for pilot production by mid-2008,” said Chiu. “It will be followed by the 90nm process in the second half of the year and the 65nm technology a couple of years after that.”

At the present time, the foundry sees the sweet spot for its business at the nodes between 180nm and 130nm, although Chiu added that customers are starting to shift to the more advanced nodes.

When asked to consider the possibility that the industry’s drive to consolidate will start hitting the smaller foundries, Chiu predicted that there will be winners in the second tier as well. “The winners will be those with the right customer set, the ability to follow technology, and who can provide a complete IP offering,” said Chiu. “The smaller foundries will look for partners with complementary strengths.”

WaferNEWS also caught up with IMEC’s VP of business development, Ludo Deferm, about the competitive landscape that foundries large and small will face going forward. Deferm believes that the smaller foundries will have to make strategic alliances with either smaller IDMs or with the large foundries, where they can offer capabilities that the larger foundries do not want to offer. “Going forward

By Bob Haavind, editorial director, Solid State Technology

3D chip packaging with through-silicon vias (TSVs) will transform the industry over the next 3–5 years, based on presentations and discussions at SEMICON West. Using TSVs could enable compact packaging with increased performance.

By Fran&#231oise von Trapp, managing editor, Advanced Packaging

Material science has a firm foothold in the future of advanced packaging. At SEMICON West’s Wednesday, July 18, Packaging Materials Trends TechXPOT, sponsored by IMAPS, industry experts shared insights and developments in packaging materials, their applications, and how these innovations will help device packaging address functionality, form factor, and reliability challenges.

by Phil LoPiccolo, Editor-in-Chief, Solid State Technology

A pair of Wednesday keynotes at SEMICON West described opportunities for semiconductor suppliers in the solar energy market, but cautioned that there are fundamentally different manufacturing requirements in the two industries.

Solar energy accounts for a paltry 1/30th of 1% of total annual electricity consumption in the US, and currently lags far behind the global leaders in total solar power produced annually (Germany >50%, Japan ~25%, US 9%), noted Rhone Resch, president of the Solar Energy Industries Association. But the US has the best “resources” of any developed country in terms of amount and intensity of available sunlight, he noted, and is keen to find independent energy sources. Plus the federal government is stepping in with a more aggressive promotion of solar energy, and enacting policies to help jumpstart industry efforts to reduce costs.

Taking all these factors into account, Resch projects US solar demand will ride an 83% CAGR through 2010. And that’s a tremendous opportunity for semiconductor suppliers to provide first-, second-, and third-generation equipment to help the solar industry maintain that pace, he said.

For those hoping to tap into the nascent solar growth, T.J. Rodgers, chairman of SunPower Corp and president/CEO of Cypress Semiconductor (from which SunPower was spun out in 2002), emphasized in a separate keynote the vast differences between how silicon plants for solar and semiconductor fabs operate. While solar cell plants are far less stringent in terms of individual processes (e.g., lithography diffusion, etching, metallization, etc.) than present-day semiconductor fabs, he explained, they also need equipment that’s more reliable in a high-throughput, 24/7 environment (minimum ~99.8% uptime) and is 10x cheaper and faster — i.e., tools that cost, say, $400k instead of $4M, and achieve 800 wafers/hr throughput, not 80 wafers/hr. Solar fabs also run a more continuous-flow manufacturing setup than a semiconductor fab, and process a lot more silicon, he noted.

As an example, Rodgers pointed to SunPower’s “mega-monster fab” in the Philippines, which boasts output capability of 100M watts/year, or about 32M wafers/year, vs. a large semiconductor plant that may produce about 1M wafers/year, he said. The site also consumes about 15 tons of silicon per week, which is nearly 800 tons per year. — P.L.