Category Archives: Semicon West

July 12, 2004 — SEMICON West opens today in San Francisco with Steven R. Appleton, chairman, CEO, and president of Micron Technology, presenting a keynote presentation as planned, reports SEMI.

Other SEMICON West keynoters include Dr. Paolo A. Gargini of Intel, Dr. Aart J. de Geus of Synopsys, and Bruce Freyman, president and COO, Amkor Technology.

SEMICON West runs through July 16, 2004. The expo opens at the Moscone Center with the Wafer Processing segments, July 12-14, and continues at the San Jose Convention Center with Final Manufacturing programs and exhibits, July 14-16.

The event will feature more than 1500 exhibitors in 3700 booths and include an array of technical programs, prominent keynote speakers, standards meetings and other events.

Von Pierer has served as Siemens’ CEO since 1992, and will assume the role of supervisory board chairman once Kleinfeld takes the reins. The company didn’t give a reason for this move, except to state that “Siemens has begun a generation change in the company’s top management.”

(July 9, 2004) San Francisco, Calif.&#8212At SEMICON West 2004, Mexican Secretary of the Economy Fernando Canales Clariond, Baja California Governor Eugenio Elorduy Walther, and developers will discuss their plans to create a 10,000-acre industrial park for the high-tech industry along the shared border between Mexico and the United States.

(June 30, 2004) San Francisco, Calif.&#8212Attendees of the 2004 SEMICON West exposition now have the option of attending a panel discussion about the migration to 65nm including IP ownership and new models of collaboration. The panel consists of top industry technologists such as Bill Rozich of IBM, Mendi Moussavi of LETI, LaMar Hill of Albany Nanotech, Mark Pinto of Applied Materials and Mark McClear of Dow Chemical.

(Business Wire, June 28, 2004) Buffalo, N.Y.&#8212NanoDynamics, Inc., a manufacturer of nanomaterials, today announced that Dr. Alan Rae has joined the company as vice president of market and business development. In this role, Dr. Rae will manage the ND innovations strategic business unit and will be responsible for developing business opportunities for commercial products.

May 28, 2004 — Due to expanded facilities at San Francisco’s Moscone Center, the front-end and final manufacturing segments of Semicon West will be reunited in San Francisco next year, according to Semi, the organization that runs the event.

In recent years, the annual semiconductor manufacturing technology show has spanned two cities (San Francisco and San Jose, CA) in order to accommodate the demand for exhibit space, meeting rooms and technical programs.

Moscone West added 300,000 sq. ft. of exhibit space to the existing 600,000 sq. ft. in Moscone North and South Halls last year. With the additional facility, available space exceeds historic exposition requirements and provides room for growth.

Vicki Hadfield, president of SEMI North America, said: “The San Jose venue provided an efficient and hospitable interim solution. However, it was never desirable to host a split event. Reuniting Semicon West allows attendees to visit a single integrated venue and use their time more productively. It also provides exhibitors with access to a concentrated community of attendees.”

Semicon West 2005 will maintain exhibit segmentation. Final Manufacturing will be located in the new Moscone West facility, which will also house exposition keynotes and technical programs on the third floor. Wafer Processing will remain in the North, South, and Gateway Halls.

Semicon West 2005 events will span the week of July 11-15, 2005, with the product exhibition occurring from July 12-14.

May 24, 2004 – Semiconductor Equipment and Materials International (SEMI) officials are looking at numerous ways to add value to the SEMICON shows, including the possibility of re-unifying SEMICON West under one roof.

“Moscone added a new building, Moscone West, that brings space up in San Francisco fundamentally equivalent to what we’ve been using in San Jose,” Dan Martin, SEMI COO, told WaferNews in an exclusive interview. “[We’re considering] consolidating the show in San Francisco. We’ve been looking at that very, very closely.” The show’s growth forced SEMI to split it into two parts in 1997. SEMI has contracts to use the San Jose Convention Center through 2005, and would face penalties if it backs out.

Martin couldn’t comment on when, or even if, the show would re-unify. “We are very, very close to a high percentage probability that we’re going to make that decision to unify backend and frontend very soon,” said Martin. “We’ve done a lot of research on this, and we’ve received overwhelming support for doing this.”

Several member company executives also spoke to WaferNews, most noting an industry-wide perceived need to at least tweak the shows. The concept of a single flagship show featuring both frontend and backend companies would doubtless make a lot of member companies happy.

“I hope we’re in touch with our members to the extent that we hear it all, and I think we are,” said Martin. “Fundamentally, our expositions are extremely important to our members; that’s demonstrated by their continued participation.”

Martin added that SEMI understands that exhibitors care greatly that they get a return for the investment in the SEMICON shows. “That’s a key, high-level issue that we hear a lot about,” he said. “We care very, very dearly about making sure we’ve got the appropriate value proposition for our member companies and our exhibitors.”

Martin said SEMI is trying to tweak the shows with three strategic goals in mind. First, they’re trying to increase the value of the event for both exhibitors and attendees. SEMI also is opening the shows up to a participation model, where even companies that aren’t exhibiting can get value from the shows. In addition, they’re trying to reduce costs, in part by working with their global contractors to drive down their costs, ideally passing those savings onto member companies.

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When will the U.S. economy recover? According to Klaus-Dieter Rinnen, the managing vice president at Gartner, it will happen “when we least expect it.” In 2003, the economy will improve, though back-end-loaded. In electronic assembly equipment, we should expect a gradually improving phased recovery. Look for corporate spending to return in 2003.

Newcastle upon Tyne, U.K.&#8212Gold is used extensively in the electronics industry as a relatively stable conductor of electricity for products such as computers, mobile phones and smart cards, with one great drawback&#8212it’s one of the most expensive metals on the market.

Tessera 3-D Symposium Demonstrates Greater Supply Chain Cooperation, Advanced Packaging Media Sponsor

SAN JOSE, CALIF.
Driven largely by the wireless handset market and emerging high-performance computing requirements, the semiconductor industry is increasingly looking to advanced packaging solutions as a means of achieving the reductions in package height, area and cost needed to sustain electronic product innovation. However, some key challenges associated with integration and industry-wide collaboration must also be addressed. These themes, along with some proposed solutions, emerged during Tessera Inc.’s 3-D Packaging Symposium at SEMICON West.

More than 100 technologists and executives attended the event, held at the Fairmont Hotel in San Jose. Experts from throughout the semiconductor supply chain &#8212 including chip manufacturing, packaging, materials, EMS and assembly leaders &#8212 covered topics ranging from the global outlook for 3-D packaging to focused discussions on materials, reliability, wireless integration and memory densification.

In his welcome and introduction, Tessera’s chairman and CEO, Bruce McWilliams, set the tone for the Symposium by examining the value proposition 3-D packaging technologies provide to the industry, namely increased miniaturization, performance and ultimately lower cost. To illustrate this point, he pointed out that the volume of functional silicon in one supercomputer rack takes up approximately 1 cubic centimeter of space &#8212 most of the rest of the floor-to-ceiling rack is comprised of various levels of packaging and interconnect. Advanced 3-D packaging technologies can not only dramatically reduce the size of electronic products ranging from super computers to cellular handsets, but also improve performance and lower cost. McWilliams noted that intensified cooperation throughout the supply chain is needed to realize 3-D package advantages, which can be applied to a broad range of consumer electronic products.

Keynote speaker Jan Vardaman, president of technology consulting firm TechSearch International, provided a global perspective on 3-D packaging applications. Driven in large part by wireless applications, the industry is shifting its focus to 3-D packages, which demand higher functionality in a small space, particularly in the case of mobile phones. Handset makers from around the world, including the U.S., Europe, Japan and China, are increasingly using both die stacking and package stacking to meet feature and size requirements. While broader adoption and resolution of cost issues depends on solving several key problems, such as addressing the known-good-die (KGD) problem and optimizing wafer/die-thinning technologies, Vardaman concluded that “3-D packaging has arrived.”

According to Catherine de Villeneuve, Tessera’s director of RF markets, wireless handsets, which are now integrating voice and data with more advanced features such as digital cameras, MP3 players, wireless gaming, GPS and other functions, accounted for 82 percent of multi-chip packages shipped in 2002. As was the case with CSPs, the cost-sensitive handset market is once again driving the need for advancement in packaging technology to accommodate added functionality in compact form factors. An area gaining increased attention involves optimizing the integration of passive functions at various levels, including chip, package and board.

A noteworthy trend in cell phone integration is the emergence of IC, package and radio module integration. For every new function incorporated into wireless handsets, said Glenn Raskin, a member of the technical staff of Motorola’s Wireless and Broadband Systems Group, the industry mantra should be: “integrate, optimize, eliminate” where possible. Following this process to determine where components, process steps, packaging area, etc., can be eliminated is key to optimizing miniaturization and functionality, at the lowest possible cost.

Mike Steidl, vice president of advanced product development at Amkor, pointed out that package stacking can now provide multi-sourcing flexibility and address the KGD problem by allowing individual devices to be tested prior to stacking. The die stacking approach, on the other hand, also provides important benefits, such as small size, low package profile, and low cost. The question of when to die-stack versus when to package-stack should be evaluated and modeled based on customer requirements. This sentiment was also expressed by Tessera’s Jeffrey Demmin, director of product marketing, who also noted that die stacking can be the solution of choice for high yielding devices available as bare die, whereas packaging stacking is the solution of choice when combining higher and lower yielding devices, or in a scenario where particular ICs require burn-in.

Stacked CSP Trends

Stacked CSP technology was cited as critical to the future of several device types, particularly accelerating the availability of next generation double-data-rate (DDR) DRAMs. Sunny Khang, technical marketing manager for Hynix Semiconductor, commented that stacking can provide successive windows of opportunity, offering levels of integration promised in future generations of memory chips, before a sweet spot of high volume production is reached at the next level of IC integration.

Also noting the rise of stacked CSPs was Steve Greathouse, program manager at Intel, who estimated the total available market for the technology will reach over 8 billion dollars in shipments by 2007. With memory and computing requirements being driven higher, stacking technology provides an optimum solution to augment functionality when space is limited.

At the end of the day, presenters echoed the sentiment that cost and size are of paramount importance, and concurred that elevated dialogue and cooperation is needed throughout the industry to accelerate implementation. Such collaboration between system manufacturers, chipmakers, EMS providers and assemblers &#8212 as well as among competitors &#8212 will be crucial to achieving the goals and promise of increased system-level integration enabled by 3-D packaging technologies.

Copies of the proceedings are available for $50.00 by contacting Daryl Larsen, symposium event manager, at (408) 952-4364, or [email protected].

K&S Announces a Volume Purchase Agreement with National Semiconductor
BY GAIL FLOWER

Flip Chip Bonder
Assembl&#233on’s D9 has a low-maintenance linear motor H-drive gantry coupled with a modular, open architecture, and can handle up to 75 die from myriad media. A direct drive, closed-loop Z-axis design provides consistent bond line thickness and the ability to stack die. In addition, the same system affords a programmable placement force from 90 to 4,000 gf, with selectable placement forces down to 6 gf. According to company claims, it has a flip chip throughput rate of 2,700 cph with 9 &#181m @ 3 sigma and a 3 ppm placement yield.
Assembl&#233on

Eutectic Die Bonder
The Palomar Technologies Model 6500 Precision Eutectic Die Bonder provides a high accuracy, high-throughput solution for hybrid assembly. With a footprint of only 38 x 48″, the 6500 takes up less than half of the cleanroom space of comparable equipment. A 6 x 12″ work area eliminates the need for additional bond heads to feed and preposition die in the work area. The 6500 moves quickly using high-speed linear motors on an air-bearing table. The rigidity and speed of this positioning system enable post-process accuracy of better than 1.5 &#181m at 3 sigma at cycle times of less than seven seconds per pick/place operation. A 6-position, bidirectional tool turret maximizes flexibility and throughput by changing pick tools “on the fly” rather than using a tool docking/ undocking system. The 6500 uses Palomar’s award-winning pulse heat control system with rapid heating rates of more than 100&#176C per second, with control within 2&#176C through the entire eutectic cycle. For maximum flexibility, the 6500 allows die presentation from wafer die feeders, waffle packs, gel packs and automated waffle pack loaders.
Palomar Technologies

Semiconductor Companies Take Center Stage at Advanced Packaging Award Program
SAN JOSE, CALIF.
On Wednesday, July 16, Advanced Packaging magazine honored top supplier companies and their staffs with the 2003 Advanced Packaging Awards at a ceremony held here at the McEnery Convention Center.

8:00 a.m.-5:00 p.m.
Semiconductor Processing Technology (Day 3)
San Jose Marriott Hotel, San Jose

8:30 a.m.-10:30 p.m.
Equipment and Materials Market Briefing
San Jose Marriott Hotel, San Jose

8:30 a.m.-12:30 p.m.
TFT-LCD Manufacturing Conference
San Jose Marriott Hotel, San Jose

8:30 a.m.-4:30 p.m.
SECS/GEM Maps and Trace Standards for Assembly Test (Day 1)
San Jose Marriott Hotel, San Jose

8:30 a.m.-5:00 p.m.
Fab Managers Forum
(at National Semiconductor, Sunnyvale, Calif.)

9:00 a.m.-6:00 p.m.
STS: IEMT (Day 2)
San Jose Marriott Hotel, San Jose

1:00 p.m.-5:00 p.m.
OLED Manufacturing Conference
San Jose Marriott Hotel, San Jose

The following are press conferences and educational sessions that will be held at SEMICON West in San Jose, Calif. on July 18, 2003. To check for availability of these courses or others, or to register online at SEMI’s Web site. Registration for programs/events includes free admission to the exposition.