Tag Archives: 193nm

Patterning with Films and Chemicals

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Somewhere around 40nm is the limit on the smallest half-pitch feature that can be formed with a single-exposure of 193-nm wavelength laser light using water immersion (193i) lithography. While multiple-patterning (MP) is needed to achieve tighter half-pitches, smaller features at the same pitch can be formed using technology extensions of 193i. “Chemistry is key player in lithography process,” is the title of a short video presentation by Dow Electronic Materials corporate fellow Peter Trefonas now hosted on the SPIE website (DOI: 10.1117/2.201608.02).

Trefonas as been working on chemistries for lithography for decades, including photoresists, antireflectant coatings, underlayers, developers, ancillary products, and environmentally safer green products. He is an inventor on 61 US patents, has over 25 additional published active U.S. patent applications, is an author of 99 journal and technical publications, and is a recipient of the 2014 ACS Heroes of Chemistry Award and the 2013 SPIE C. Grant Willson Best Paper Award in Patterning Materials and Processes. Now a Senior Member of SPIE, he earned his Ph.D. in inorganic chemistry with Prof. Robert West at the University of Wisconsin-Madison in 1985.

Trefonas explains how traditional Chemically-Amplified (CA) resists are engineered with Photo-Acid Generators (PAG) to balance the properties for advanced lithography. However, in recent years the ~40-nm half-pitch resolution limit has been extended with chemistries to shrink contact holes, smooth line-width roughness, and to do frequency-multiplication using Directed Self-Assembly (DSA). All of these resolution extension technologies rely upon chemistry to create the final desired pattern fidelity.

—E.K.

ASML Books Production EUV Orders

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TSMC commits to two tools for delivery next year

Maybe, just maybe, ASML Holding N.V. (ASML) has made the near-impossible a reality by creating a cost-effective Extreme Ultra-Violet (EUV @ ~13.5nm wavelength) all-reflective lithographic tool. The company has announced that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has ordered two NXE:3350B EUV systems for delivery in 2015 with the intention to use those systems in production. In addition, two NXE:3300B systems already delivered to TSMC will be upgraded to NXE:3350B performance. While costs and throughputs are conspicuously not-mentioned, this is still an important step for the industry.
Perhaps acquiring Cymer to get the source-technology in-house for tighter integration was important. Perhaps evolutionary improvements crept along by tough engineering rigor. Perhaps the industry got lucky. One way or the other, ASML has had the goal of delivering not just hardware but functional uptime/availability using very complex EUV technology, and now it seems to be on the cusp of making it happen. The company claims that current EUV tools are available 50% of the time, at unspecified source power levels.
At its Investor Day in London today, ASML outlined its expected opportunity to grow net sales to about EUR 10 billion and to triple earnings per share by 2020, an indication of the confidence the company has in its technology and employees. Much of the growth will be in Deep-UV immersion tools, and in so-called “Holistic Lithography” products to deliver advanced correction capabilities. An example of Holistic Litho is Source-Mask-Optimization (SMO) that can be used for triple-patterning of a 48nm minimum pitch metal layer using DUV immersion in a Litho-Etch-Litho-Etch-Litho-Etch (LELELE) flow, such that the Depth-of-Focus (DoF) can be increased from 70 to 86nm. Holistic EUV means that SMO can reduce the dose required to get 120nm DoF from 46 to 20 mJ/cm2 for a 45nm minimum pitch metal layer.
The presentations can be found at the company’s website.
— E. K.

Moore’s Law is Dead – (Part 3) Where?

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…we reach the atomic limits of device scaling.

At ~4nm pitch we run out of room “at the bottom,” after patterning costs explode at 45nm pitch.

Lead bongo player of physics Richard Feynman famously said, “There’s plenty of room at the bottom,” and in 1959 when the IC was invented a semiconductor device was composed of billions of atoms so it seemed that it would always be so. Today, however, we can see the atomic limits of miniaturization on the horizon, and we can start to imagine the smallest possible functioning electronic device.

Today’s leading edge ICs are made using “22nm node” fab technology where the smallest lithographically defined structure—likely a transistor gate—is just 22nm across. However, the pitch between such transistors is ~120nm, because we are already dealing with the resolution limits of lithography using water-immersion 193nm with off-axis-illumination through phase-shift masks. Even if a “next-generation” lithography (NGL) technology were proven cost-effective in manufacturing— perhaps EbDW for guidelines combined with DSA for feature fill and EUV for trim—we still must control individual atoms.

We may have confidence in shrinking to 62nm pitch for a 4x increase in density. We may even be optimistic that we can shrink further to a 41nm pitch for a ~10x increase in density…but that’s nearing the atomic limits of variability. There are many hypothesized nanoscale devices which could succeed silicon CMOS in IC, but one commonality of all devices is that they will have to be electrically connected. Therefore, we can simplify our consideration of the atomic limits of device scaling by focusing on the smallest possible interconnect.

4nmPitchDevice_TheorySo what is the smallest possible electrical interconnect? So far it would be a Single-Walled Carbon NanoTube (SWCNT) doped with metals to be conducting. The minimum diameter of a SWCNT happens to be 0.4nm, but that was found inside another CNT and the minimum repeatable diameter for a stand-alone SWCNT is ~1nm. So if we need three contacts to a device then the smallest device we can build with atoms would be a 3nm diameter quantum dot. As shown in the figure at right, if we examine a plan-view of such a device we can just fit three 1nm diameter contacts within the area.

Our magical device will have to be electrically isolated and so some manner of dielectric will be needed with some minimal number of atoms. Atomic Layer Deposition (ALD) of alumina has been proven in very tight geometries, and 3 atomic layers of alumina takes up ~1nm so we can assume that spacing between devices. A rectangular array would then result in ~16nm2 as the smallest possible 3-terminal device that can be built on the surface of planet Earth.

Note that a SWCNT of ~1 nm diameter theoretically could carry ~25 microAmps across an estimated 5kOhm internal resistance [(ECS Transactions, 3 (2) 441-448 (2006)]. I will leave it to someone with a stronger device physics background to comment as to the suitability of such contacts for useful circuitry. However, from a manufacturing perspective, to ensure electrical contacts to billions of nanoscale devices we generally use redundant structures, and doubling the number of SWCNT contacts to a 3-terminal device would call for ~8 nm pitch.

However, before we reach the 4-8nm pitch theoretical limits of device scaling, we will reach relative economic limits of scaling just one device feature such as a transistor gate. Recall that there are just 22 silicon atoms (assuming silicon crystal lattice spacing of ~0.3nm) across a ~7nm line, and every atom counts in controlling device parameters. Imec’s Aaron Thean recently provided an excellent overview of scaled finFET technologies, and though the work does not look at packing density we can draw some general trends. If we assume 41nm pitch and double fins with 20nm gate length then each device would use ~1,600 nm2.

Where are we now? Let us consider traditional 6-transistor (6T) SRAM cells built using “22nm node” logic process flows to have minimal area of ~100,000 nm2 or ~16,000 nm2 per transistor. At IEDM2013 (9.1), TSMC announced a “16nm node” 6T SRAM with ~70,000 nm2 area or ~10,000 nm2 per transistor.

IBM recently announced that 6 parallel 30nm long SWCNT spaced 8nm apart will be developed as transistors for ICs by the year 2020. Such an array would use up ~1440 nm2 of area. Again, this is at best another 10x in density compared to today’s “22nm node” ICs.

Imec held another Technology Forum at SEMICON/West this year, in which Wilfried Vandervorst presented an overview of innovations in metrology needed to continue shrinking device dimensions. His work with Scanning Spreading Resistance Microscopy (SSRM) is extraordinary, showing ability to resolve 1-2nm conductivity variations in memory cell material. Working with Resistive RAM (ReRAM) material using a 2nm diameter probe tip as the top contact, researchers were able to show switching of the material only underneath the contact…thus proving that a stable ReRAM cell can be made with that diameter. If we use cross-bar architectures of that material we’d be at a 4nm pitch for memory, coincidentally the same pitch needed for the densest array of 3-terminal logic components.

IC SCALING LIMITATION

Pitch / “Node”

Transistor nm2

Scale from 22nm
193nm lithography double-patterning

124nm / “22nm”

16000

1
Atomic variability (economics)

41nm / “7nm”

1600

10
Perfect atoms (physics)

4nm

16

1000

The refreshing aspect of this interconnect analysis is that it just doesn’t matter what magical switch you imagine replacing CMOS. No matter whether you imagine quantum-dots or molecular memories as circuit elements, you have to somehow connect them together.

Note also that moving to 3D IC designs does not fundamentally change the economic limits of scaling, nor does it alter the interconnect challenge. 3D ICs will certainly allow for greater number of devices to be packed into a given volume, so mobile applications will likely continue to pull for 3D integration. However, the cost/transistor is limited by 2D process technologies that have evolved over 60 years to provide maximum efficiency. Stacking IC layers will allow for faster and smaller devices, though generally only with greater costs.

Atoms don’t scale.

Past posts in the blog series:

Moore’s Law is Dead – (Part 1) What defines the end, and

Moore’s Law is Dead – (Part 2) When we reach economic limits.

The final post in this blog series (but not the blog) will discuss:

Moore’s Law is Dead – (Part 4) Why we say long live “Moore’s Law”!

—E.K.

Moore’s Law is Dead – (Part 2) When?

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…economics of lithography slow scaling.

Moore’s Law had been on life support ever since the industry started needing Double-Patterning (DP) at 1/4-pitch of 193nm optical lithography. EUV lithography shows slow and steady progress in source and resist technologies, and ASML folks tell me that they now have a pellicle to protect the reflective masks, yet it remains in R&D. All other lithographic technologies under consideration—e-beam direct write, nano-imprint, directed self-assembly—can help with patterning certain layers for certain chips, but lack the broad applicability and economic advantages of 193nm.

At this year’s SPIE Advanced Lithography event, renowned lithographer and gentleman scientist Chris Mack led an extended toast (https://www.youtube.com/watch?v=IBrEx-FINEI) that ended with, “Moore’s Law is over, long live Moore’s Law.” While Wednesday, February 26, 2014 may seem like a rather arbitrary moment, we seem to have the informal consensus of the world’s leading lithographers.

The 4th blog in this series will discuss the “Why” of Moore’s Law continuing as a marketing term…with each company in the industry using the term as well as “More than Moore” to mean slightly different technology advances. Henceforth, “Moore’s Law” may mean that the next IC will be smaller, or faster, or cheaper…but we are past the era when new chips will be simultaneously smaller and faster and cheaper.

ScalingTrends_2003-2015_32nmThe adjacent figure from SEMI shows the rate of scaling since we hit 90nm half-pitch…the last time that the term “node” directly correlated to the lithographic half-pitch. The clear inflection-point at the “32nm node” (which was really 45nm half-pitch) was the moment that DP was needed for patterning critical layers. In a panel discussion at the 2014 imec Technology Forum in San Francisco during SEMICON/West, John Chen, vice president of technology and foundry management, NVIDIA clearly declared, “Double-patterning is a technological and economic discontinuity.”

I should note that, as the EUV developer for the world, ASML strongly feels that the technology will enable future cost-effective scaling.

Meanwhile, 193nm lithography currently provides the economic limits to scaling, so we can easily understand recent and future phases of the industry in terms of fractions of this wavelength:

½ of 193nm = 90nm half-pitch as the end of simple scaling,

¼ of 193nm = 45nm half-pitch (~32nm “node”) begins Double Patterning,

1/8 of 193nm = 22nm half-pitch begins Quadruple Patterning, and

1/16th of 193nm = 11nm half-pitch which would need Octuple Patterning.

Note that the half-pitch limits shown above are approximations, and the lithography community has been using every trick in the book to lower the resolution limit of 193nm lithography. Water immersion for higher-NA, ‘inverse lithography’ to optimize phase-shifting masks, and off-axis illumination have all been deployed to allow 45nm half-pitch patterning.

Quartz lenses become opaque below 193nm, and thereby limit use of any lower wavelengths. Thus, 193nm has become an economic limit on affordable IC production, just as 1234 km/h has been proven as the economic limit on commercial aircraft speed. The “Concorde analogy” explains that physical world constraints combine with economics to create real limits on exponential progress.

Since the air-travel industry hit the economic limit of the speed-of-sound, air-travel innovation has continued but not in raw speed. Quiet airplane cabins and huge improvement in in-flight entertainment and food, when combined with refreshments and entertainment in airports improves the overall experience. Wireless computer networks on airplanes and in airports allow travelers with mobile computers (including smart-phones and tablets) to work and play throughout the travel day.

Innovation in the semiconductor industry will certainly continue after we can no longer afford to shrink digital switches. We already have billions of logic elements with which to form circuitry, and we can combine logic with embedded-memory and with sensors and actuators into 3D nanoscale systems. We can do this today. The truth is, when we run out of room at the 2D bottom we have plenty of room to play at the 3D top…remembering that the cost of chip stacking is set by 2D processing economics.

Past post in the blog series:

Moore’s Law is Dead – (Part 1) What defines the end.

Imminent posts in this blog series will discuss:

Moore’s Law is Dead – (Part 3) Where we reach atomic limits,

Moore’s Law is Dead – (Part 4) Why we say long live “Moore’s Law”!

—E.K.