Tag Archives: node

Moore’s Law Smells Funny

…maybe we need “Integrated Cleverness Law”

“Jazz is not dead, it just smells funny.” – Frank Zappa 1973
from Be-Bop Tango (Of The Old Jazzmen’s Church)

Marketing is about managing expectations. IC marketing must position next-generation chips as adding significant new/improved functionalities, and for over 50 years the IC fab industry has leaned on the conceptual crutch of “so-called Moore’s Law” (as Gordon Moore always refers to it) to do so. For 40 years the raw device count was a good proxy for a better IC, but since the end of Dennard Scaling the raw transistor count on a chip is no longer the primary determinant of value.

Intel’s has recently released official positions on Moore’s Law, and the main position is certainly correct: “Advances in Semi Manufacturing Continue to Make Products Better and More Affordable,” as per the sub-headline of the blog post by Stacy Smith, executive vice president leading manufacturing, operations, and sales for Intel. Smith adds that “We have seen that it won’t end from lack of benefits, and that progress won’t be choked off by economics.” This is what has been meant by “Moore’s Law” all along.

When I interviewed Gordon Moore about all of this 20 years ago (“The Return of Cleverness” Solid State Technology, July 1997, 359), he wisely reminded us that before the industry reaches the limits of physical scaling we will be working with billions of transistors in a square centimeter of silicon. There are no ends to the possibilities of cleverly combining billions of transistors with sensors and communications technologies to add more value to our world. Intel’s recent spend of US$15B to acquire MobileEye is based on a plan to cost-effective integrate novel functionalities, not to merely make the most dense IC.

EETimes reports that at the International Symposium on Physical Design (ISPD 2017) Intel described more than a dozen technologies it is developing with universities and the SRC to transcend the limitations of CMOS. Ian Young, a senior fellow with Intel’s Technology Manufacturing Group and director of exploratory integrated circuits in components research, recently became the editor-in-chief of a new technical journal called the IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, which explores these new CMOS-fab compatible processes.

Meanwhile, Intel’s Mark Bohr does an admirable job of advocating for reason when discussing the size of minimally scaled ICs. Bohr is completely correct in touting Intel’s hard-won lead in making devices smaller, and the company’s fab prowess remains unparalleled.

As I posted here three years ago in my “Moore’s Law Is Dead” blog series, our industry would be better served by retiring the now-obsolete simplification that more = better. As Moore himself says, cleverness in design and manufacturing will always allow us to make more valuable ICs. Maybe it is time to retire “Moore’s Law” and begin leveraging a term like “Integrated Cleverness Law” when telling the world that the next generation of ICs will be better.

—E.K.

EUVL Masks may need to be Tool-Specific

Leave a reply

Extreme Ultra-Violet Lithography (EUVL) keeps hurting my brain. Just when I can understand how it could be used in profitable commercial high-volume manufacturing (HVM) I hear something that seriously strains my brain. First it was the mirrors and mask in vacuum, then it was the resist and pellicle, then it was the source power and availability, and in each case scientists and engineers did amazing work and showed a way to HVM. Now we hear that EUVL might require fabs to park work-in-progress (WIP) lots of wafers behind a single critical tool with an idealistic 80% availability on a good day, and lots of downtime bad days. Horrors!

For “5nm-node” designs the maximum allowable edge placement-error (EPE) in patterning overlay is only 2nm. While the physics of ~13.5nm wavelength EUVL means that aberration in the reflecting mirrors appears as up to 3nm variation in the fidelity of projected patterns. This variation can be measured and compensated for at the physical mask level, but then each mask would only be good for one specific exposure tool. John Sturtevant—SPIE Fellow, and director of RET product development in the Design to Silicon Division at Mentor Graphics—briefly discussed this on February 26th during Nikon LithoVision held just before SPIE Advanced Lithography.

Sturtevant explained that the Zernike coefficients for EUV are inherently almost 1 order-of-magnitude higher than for DUV at 193nm wavelength, as detailed in the SemiMD article “Edge Placement Error Control in Multi-Patterning.” How the inherent physical sources of aberration must be tightened to avoid image distortion and contrast loss as they scale with wavelength was discussed by by Fenger et al. in 2013 in the article “Extreme ultraviolet lithography resist-based aberration metrology” (doi:10.1117/1.JMM.12.4.043001).

—E.K.

Reliable ICs from unreliable devices

Leave a reply

In an article published in the most recent issue of imec’s online magazine (http://magazine.imec.be/) titled “Chips must learn how to feel pain and how to cure themselves,” researchers Francky Chatthoor and Guido Groeseneken discuss how to build reliable “5nm-node” ICs out of inherently unreliable transistors. Variability in “zero time” and “over time” performance of individual transistors cannot be controlled below the “7nm-node” using traditional guard-banding in IC design.

“Maybe it means the end of the guard-band approach, but certainly not the end of scaling,” says Groeseneken in the article. “In our research group we measure and tried to understand reliability issues in scaled devices. In the 40nm technology, it is still possible to cope with the reliability issues of the devices and make a good system. But at 7nm, the unreliability of the devices risks to affect the whole system. And conventional design techniques can’t stop this from happening. New design paradigms are therefore urgently needed.” These researchers predict that industry will have to manufacture self-healing chips by the year 2025.

Self-healing chips could use the workload variation of the system for their benefit. Based on a deterministic predictor of the future, future slack is determined and used to compensate for the delay error and mitigate at peak load. (Source: imec)

The ultimate goal of imec and its academic partners is to develop a fully proactive parametric reliability mitigation technique with distributed monitors, a control system and actuators, fully preventing the consequence of delay faults and potentially also of functional faults. Said Catthour, “the secret to the solution lies in the work load variation of the system. Based on a deterministic predictor of the future, you determine future slack and use this to compensate for the delay error at peak load. Based on this info on the future, you change the scheduling order and the assignment of operations.” The Figure shows how self-healing chips can use future slack to compensate for delay error and mitigate at peak load.

—E.K.

EUV Cost at 1000 Daily Exposures

Leave a reply

On October 14, 2015, ASML Holding N.V. (ASML) published its 2015 third-quarter results: Q3 net sales of €1.55 billion with gross margin of 45.4% (in line with guidance), and guided Q4 2015 net sales at approximately €1.4 billion and a gross margin of around 45%. Due to mismatched financial analyst expectations, Bloomberg reported that ASML’s stock price dropped ~7% in a single day of trading, despite the company also reporting upgrades to both the TWINSCAN NXT 193nm-immersion (193i) and the NXE Extreme Ultraviolet (EUV) tools. In particular, a new record of 1000 wafer exposures in a single day was set by one EUV tool.

The science of controlling the 13.54nm wavelength electromagnetic radiation that we like to call “Extreme Ultra-Violet” or “EUV” (instead of the colloquial scientific term “soft x-ray”) is inherently challenging. The engineering of EUV Lithography is not just challenging but bordering on inherently impossible: from exploding tin plasma source, to all-reflective lenses that absorb energy, to the trade-offs in mask pattern protection. The team at ASML working on the exposure tool—along with the different specialist organizations still working on improved sources, masks, and resists—deserve the industry’s unwavering admiration for the important work they do every day.

In a prepared statement, ASML President and Chief Executive Officer Peter Wennink said, “We have proven the capability both to expose 1,000 wafers per day and, in a manufacturing readiness test, to expose 15,000 wafers in four weeks. We have also achieved a four-week average availability of more than 70 percent at multiple customer sites. The first shipment of our fourth-generation EUV lithography system, the NXE 3350B, is in progress, with two more expected to ship in Q4.”

Still, progress along desired EUV roadmaps continues to be slow, and the competitive target shifts when the 193i exposure tool gains a 10% throughput improvement to 275 wafer-passes/hour (wph). When the 193i tool gains a 30% overlay improvement, that means double-patterning based on litho-etch-litho-etch (LELE) process flows gain in pattern fidelity. Since ASML provides both technologies, delays in orders for EUV just means more sales of 193i tools.

Let’s play with the numbers here…275 wph x 20 hours x 30 days = 165k wafer-passes/month for the NXT:1980. The NXE:3350B can current handle 15k wafer-passes/month. So even if the tools were equally priced, just based on tool depreciation each EUV exposure today costs >10x that of a 193i exposure, which is why pitch-splitting multi-patterning 193i continues to dominate.

—E.K.

Electronic Materials Specifications and Markets

Leave a reply

At SEMICON West this year, July 14-16 in San Francisco, the Chemical and Gas Manufacturers Group (CGMG) Committee of SEMI have organized an excellent program covering “Contamination Control in the Sub-20nm Era” to occur in the afternoon of the 14th as part of the free TechXPOT series. Recent high-volume manufacturing (HVM) developments have shown much tighter IC control specifications in terms of particles, metal contaminants, and organic contaminants. The session will present a comprehensive picture of how the industry value chain participants are collaborating to address contamination control challenges:
1. IDM / foundry about the evolving contamination control challenges and requirements,
2. OEM process and metrology/defect inspection tools to minimize defects, and
3. Materials and sub-component makers eliminating contaminants in the materials manufacturing, shipment, and dispensing process before they reach the wafer.

Updated reports about the markets for specialty electronic materials have recently been published by the industry analysts at TechCet, including topics such as ALD/CVD presursors, CMP consumables, general gases, PVD targets, and silicon wafers. Strategic inflection points continue to appear in different sub-markets for specialty materials, as specifications evolve to the point that a nano-revolution is needed. One example is TechCet’s recent reporting that 3M’s fixed-abrasive pad for CMP has been determined to be unable to keep up with defect demands below 20nm, and is undergoing an orderly withdrawal from the market.

As in prior years, SEMICON West includes many free and paid technology sessions and workshops, the Silicon Innovation Forum and other business events, as well as a profusion of partner events throughout the week.

—E.K.

Moore’s Law is Dead – (Part 3) Where?

10 Replies

…we reach the atomic limits of device scaling.

At ~4nm pitch we run out of room “at the bottom,” after patterning costs explode at 45nm pitch.

Lead bongo player of physics Richard Feynman famously said, “There’s plenty of room at the bottom,” and in 1959 when the IC was invented a semiconductor device was composed of billions of atoms so it seemed that it would always be so. Today, however, we can see the atomic limits of miniaturization on the horizon, and we can start to imagine the smallest possible functioning electronic device.

Today’s leading edge ICs are made using “22nm node” fab technology where the smallest lithographically defined structure—likely a transistor gate—is just 22nm across. However, the pitch between such transistors is ~120nm, because we are already dealing with the resolution limits of lithography using water-immersion 193nm with off-axis-illumination through phase-shift masks. Even if a “next-generation” lithography (NGL) technology were proven cost-effective in manufacturing— perhaps EbDW for guidelines combined with DSA for feature fill and EUV for trim—we still must control individual atoms.

We may have confidence in shrinking to 62nm pitch for a 4x increase in density. We may even be optimistic that we can shrink further to a 41nm pitch for a ~10x increase in density…but that’s nearing the atomic limits of variability. There are many hypothesized nanoscale devices which could succeed silicon CMOS in IC, but one commonality of all devices is that they will have to be electrically connected. Therefore, we can simplify our consideration of the atomic limits of device scaling by focusing on the smallest possible interconnect.

So what is the smallest possible electrical interconnect? So far it would be a Single-Walled Carbon NanoTube (SWCNT) doped with metals to be conducting. The minimum diameter of a SWCNT happens to be 0.4nm, but that was found inside another CNT and the minimum repeatable diameter for a stand-alone SWCNT is ~1nm. So if we need three contacts to a device then the smallest device we can build with atoms would be a 3nm diameter quantum dot. As shown in the figure at right, if we examine a plan-view of such a device we can just fit three 1nm diameter contacts within the area.

Our magical device will have to be electrically isolated and so some manner of dielectric will be needed with some minimal number of atoms. Atomic Layer Deposition (ALD) of alumina has been proven in very tight geometries, and 3 atomic layers of alumina takes up ~1nm so we can assume that spacing between devices. A rectangular array would then result in ~16nm2 as the smallest possible 3-terminal device that can be built on the surface of planet Earth.

Note that a SWCNT of ~1 nm diameter theoretically could carry ~25 microAmps across an estimated 5kOhm internal resistance [(ECS Transactions, 3 (2) 441-448 (2006)]. I will leave it to someone with a stronger device physics background to comment as to the suitability of such contacts for useful circuitry. However, from a manufacturing perspective, to ensure electrical contacts to billions of nanoscale devices we generally use redundant structures, and doubling the number of SWCNT contacts to a 3-terminal device would call for ~8 nm pitch.

However, before we reach the 4-8nm pitch theoretical limits of device scaling, we will reach relative economic limits of scaling just one device feature such as a transistor gate. Recall that there are just 22 silicon atoms (assuming silicon crystal lattice spacing of ~0.3nm) across a ~7nm line, and every atom counts in controlling device parameters. Imec’s Aaron Thean recently provided an excellent overview of scaled finFET technologies, and though the work does not look at packing density we can draw some general trends. If we assume 41nm pitch and double fins with 20nm gate length then each device would use ~1,600 nm2.

Where are we now? Let us consider traditional 6-transistor (6T) SRAM cells built using “22nm node” logic process flows to have minimal area of ~100,000 nm2 or ~16,000 nm2 per transistor. At IEDM2013 (9.1), TSMC announced a “16nm node” 6T SRAM with ~70,000 nm2 area or ~10,000 nm2 per transistor.

IBM recently announced that 6 parallel 30nm long SWCNT spaced 8nm apart will be developed as transistors for ICs by the year 2020. Such an array would use up ~1440 nm2 of area. Again, this is at best another 10x in density compared to today’s “22nm node” ICs.

Imec held another Technology Forum at SEMICON/West this year, in which Wilfried Vandervorst presented an overview of innovations in metrology needed to continue shrinking device dimensions. His work with Scanning Spreading Resistance Microscopy (SSRM) is extraordinary, showing ability to resolve 1-2nm conductivity variations in memory cell material. Working with Resistive RAM (ReRAM) material using a 2nm diameter probe tip as the top contact, researchers were able to show switching of the material only underneath the contact…thus proving that a stable ReRAM cell can be made with that diameter. If we use cross-bar architectures of that material we’d be at a 4nm pitch for memory, coincidentally the same pitch needed for the densest array of 3-terminal logic components.

IC SCALING LIMITATION	Pitch / “Node”	Transistor nm2	Scale from 22nm
193nm lithography double-patterning	124nm / “22nm”	16000	1
Atomic variability (economics)	41nm / “7nm”	1600	10
Perfect atoms (physics)	4nm	16	1000

The refreshing aspect of this interconnect analysis is that it just doesn’t matter what magical switch you imagine replacing CMOS. No matter whether you imagine quantum-dots or molecular memories as circuit elements, you have to somehow connect them together.

Note also that moving to 3D IC designs does not fundamentally change the economic limits of scaling, nor does it alter the interconnect challenge. 3D ICs will certainly allow for greater number of devices to be packed into a given volume, so mobile applications will likely continue to pull for 3D integration. However, the cost/transistor is limited by 2D process technologies that have evolved over 60 years to provide maximum efficiency. Stacking IC layers will allow for faster and smaller devices, though generally only with greater costs.

Atoms don’t scale.

Past posts in the blog series:

Moore’s Law is Dead – (Part 1) What defines the end, and

Moore’s Law is Dead – (Part 2) When we reach economic limits.

The final post in this blog series (but not the blog) will discuss:

Moore’s Law is Dead – (Part 4) Why we say long live “Moore’s Law”!

—E.K.

Moore’s Law is Dead – (Part 2) When?

5 Replies

…economics of lithography slow scaling.

Moore’s Law had been on life support ever since the industry started needing Double-Patterning (DP) at 1/4-pitch of 193nm optical lithography. EUV lithography shows slow and steady progress in source and resist technologies, and ASML folks tell me that they now have a pellicle to protect the reflective masks, yet it remains in R&D. All other lithographic technologies under consideration—e-beam direct write, nano-imprint, directed self-assembly—can help with patterning certain layers for certain chips, but lack the broad applicability and economic advantages of 193nm.

At this year’s SPIE Advanced Lithography event, renowned lithographer and gentleman scientist Chris Mack led an extended toast (https://www.youtube.com/watch?v=IBrEx-FINEI) that ended with, “Moore’s Law is over, long live Moore’s Law.” While Wednesday, February 26, 2014 may seem like a rather arbitrary moment, we seem to have the informal consensus of the world’s leading lithographers.

The 4^th blog in this series will discuss the “Why” of Moore’s Law continuing as a marketing term…with each company in the industry using the term as well as “More than Moore” to mean slightly different technology advances. Henceforth, “Moore’s Law” may mean that the next IC will be smaller, or faster, or cheaper…but we are past the era when new chips will be simultaneously smaller and faster and cheaper.

The adjacent figure from SEMI shows the rate of scaling since we hit 90nm half-pitch…the last time that the term “node” directly correlated to the lithographic half-pitch. The clear inflection-point at the “32nm node” (which was really 45nm half-pitch) was the moment that DP was needed for patterning critical layers. In a panel discussion at the 2014 imec Technology Forum in San Francisco during SEMICON/West, John Chen, vice president of technology and foundry management, NVIDIA clearly declared, “Double-patterning is a technological and economic discontinuity.”

I should note that, as the EUV developer for the world, ASML strongly feels that the technology will enable future cost-effective scaling.

Meanwhile, 193nm lithography currently provides the economic limits to scaling, so we can easily understand recent and future phases of the industry in terms of fractions of this wavelength:

½ of 193nm = 90nm half-pitch as the end of simple scaling,

¼ of 193nm = 45nm half-pitch (~32nm “node”) begins Double Patterning,

1/8 of 193nm = 22nm half-pitch begins Quadruple Patterning, and

1/16^th of 193nm = 11nm half-pitch which would need Octuple Patterning.

Note that the half-pitch limits shown above are approximations, and the lithography community has been using every trick in the book to lower the resolution limit of 193nm lithography. Water immersion for higher-NA, ‘inverse lithography’ to optimize phase-shifting masks, and off-axis illumination have all been deployed to allow 45nm half-pitch patterning.

Quartz lenses become opaque below 193nm, and thereby limit use of any lower wavelengths. Thus, 193nm has become an economic limit on affordable IC production, just as 1234 km/h has been proven as the economic limit on commercial aircraft speed. The “Concorde analogy” explains that physical world constraints combine with economics to create real limits on exponential progress.

Since the air-travel industry hit the economic limit of the speed-of-sound, air-travel innovation has continued but not in raw speed. Quiet airplane cabins and huge improvement in in-flight entertainment and food, when combined with refreshments and entertainment in airports improves the overall experience. Wireless computer networks on airplanes and in airports allow travelers with mobile computers (including smart-phones and tablets) to work and play throughout the travel day.

Innovation in the semiconductor industry will certainly continue after we can no longer afford to shrink digital switches. We already have billions of logic elements with which to form circuitry, and we can combine logic with embedded-memory and with sensors and actuators into 3D nanoscale systems. We can do this today. The truth is, when we run out of room at the 2D bottom we have plenty of room to play at the 3D top…remembering that the cost of chip stacking is set by 2D processing economics.

Past post in the blog series:

Moore’s Law is Dead – (Part 1) What defines the end.

Imminent posts in this blog series will discuss:

Moore’s Law is Dead – (Part 3) Where we reach atomic limits,

Moore’s Law is Dead – (Part 4) Why we say long live “Moore’s Law”!

—E.K.