Tag Archives: advanced

EUVL Masks may need to be Tool-Specific

Extreme Ultra-Violet Lithography (EUVL) keeps hurting my brain. Just when I can understand how it could be used in profitable commercial high-volume manufacturing (HVM) I hear something that seriously strains my brain. First it was the mirrors and mask in vacuum, then it was the resist and pellicle, then it was the source power and availability, and in each case scientists and engineers did amazing work and showed a way to HVM. Now we hear that EUVL might require fabs to park work-in-progress (WIP) lots of wafers behind a single critical tool with an idealistic 80% availability on a good day, and lots of downtime bad days. Horrors!

For “5nm-node” designs the maximum allowable edge placement-error (EPE) in patterning overlay is only 2nm. While the physics of ~13.5nm wavelength EUVL means that aberration in the reflecting mirrors appears as up to 3nm variation in the fidelity of projected patterns. This variation can be measured and compensated for at the physical mask level, but then each mask would only be good for one specific exposure tool. John Sturtevant—SPIE Fellow, and director of RET product development in the Design to Silicon Division at Mentor Graphics—briefly discussed this on February 26th during Nikon LithoVision held just before SPIE Advanced Lithography.

Sturtevant explained that the Zernike coefficients for EUV are inherently almost 1 order-of-magnitude higher than for DUV at 193nm wavelength, as detailed in the SemiMD article “Edge Placement Error Control in Multi-Patterning.” How the inherent physical sources of aberration must be tightened to avoid image distortion and contrast loss as they scale with wavelength was discussed by by Fenger et al. in 2013 in the article “Extreme ultraviolet lithography resist-based aberration metrology” (doi:10.1117/1.JMM.12.4.043001).

—E.K.

CSP Market Forecast – Strong

Chip-Scale Packages (CSP) continue to be in strong demand for IC needing the smallest form-factors for applications including automotive, industrial applications to mobile phones and wearable electronics, according to leading market research firm TechSearch International. TechSearch’s latest CSP market forecast shows a 8% CAGR from 2015 to 2020, despite a slowing growth rate for smartphones.

One of the categories with the strongest growth is the quad flat no-lead (QFN) package with a CAGR of 8.6%. QFNs are a low-cost, low-profile package found in a wide range of products from automotive and power devices. An analysis of the Out-Sourced Assembly and Test (OSAT) market in China provides insight into expansion plans and market shares.

Fan-Out Wafer-Level Packages (FO-WLP) with many variations are now winning slots in many new mobile devices. New advanced packages such as JCAP’s FO-WLP are highlighted in the latest Advanced Packaging Update, along with the use of TSMC’s FO-WLP for Apple’s A10 application processor. The report also examines trends in stacked die CSPs, laminate-substrate CSPs, and package-on-package (PoP) with a market forecast for each. See:  http//www.techsearchinc.com.

—E.K.