Tag Archives: engineering

Controlling Polymers to Tune TFTs

Thin-film transistors (TFT) created using only additive process steps could create new low-cost ICs with functionalities beyond silicon, but only if we understand how to control structures at the molecular level. Thin films of conjugated polymers such as poly(3-hexylthiophene) (P3HT) can provide useful conductivity when the electron mobilities are controlled within as well as between molecules. In producing TFTs using such organic macromolecules, we must rigorously control the deposition and annealing processes so that the right molecules line up in the right order.
Peter F. Green, Professor of Chemical Engineering, Macromolecular Science and Engineering at the University of Michigan, and his team fabricated ~55 nm thin films of P3HT using resonant-infrared matrix-assisted pulsed laser evaporation (RIR-MAPLE), as well as conventional spin-casting. The films produced by MAPLE show a higher degree of structural disorder, with localized trap sites that reduce mobility out-of-plane by an order of magnitude compared to spin-cast films.

(Source: Peter Green, University of Michigan)

The Figure shows that despite the disorder of MAPLE-deposited P3HT, enhanced carrier density at the dielectric interface allows TFTs to exhibit similar in-plane mobilities to those built using conventionally spin-coated films. TFTs were top-contact, bottom-gate designs on 300nm thermal oxide on highly doped silicon. In-plane carrier mobilities of MAPLE-deposited versus spin-cast films were 8.3 versus 5.5 (×10 -3 cm2/V/s). In principle, the ability to independently control in- and out-of-plane mobilities allows for the fine tuning of TFT parameters for different applications.
—E.K.

Nowhere Near Room Temp Superconductors

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On-chip metal interconnects limit IC speed in many advanced design today, and with signal delay proportional to the product of the resistance (R) of wires and the capacitance (C) of dielectric insulation, wires with R lower than that of copper (Cu) metal would significantly improve IC performance. We know of superconductors—materials with zero resistance to electrical current flow—but only at “critical temperature” (Tc) well below 77°K, and so there has been an ongoing quest by scientists to find a material with Tc above room temperature of 298°K.

Sadly, after 4 years and nearly 1000 materials tested, a team of 6 Japanese research groups led by Hideo Hosono from the Tokyo Institute of Technology found no room temperature superconductors. They did find 100 previously unknown superconductors with Tc <56°K, and they published crystal structures and phase diagrams of all materials studied to help other researchers avoid now known dead-ends (DOI: 10.1088/1468-6996/16/3/033503).

Other researchers continue to explore the possibilities of using one-dimensional (1D) carbon-based materials such as carbon-nano-tubes (CNT) or graphene as on-chip conductors. So far, there are extreme difficulties in controlling the growth of such 1D structures within interconnect patterns, and additional challenges with forming ohmic contacts between CNT and Cu lines across billions of connections in a modern IC. More science is seemingly needed to find new paths before the engineers can explore those paths to find better solutions. Meanwhile…for the next few years at least…expect Cu metal to be the continued choice for nearly all multi-level metal interconnects on chip.

—E.K.

EUV Cost at 1000 Daily Exposures

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On October 14, 2015, ASML Holding N.V. (ASML) published its 2015 third-quarter results: Q3 net sales of €1.55 billion with gross margin of 45.4% (in line with guidance), and guided Q4 2015 net sales at approximately €1.4 billion and a gross margin of around 45%. Due to mismatched financial analyst expectations, Bloomberg reported that ASML’s stock price dropped ~7% in a single day of trading, despite the company also reporting upgrades to both the TWINSCAN NXT 193nm-immersion (193i) and the NXE Extreme Ultraviolet (EUV) tools. In particular, a new record of 1000 wafer exposures in a single day was set by one EUV tool.

The science of controlling the 13.54nm wavelength electromagnetic radiation that we like to call “Extreme Ultra-Violet” or “EUV” (instead of the colloquial scientific term “soft x-ray”) is inherently challenging. The engineering of EUV Lithography is not just challenging but bordering on inherently impossible: from exploding tin plasma source, to all-reflective lenses that absorb energy, to the trade-offs in mask pattern protection. The team at ASML working on the exposure tool—along with the different specialist organizations still working on improved sources, masks, and resists—deserve the industry’s unwavering admiration for the important work they do every day.

In a prepared statement, ASML President and Chief Executive Officer Peter Wennink said, “We have proven the capability both to expose 1,000 wafers per day and, in a manufacturing readiness test, to expose 15,000 wafers in four weeks. We have also achieved a four-week average availability of more than 70 percent at multiple customer sites. The first shipment of our fourth-generation EUV lithography system, the NXE 3350B, is in progress, with two more expected to ship in Q4.”

Still, progress along desired EUV roadmaps continues to be slow, and the competitive target shifts when the 193i exposure tool gains a 10% throughput improvement to 275 wafer-passes/hour (wph). When the 193i tool gains a 30% overlay improvement, that means double-patterning based on litho-etch-litho-etch (LELE) process flows gain in pattern fidelity. Since ASML provides both technologies, delays in orders for EUV just means more sales of 193i tools.

Let’s play with the numbers here…275 wph x 20 hours x 30 days = 165k wafer-passes/month for the NXT:1980. The NXE:3350B can current handle 15k wafer-passes/month. So even if the tools were equally priced, just based on tool depreciation each EUV exposure today costs >10x that of a 193i exposure, which is why pitch-splitting multi-patterning 193i continues to dominate.

—E.K.