Tag Archives: imec

Reliable ICs from unreliable devices

In an article published in the most recent issue of imec’s online magazine (http://magazine.imec.be/) titled “Chips must learn how to feel pain and how to cure themselves,” researchers Francky Chatthoor and Guido Groeseneken discuss how to build reliable “5nm-node” ICs out of inherently unreliable transistors. Variability in “zero time” and “over time” performance of individual transistors cannot be controlled below the “7nm-node” using traditional guard-banding in IC design.

“Maybe it means the end of the guard-band approach, but certainly not the end of scaling,” says Groeseneken in the article. “In our research group we measure and tried to understand reliability issues in scaled devices. In the 40nm technology, it is still possible to cope with the reliability issues of the devices and make a good system. But at 7nm, the unreliability of the devices risks to affect the whole system. And conventional design techniques can’t stop this from happening. New design paradigms are therefore urgently needed.” These researchers predict that industry will have to manufacture self-healing chips by the year 2025.

Self-healing chips could use the workload variation of the system for their benefit. Based on a deterministic predictor of the future, future slack is determined and used to compensate for the delay error and mitigate at peak load. (Source: imec)

The ultimate goal of imec and its academic partners is to develop a fully proactive parametric reliability mitigation technique with distributed monitors, a control system and actuators, fully preventing the consequence of delay faults and potentially also of functional faults. Said Catthour, “the secret to the solution lies in the work load variation of the system. Based on a deterministic predictor of the future, you determine future slack and use this to compensate for the delay error at peak load. Based on this info on the future, you change the scheduling order and the assignment of operations.” The Figure shows how self-healing chips can use future slack to compensate for delay error and mitigate at peak load.

—E.K.

Broadening Scope of SEMICON

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Once upon a time, SEMICONs were essentially just for semiconductor manufacturing business and technology, and predominantly CMOS ICs. Back when we followed public roadmaps for technology to maintain the cadence of new manufacturing nodes in support of Moore’s Law, it was sufficient to focus on faster transistors connected with tighter wires. Now in an era that is at least partially “More-than-Moore”—as we like to refer to heterogeneous integration of non-CMOS technologies into commercial ICs—SEMICON West 2016 will focus on technologies beyond silicon CMOS such as MEMS and flexible organic semiconductors.

Alissa Fitzgerald, founder and managing member of AM Fitzgerald & Associates, will present on some of these themes Wednesday afternoon during the “What’s Next in MEMS and Sensors: Innovations to Drive the Next Generation of Growth” session (Track 2) of SEMICON’s Advanced Manufacturing Forum. Much of that growth is expected to be in sensors, microprocessors, ultra-low-power supplies, and communications chips to support the Internet of Things (IoT) connected by high-speed 5G data networks.

Flexible/Hybrid Electronics Forum at SEMICON West this year includes two full days of excellent presentations on new technologies that include thinned device processing, device/sensor integrated printing and packaging, and reliability testing and modeling. The following is the full list of forums this year:

Advanced Manufacturing,
Advanced Packaging,
Extended Supply-Chain,
Flexible/Hybrid Electronics,
Silicon Innovation,
Sustainable Manufacturing,
Test, and
World of IoT.

Partner programs include focused forums discussing trends in technology, markets, and the business of commercial IC fabrication. The industry’s default center of “More Moore” R&D is now imec in Belgium, and invited attendees of the imec technology forum (ITF) in San Francisco happening on July 11th the day before the start of SEMICON West will learn about the latest results in CMOS device shrinking from finFETs to nanowires. The next evening, French R&D and pilot manufacturing center CEA-Leti will lead a workshop detailing how to partner with the organization to bring sensor-based “More-than-Moore” technologies to market. Thursday morning will feature the Entegris Yield Breakfast Forum discussing the need for new materials handling solutions due to “Yield Enhancement Challenges in Today’s Memory IC Production.”

As the official event website summarizes: We’ve deepened our reach across the full electronics manufacturing supply chain to connect you with more key players — including major industry leaders like Cisco, Samsung, Intel, Audi, Micron, and more. New players, demand generators, systems integrators, and emerging industry segments — all connecting in one place. Keynote presentations will be provided by Cisco Systems, Kateeva, and Oracle.

—E.K.

Eloquent Executives Ecosystem Expositions

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#cmc,#confab,#namedropping

With dimensional scaling reaching economic limits, each company in the IC fab industry must rely upon trusted connections with customers and suppliers to know which way to go, and the only way to gain trusted connections is through attending live events. Fortunately, whether you are an executive, and engineer, or an investor, there is at least one must-attend event happening these days to keep you informed.

We should always start with SEMI (sponsor of SemiMD, personal friends for many years) who has always represented the gold standard for trade-shows, executive events, and manufacturing symposia around the world. I attended my first SEMICON/West in 1988, and have since attended excellent SEMICONs in Europe, Japan, Korea, China, and Singapore. This year’s SEMICON gathering in San Francisco will feature a nearly 50% increase in the number of technical sessions.

SEMI ran another excellent Advanced Semiconductor Manufacturing Conference (ASMC) in Albany this month, featuring keynotes by visionaries such as “Nanoscale III-V CMOS” by MIT Professor Jesus A. del Alamo. The panel discussion “Moore’s Law Wall vs. Moore’s Wallet, and where do we grow from here,” was moderated by industry veteran Paul Werbaneth, now with Intevac. It is clear that we will reach economic limits of scaling well before the physical limits.

Materials technology and supply-chain solutions to extend economic limits were discussed by Intel’s VP of Technology and Manufacturing Tim Hendry in a keynote at the Critical Materials Conference (CMC) held this year in Oregon in early May, as produced by Techcet CA (I am also an analyst with Techcet and co-chair of this event, while Solid State Technology was a media sponsor). David Thompson, Senior Director, Center of Excellence in Chemistry, Applied Materials showed that despite the inherent “Agony in New Material Introductions – minimizing and correlating variabilities” is possible with improved collaboration throughout the supply-chain.

The Imec Technology Forum in Brussells this month (Solid State Technology was a media sponsor) could best be described with Lake Wobegone hyperbole that all the women were strong, the men were good-looking, and everyone was above average. The big news is imec acquiring iMinds for greater synergies when integrating the latter’s algorithms with imec-ecosystem hardware for application-specific solutions. Gary Patton, now CTO and SVP of Global R&D for GLOBALFOUNDRIES, reminded everyone at ITF of the inherent speed constraints of the copper wires and low-k dielectrics needed to connect IC transistors, “As I’ve often said, It’s like you have a Ferrari but you’re towing a boat if you don’t address the interconnect delay issues.” Regardless, Patton confidently declares that, “We will continue to provide value to our customers to be able to create new products, and we will innovate in ways other than simple scaling.”

At ITF, a video was shown of imec president Luc van den Hove interviewing Gordon Moore at his beachfront home in Hawaii. Moore has always been humble and claims no special ability to forecast trends. “It would not surprise me if we reached the end of scaling in the next decade,” said Moore. “I missed the importance of the PC, and I missed the importance of the internet. Predicting the future is a difficult job and I leave it to someone else.”

Wally Rhines seemed able to predict the future when he eloquent expounded upon Moore’s Law as a special-case learning-curve in his presentation at ITF. Rhines will provide one of the keynote addresses at the ConFab in Las Vegas this year (Solid State Technology’s home event, co-sponsored by SEMI and by IEEE-CPMT). Executives from the global industry will gather to hear insights and analysis on the challenges facing all companies in the ecosystem, as we search for profitable pathways in a more complex landscape.

—E.K.

RFID Playing Cards “Best Product” at Printed Electronics Europe

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Cartamundi, imec and Holst Centre (set up by imec and TNO) recently won the Best Product Award at Printed Electronics Europe for their ultra-thin plastic RFID technology integrated into Cartamundi’s playing cards. In each card, the RFID chip has a unique code that communicates wirelessly to an RFID reader, giving the cards in the game a unique digital identity. The jury recognized the potential of this technology to enhance printed electronics applications for the Internet-of-Things (IoT), as well as being a gamechanger <RIMSHOT> for the gaming industry.

Chris Van Doorslaer, CEO of Cartamundi, said, “The new technology will connect traditional game play with electronic devices like smartphones and tablets. As Cartamundi is committed to creating products that connect families and friends of every generation to enhance the valuable quality time they share during the day, this technology is a real enabler.” Imec and Cartamundi engineers will now explore up-scaling of the technology using a foundry production model.

“This is a thrilling development to demonstrate our TOLAE electronic technology integrated in the product of a partner company. TOLAE stands for Thin, Oxide and Large-Area Electronics”, stated Paul Heremans, department director of thin-film electronics at imec and technology director at the Holst Centre. “Our prototype thin-film RFID is thinner than paper—so thin that it can be invisibly embedded in paper products, such as playing cards. This key enabling technology will bring the cards and traditional games of our customer in direct connection with the Cloud. This achievement also opens up new applications in the IoT domain that we are exploring, to bring more data and possibilities to applications such as smart packaging, security paper, and maybe even banknotes.”

—E.K.

SAQP Specs for 7nm finFETs

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As discussed in my last Ed’s Threads, lithography has become patterning as evidenced by first use of Self-Aligned Quadruple Patterning (SAQP) in High Volume Manufacturing (HVM) of memory chips. Meanwhile, industry R&D hub imec has been investigating use of SAQP for “7nm” and “5nm” node finFET HVM, as reported as SPIE-AL this year in Paper 9782-12.
The specifications for pitches ranging from 18 to 24 nanometers are as follow:

7.0nm Critical Dimension (CD) after etch,
0.5nm (3sigma) CD uniformity (CDU), and
<1nm Line-Width and Line-End Roughness (LWR and LER) assuming 10% of CD.

“Pitch walk”—variation in final pitch after multi-patterning—results in different line widths, and can result in subsequent excessive etch variation due to non-uniform loading effects. To keep the pitch walk in SAQP at acceptable levels for the 7nm node, the core-1 CDU has to be 0.5nm 3sigma and 0.8nm range after both litho and etch. In other presentations at SPIE-AL this year, the best LER after litho was ~4nm, improving to ~2nm after PEALD smoothing of sidewalls, but still double the desired spec.

The team at imec developed a SAQP flow using amorphous-Carbon (aC) and amorphous-Silicon (aSi) as the cores, and low-temperature Plasma-Enhanced Atomic-Layer Deposition (PEALD) of SiO2 for both sets of spacers. Bilayer DARC (SiOC) and BARC were used for reflectivity control. Compared to SAQP schemes where the mandrels are only aSi, imec claims that this approach saves 20% in cost due to the use of aC core and the elimination of etch-stopping-layers.

—E.K.

Thermoplastically Deformable Electronic Circuits

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Philips is testing a technology developed by imec and CMST (imec’s associated lab at Ghent University) to create low-cost 3D LED packages. As shown at last month’s International Microelectronics Assembly and Packaging Society (IMAPS 2015) meeting, these thermoplastically deformable electronic circuits are already being integrated by Philips into LED lamp carriers, a downlight luminaire, and a omnidirectional light source.

Miniature dome test vehicle with integrated low power LEDs, (a) circuit before forming, and (b) circuit after vacuum forming using a 40mm half-sphere mold. (Source: imec)

The technology is based on meander-shaped interconnects, which are patterned using standard printed circuit board (PCB) production equipment and then sandwiched between 2D thermoplastic polymer (e.g. polycarbonate) sheets. The Figure shows one example in final form after vacuum thermoforming into a 40mm half-sphere mold.
This is a glorious example of “elegant engineering” where a clever combination of materials and processes has been integrated with highly desirable characteristics: low tooling cost, low direct material cost, easily scalable from lab to fab, low product weight, and high product resilience. This seems to represent almost a new industrial product category that combines a “package” and a PCB.

—E.K.

Bottoms-up ELD of Cobalt Plugs

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As reported in more detail at Solid State Technology, during the IEEE IITC now happening in Grenoble, imec and Lam showed a new Electroless Deposition (ELD) cobalt (Co) process that is claimed to provide void-free bottoms-up pre-filling of vias and contacts. The unit-process is intended to be integrated into flows to produce scaled interconnects for logic and DRAM ICs at the 7nm node and below. Co-incidentally at IITC this year, imec and Lam also presented on a new ELD copper (Cu) process for micron-plus-scale through-silicon vias (TSV).

The bulk resistivities of metals commonly used in IC fabrication are as follows (E-8 Ω⋅m):
Cu – 1.70,
Al – 2.74,
W – 5.3, and
Co – 5.8.
Of course, the above values for bulk materials assume minimal influence of grain sizes and boundary layers. However, in scaled on-chip interconnect structures using in today’s advanced ICs, the resistivity is dominated by grain-boundaries and interfacial materials. Consequently, the resistivity of vias in 7nm node and beyond interconnects may be similar for Cu and Co depending upon the grain-sizes and barrier layers.

The melting temperatures of these metals are as follows (°C):
Al – 660,
Cu – 1084,
Co – 1495, and
W – 3400.
With higher melting temperature compared to Cu, Co contacts/plugs would provide some of the thermal stability of W to allow for easier integration of transistors and interconnects. Seemingly, the main reason to use Co instead of W is that the latter requires CVD processing that intrinsically does not allow for bottom-up deposition.

—E.K.