Tag Archives: scaling

Reliable ICs from unreliable devices

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In an article published in the most recent issue of imec’s online magazine (http://magazine.imec.be/) titled “Chips must learn how to feel pain and how to cure themselves,” researchers Francky Chatthoor and Guido Groeseneken discuss how to build reliable “5nm-node” ICs out of inherently unreliable transistors. Variability in “zero time” and “over time” performance of individual transistors cannot be controlled below the “7nm-node” using traditional guard-banding in IC design.

“Maybe it means the end of the guard-band approach, but certainly not the end of scaling,” says Groeseneken in the article. “In our research group we measure and tried to understand reliability issues in scaled devices. In the 40nm technology, it is still possible to cope with the reliability issues of the devices and make a good system. But at 7nm, the unreliability of the devices risks to affect the whole system. And conventional design techniques can’t stop this from happening. New design paradigms are therefore urgently needed.” These researchers predict that industry will have to manufacture self-healing chips by the year 2025.

Self-healing chips could use the workload variation of the system for their benefit. Based on a deterministic predictor of the future, future slack is determined and used to compensate for the delay error and mitigate at peak load. (Source: imec)

Self-healing chips could use the workload variation of the system for their benefit. Based on a deterministic predictor of the future, future slack is determined and used to compensate for the delay error and mitigate at peak load. (Source: imec)

The ultimate goal of imec and its academic partners is to develop a fully proactive parametric reliability mitigation technique with distributed monitors, a control system and actuators, fully preventing the consequence of delay faults and potentially also of functional faults. Said Catthour, “the secret to the solution lies in the work load variation of the system. Based on a deterministic predictor of the future, you determine future slack and use this to compensate for the delay error at peak load. Based on this info on the future, you change the scheduling order and the assignment of operations.” The Figure shows how self-healing chips can use future slack to compensate for delay error and mitigate at peak load.

—E.K.

Single-electron Molecular Switch 4nm Across

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A molecule rotating on the surface of a crystal can function as a tunnel-gate of a transistor, as shown by researchers from the Paul-Drude-Institut für Festkörperelektronik (PDI) and the Freie Universität Berlin (FUB), Germany, the NTT Basic Research Laboratories (NTT-BRL), Japan, and the U.S. Naval Research Laboratory (NRL). Their complete findings are published in the 13 July 2015 issue of the journal Nature Physics. The team used a highly stable scanning tunneling microscope (STM) to create a transistor consisting of a single organic molecule and positively charged metal atoms, positioning them with the STM tip on the surface of an indium arsenide (InAs) crystal.
Dr. Stefan Fölsch, a physicist at the PDI who led the team, explained that “the molecule is only weakly bound to the InAs template. So, when we bring the STM tip very close to the molecule and apply a bias voltage to the tip-sample junction, single electrons can tunnel between template and tip by hopping via nearly unperturbed molecular orbitals, similar to the working principle of a quantum dot gated by an external electrode. In our case, the charged atoms nearby provide the electrostatic gate potential that regulates the electron flow and the charge state of the molecule.”

(Top) STM images of phthalocyanine (H2Pc) molecule rotated from a neutral (50 pA, 60 mV; left) to −1 charged states (50 pA, −60 mV; centre and right) on InAs(111) surface using a ~4nm across hexagonal array of charged indium adatoms surrounding the H2Pc to create rotational energy minima, and (Bottom) schematic model of H2Pc rotation relative to the InAs lattice resulting in the electrostatic gating of tunneling to an STM tip vertical to the device. (Source: Nature Physics)

(Top) STM images of phthalocyanine (H2Pc) molecule rotated from a neutral (50 pA, 60 mV; left) to −1 charged states (50 pA, −60 mV; centre and right) on InAs(111) surface using a ~4nm across hexagonal array of charged indium adatoms surrounding the H2Pc to create rotational energy minima, and (Bottom) schematic model of H2Pc rotation relative to the InAs lattice resulting in the electrostatic gating of tunneling to an STM tip vertical to the device. (Source: Nature Physics)

The Figure shows that the diameter of the device is ~4nm, so by conservative estimation we may take this as the half-pitch of closest-packed devices in IC manufacturing, which leads to pitch of 8nm. As a reminder, today’s “22nm- to 14nm-node” devices feature ~80nm transistor gate pitches (with “10nm node” planning to use ~65nm gate pitch, and “5nm node” ICs expected with ~36nm gate pitch). Thus, these new prototypes prove the concept that ICs with densities 100x more than today’s state-of-the-art chips could be made…if on-chip wires can somehow connect all of the needed circuitry together reliably and affordably.
—E.K.