Tag Archives: design

Moore’s Law Smells Funny

…maybe we need “Integrated Cleverness Law”

“Jazz is not dead, it just smells funny.” – Frank Zappa 1973
from Be-Bop Tango (Of The Old Jazzmen’s Church)

Marketing is about managing expectations. IC marketing must position next-generation chips as adding significant new/improved functionalities, and for over 50 years the IC fab industry has leaned on the conceptual crutch of “so-called Moore’s Law” (as Gordon Moore always refers to it) to do so. For 40 years the raw device count was a good proxy for a better IC, but since the end of Dennard Scaling the raw transistor count on a chip is no longer the primary determinant of value.

Intel’s has recently released official positions on Moore’s Law, and the main position is certainly correct: “Advances in Semi Manufacturing Continue to Make Products Better and More Affordable,” as per the sub-headline of the blog post by Stacy Smith, executive vice president leading manufacturing, operations, and sales for Intel. Smith adds that “We have seen that it won’t end from lack of benefits, and that progress won’t be choked off by economics.” This is what has been meant by “Moore’s Law” all along.

When I interviewed Gordon Moore about all of this 20 years ago (“The Return of Cleverness” Solid State Technology, July 1997, 359), he wisely reminded us that before the industry reaches the limits of physical scaling we will be working with billions of transistors in a square centimeter of silicon. There are no ends to the possibilities of cleverly combining billions of transistors with sensors and communications technologies to add more value to our world. Intel’s recent spend of US$15B to acquire MobileEye is based on a plan to cost-effective integrate novel functionalities, not to merely make the most dense IC.

EETimes reports that at the International Symposium on Physical Design (ISPD 2017) Intel described more than a dozen technologies it is developing with universities and the SRC to transcend the limitations of CMOS. Ian Young, a senior fellow with Intel’s Technology Manufacturing Group and director of exploratory integrated circuits in components research, recently became the editor-in-chief of a new technical journal called the IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, which explores these new CMOS-fab compatible processes.

Meanwhile, Intel’s Mark Bohr does an admirable job of advocating for reason when discussing the size of minimally scaled ICs. Bohr is completely correct in touting Intel’s hard-won lead in making devices smaller, and the company’s fab prowess remains unparalleled.

As I posted here three years ago in my “Moore’s Law Is Dead” blog series, our industry would be better served by retiring the now-obsolete simplification that more = better. As Moore himself says, cleverness in design and manufacturing will always allow us to make more valuable ICs. Maybe it is time to retire “Moore’s Law” and begin leveraging a term like “Integrated Cleverness Law” when telling the world that the next generation of ICs will be better.

—E.K.

Reliable ICs from unreliable devices

Leave a reply

In an article published in the most recent issue of imec’s online magazine (http://magazine.imec.be/) titled “Chips must learn how to feel pain and how to cure themselves,” researchers Francky Chatthoor and Guido Groeseneken discuss how to build reliable “5nm-node” ICs out of inherently unreliable transistors. Variability in “zero time” and “over time” performance of individual transistors cannot be controlled below the “7nm-node” using traditional guard-banding in IC design.

“Maybe it means the end of the guard-band approach, but certainly not the end of scaling,” says Groeseneken in the article. “In our research group we measure and tried to understand reliability issues in scaled devices. In the 40nm technology, it is still possible to cope with the reliability issues of the devices and make a good system. But at 7nm, the unreliability of the devices risks to affect the whole system. And conventional design techniques can’t stop this from happening. New design paradigms are therefore urgently needed.” These researchers predict that industry will have to manufacture self-healing chips by the year 2025.

Self-healing chips could use the workload variation of the system for their benefit. Based on a deterministic predictor of the future, future slack is determined and used to compensate for the delay error and mitigate at peak load. (Source: imec)

The ultimate goal of imec and its academic partners is to develop a fully proactive parametric reliability mitigation technique with distributed monitors, a control system and actuators, fully preventing the consequence of delay faults and potentially also of functional faults. Said Catthour, “the secret to the solution lies in the work load variation of the system. Based on a deterministic predictor of the future, you determine future slack and use this to compensate for the delay error at peak load. Based on this info on the future, you change the scheduling order and the assignment of operations.” The Figure shows how self-healing chips can use future slack to compensate for delay error and mitigate at peak load.

—E.K.

MPU Cores and Legal Boors

Leave a reply

As reported by The Register, AMD has been sued by a customer who claims that the number of Bulldozer cores in some Opteron and FX microprocessor (MPU) chips are fewer than advertised. The claim is based on the argument that a “real” MPU core has it’s own floating point unit for calculations, and that consumers were misled by product claims. I am not a lawyer (IANAL) and have no connections to either side in this case, but AMD’s website (http://www.amd.com/en-us/products/processors/desktop/fx#) now clearly indicates that cores share a Floating Point (FP) scheduler.

The Figure shows that the confusion is due to the design of the Bulldozer microarchitecture wherein a pair of cores is called a module, and each pair shares a branch prediction engine, an instruction fetch and decode stage, a floating-point math unit, a cache controller, a 64K L1 instruction cache, a microcode ROM, and a 2MB L2 cache. The lawsuit claims, “Because AMD did not convey accurate specifications, tens of thousands of consumers have been misled into buying Bulldozer CPUs that do not conform to what AMD advertised, and cannot perform the way a true eight core CPU would (i.e., perform eight calculations simultaneously).”

This is analogous to someone buying a car with a V8 internal combustion engine, and then suing the manufacturer because there are only 4 fuel injectors and not all cylinders fire simultaneously. The claim that “true” multi-cores must be capable of functioning simultaneously is like claiming that “true” multi-cylinder engines must be capable of all cylinders firing simultaneously. AMD has officially responded with the statement that, “We believe our marketing accurately reflects the capabilities of the Bulldozer architecture which, when implemented in an 8-core AMD FX processor, is capable of running eight instructions concurrently.” There seems to be little legal difference between “simultaneously” and “concurrently” but IANAL.

Sure, there’s a technical difference and likely a slight performance benefit to direct fuel injection into each cylinder, but raw performance is only one aspect of the design trade-offs between performance and cost and reliability. Sharing 1 fuel injector between 2 cylinders often provides an optimum of performance/cost/reliability in internal combustion engines. Sharing 1 FPU between 2 logic cores seemingly provides an optimum of performance/cost/reliability in CPUs.

—E.K.