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Moving forward with Moore’s Law: Throughput of EUVL scanners

In order to bring EUVL scanners into high volume manufacturing (HVM) of computer chips, its throughput of 10 wafers per hour (WPH) needs to increase. That brings up three questions: how much do we need to increase the current throughput for HVM insertion, what needs to be done to increase throughput, and how quickly can this increase be achieved?
Throughput of EUVL scanner for HVM insertion
Imaging by EUVL scanner offers a higher k1 value than is available from 193 immersion (193i) based lithography. A higher k1 value results in better imaging and lower lithography process complexity, hence the attraction of EUVL as an optical projection lithography.  Today, 193i scanners are used in a double pattering process to print the smallest features needed in HVM. Toward 14 nm and smaller nodes, if EUVL is not ready, chipmakers will need to use quadruple patterning with 193i scanners, combined with increased optical proximity correction (OPC) and design rules restrictions to print increasingly smaller features. This is not an attractive option for chipmakers, hence their increasing emphasis on EUVL readiness. As manufacturers evaluate available technology, switching from double patterning-based 193i to EUVL, throughput is most often mentioned as the criterion for evaluation.
As printing of circuits is a sequential process, in double patterning (DP) the same wafer is exposed twice in a 193i scanner. Between the two exposures, there are many additional processing steps to enable the DP process. Hence, we need less than 50% throughput from an EUVL scanner (as compared to 193i scanners) to achieve a given feature size. In the case of quadruple pattering, an EUVL scanner needs less than 25% throughput to compare with an immersion scanner due to the four exposures.  After accounting for the additional processes of deposition, etch, ash and metrology, the equivalent throughput of an EUVL scanner may become less than 40% and 20% to compete with double and quadruple patterning, respectively. Thus, to match the throughput of a 200 WPH 193i scanner for DP process , we need less than 80 WPH and 40 WPH from an EUVL scanner. This is an important point, as it’s often said in press that an EUVL scanner must reach the throughput of a 193i scanner to be considered equal. (Cost of Ownership wise, the Lithography team of the International Technology Roadmap for Semiconductors (ITRS) has already shown that EUVL is more cost-effective than 193i DP for next generation lithography (NGL) [1]).
How to increase EUVL scanner throughput
Of course, EUVL scanners still need to boost their throughput numbers from the current 10 WPH.  For economic reasons, it’s best to have throughput as high as possible from an EUVL scanner.  Although much focus is placed on sources for improving throughput, other things can be done to increase the productivity of an EUVL scanner.
To better understand the challenge, let’s start with a model that estimates throughput of an EUVL scanner for 1) a given source power, 2) scanner parameters, and 3) reflection/transmission efficiency of various components [2]. EUVL scanners are not very efficient in transferring photons from source to wafer. Hence, in addition to increasing the number of photons available to the scanner, we can also work to increase its transmission. It is important to note the relationship of scanner throughput to scanner’s overhead time and resist sensitivity. [2] For example, for 50 W of source power at intermediate focus (IF), 20 mJ resist will allow 30 WPH while 10 mJ resist will allow 55 WPH. For a 10 mJ resist at 80 WPH, we need 115 W of power for 18 s overhead time, while for the 10 s overhead time we need only 50 W of power! [2]
There are additional factors that can help increase throughput. By decreasing the resist sensitivity to out-of-band radiation, the need for spectral purity filters may be eliminated. Reflection of mask as well as effective reflection of optics can be increased as well. Optical throughput of the NXE3300B is supposed to be 50% more than the NXE3100 [3] so there is already progress in increasing scanner throughput.
EUV sources are a difficult challenge due to the inherent complexity of reliable and repeatable generation of high temperature plasma of 40 eV for a production environment.  Current EUV source conversion efficiency (CE) is only 2 % (i.e., 2% of input energy is converted into EUV photons). Of these photons, only about 10% can be collected due to the limitations of collector optics, debris mitigation and spectral purity filters. We need improvement in each of these areas to enable higher power and increased throughput. CE of 5.5 % has been demonstrated recently, larger collectors are being developed and debris mitigation techniques will continue to improve – all allowing more photons to reach the wafer.
How higher scanner throughput can be achieved quickly
There is no magic bullet, so lots of innovative solutions are needed to lessen various loss factors to reach 100 W of source power. Beyond that, we may need different approaches to key source components  such as fuel delivery. In meetings at the 2012 International Workshop on EUV and Soft X-Ray Sources (Dublin, Ireland, October 8-11), the largest annual gathering of EUV source experts, we can expect discussion on some of these key topics in EUV source development. The workshop will include:
·          Several papers on how to increase CE of sources for both EUV and beyond BEUV ( 6.x nm) LPP sources
·          New designs to allow higher power DPP sources
·          Data on the latest SPF of up to 80% transmission, improved collector optics, and other topics
I look forward to seeing the latest results from the industry’s source experts and will report them on this site.
In summary, I expect a rather slow but steady increase in EUV source power, and I’m still on record as predicting enough throughput by 2014 to allow adoption of EUVL scanners for HVM by leading chipmakers.
References:
1. Lithography Chapter, International Technology Roadmap for Semiconductors (2009).
2. Chapter 3, “EUV Source Technology,” in EUV Lithography, Vivek Bakshi (Editor), SPIE Press 2008, for discussion of a general throughput model for an EUVL scanner.
3. Rudy Peters, ASML presentation at the 2011 EUVL Symposium.

Moving forward with Moore’s Law: Analysis of EUVL investments by chipmakers

There have been recent announcements by leading chip-makers of very large investments in ASML.  The company has received investments of  3 billion euro in equity and 1.3 billion euro for R&D for its next-generation EUVL and 450 mm tools. The first announcement was made by Intel in July, followed by similar statements from TSMC and Samsung.

These investments are obviously a very good thing for ASML. They demonstrate chipmakers’ confidence in the company and willingness to support ASML in producing leading-edge scanners. ASML took a risk by investing heavily in EUVL, but it seems to be paying off in terms of financial support and increasing orders for EUVL scanners. But there is more to this story, which I will explain below.
1. While Intel invested 3.3 billion euro in ASML, it simultaneously made a much smaller investment in Nikon to develop 450 mm scanners! This further indicates ASML’s growing importance as the ONLY supplier of leading-edge EUVL scanners, along with its being the world’s # 1 scanner maker. This is a significant change in the industry model, which has been used to having two suppliers for critical scanning tools. Having only one supplier for the most critical chipmaking equipment poses some risks for manufacturers, and that may be the reason for ASML’s equity co-investment program – although the company says that “voting rights of customer shareholders are restricted.”  Also, ASML says the “results of these development programs will be available to every semiconductor manufacturer with no restrictions,” hence it’s a good thing for the entire industry.
2. Intel, TSMC and Samsung will be the first recipients of EUVL scanners and will be ahead of others in making advanced semiconductors –  ensuring their positions as leading-edge chip-makers. Other chip-makers planning to use EUVL – Toshiba, GlobalFoundries, IBM and Hynix – most probably will be next in line for scanners.
3. 450mm is looking like a sure thing, and the recent investments show that it’s likely next-generation EUVL scanners will support 450mm. The transition to 450mm is going to be very expensive, but Moore’s Law must move forward and we have to depend on the known enablers of increasing wafer size and decreasing source wavelength. I mentioned in the press in 1999 that “transition to 300 mm is not optional.” In the same article, I estimated the next wafer size as 450 mm. Almost a dozen years later, the 450 mm transition is running full speed! No one said the route to Moore’s Law is going to be easy, but this may be the only road we have and the industry will need to adjust to new economic models.  
4. Although chipmakers have invested heavily in ASML, the supplier integrates but does not make EUV sources. So 1.3 billion euro will go toward developing parts for ASML’s tools. Hence, it is not clear how this investment is going to help with the issue of source power.
Do EUVL investments adequately address the technical challenges?
EUVL early insertion by 2014 is not without risk. Some things about the industry’s investment strategy will need to change if we want EUVL in high-volume manufacturing (HVM) sooner rather than later. To insert EUVL into HVM, we need not only technical viability (proven for a few years) but also cost benefit (not yet fully proven).  EUVL can print better than competing technologies but must print with sufficient yield to a better or comparable cost to competing technology – double or quadruple 193 nm immersion.
In order to discuss this further, let’s do a quick review of the current leading challenges of EUVL:
#1 Source (average power, dose stability and uptime)
#2 Mask (defect density, inspection tools and sources for inspection tools)
#3 Resist (line edge roughness [LER], sensitivity and resolution)
Optics is a fourth issue, but its challenges are considered well addressed by Carl Zeiss. Assembly of EUVL scanners themselves are well in hand at ASML.  Other challenges also will be overcome, but we need an order of magnitude improvement to deliver 100 W sources.
It should be noted that in addition to its recent investments, the industry also has committed $150 million in the last two years for mask inspection tools, and this year announced more support for developing high numerical aperture (NA) EUV optics.
However, the investment in the #1 issue of EUV sources has been a BIG ZERO. The industry’s assumption has been that source suppliers will address this challenge and no other action is needed. With billions of dollars going into solving lesser issues, this investment approach is bit flawed. No wonder EUVL scanners are delayed – how can they be otherwise? EUV source suppliers are working very hard and investing heavily on their own, but this is a difficult challenge and suppliers will benefit from new solutions that they can engineer into products.  Sources have not met the needed 100 W target, and I think it will take few more years to get there. I doubt that higher power targets will be met with current technical approaches, and without fresh investment in new technologies.
Chipmakers can continue to ignore this topic, but they have already paid a price in terms of the delay in HVM insertion, and will continue paying with further delays in EUV readiness and lower throughput as they enter into HVM. I think there are insertion paths for EUVL scanners with < 100 W sources, but the ROI will not be very good. Can’t we do better?
Some will say that chipmakers are doing all they can. EUV sources are plasma-based, and chip manufacturers are not experts in plasma physics and don’t fully know what to do with it. However, they have funded EUVL R&D in other areas through various consortia with very significant budgets. Yet no one has any R&D programs to generate new solutions for source technology. In short, chip-akers have a flawed investment strategy which is going to continue costing them. I believe that the industry model on this issue must change. Chipmakers need to be proactive in ensuring that sources not only deliver power today, but also that there are enough new ideas in the pipeline so that tomorrow’s 250 to 1000 W sources will be available when we need them. They are already spending hundreds of millions in R&D; why not invest in generating new approaches to our #1 issue?
Conclusions
EUVL investment is growing, but the source challenge remains. Although EUVL’s place is set as the leading technology for next-generation lithography (NGL), we need to know what will happen to EUVL insertion timing if sources continue to develop at their current rate. How can we bring EUVL into HVM sooner? These are topics on which I will share my opinions in future blogs at this website.

EUVL workshop focuses on source power, timing

At the recently concluded 2012 EUVL Workshop (held June 4-8 in Maui, HI), attendees shared their latest technology developments and discussed ways to address the challenges of EUVL insertion into high-volume manufacturing (HVM). The Workshop’s low-key, R&D-focused setting allowed detailed discussions and a fresh overall look at many of the most pressing EUVL manufacturing issues.  
Keynote talks

Yan Borodovsky, Director of Advanced Lithography and Senior Fellow at Intel Corporation, gave the first keynote talk of the Workshop.  He identified reduction of edge placement error (EPE) as the key benefit expected of EUVL over competing optical techniques. He also pointed to a need for significant OPC infrastructure improvement for correcting 3D mask effects. Borodovsky believes there is no benefit in developing higher resolution EUVL through numerical aperture (NA) > 0.33 increase or wavelength reduction to (λ) = 6.8 nm unless resist stochastic effects can be reduced ~2X from current best levels of chemically amplified resist (CAR) platforms.

He estimated that 60 mJ/cm2 resists will be needed for printing all of 20 nm contacts on the chip with 5% exposure latitude at 98% probability in order to overcome contact exposure dose uncertainty due to stochastic effects introduced by EUV photons shot noise. Because ASML’s future tools utilizing 15 mJ/cm2 resist will require 250 W of source power for throughput of 100 wafers per hour (WPH), he expects power requirements will rise to 1000 W in order to enable defect free contact printing at EUV insertion or closely thereafter. Of course, new ideas and concentrated efforts are needed to develop and implement such sources, and he encouraged us to also look at alternate source technologies.

Soichi Inoue, general manager of EIDEC, a consortium for developing EUVL infrastructure, outlined what he called “persistent efforts to overcome challenges of EUVL.” EIDEC believes that EUVL is the mainstream technology from the cost and extendibility viewpoint. He said source power needs to increase dramatically and reach set targets (main and pre-pulse laser, debris mitigation, droplet generation, IR reduction) with sufficient stability. He added that resist and mask inspection tools, now in the precompetitive arena, could be more effectively developed through a consortium approach.

EUVL Insertion and EUVL Extension Panel Discussion

A panel discussion on EUVL insertion and extension was moderated by Sushil Padiyar of AMAT. Borodovsky noted that Intel will adopt EUVL when yields and cost of ownership (COO) compare well with those of 193 nm immersion (193i) technology.  In his opinion, complementary cuts and via patterned by EUVL for logic and DRAM contact lithography will drive early EUV HVM adoption. Even if the initial cost is large, investments can be recovered if the tools can be used for a long time.

Takeshi Komo of Toshiba focused on mask-related issues as barriers to EUVL implementation. He thinks that an aerial image measurement system (AIMS) for EUV will not be available at the early stage of HVM. Thus we will use 3D-scanning electron microscopy (SEM) and litho simulation as alternatives. He also noted the need for mask R&D for high NA and Beyond EUV (BEUV) wavelengths.

Pawitter Mangat of GlobalFoundries believes that 2016 is the earliest opportunity for HVM insertion, with 2017 most probable for his company. He also believes the need to match productivity with 193i tools for EUVL insertion and sees success as dependent on source power.
The Workshop presented its Outstanding Contribution Award was to EUV Technology, a company that has been making tools to support EUVL infrastructure development since 1997. The award was presented to President and CEO Rupert Perera by Greg Denbeaux of the University of Albany-SUNY, on the behalf of the Workshop. Greg mentioned his own positive experience with EUV Technology tools and shared positive comments from IMEC, whose engineers admire the creative design and simplicity of the supplier’s tools. Attendees voted to give the Workshop’s Best Poster Award to High CE Technology for HVM EUV Source, by Hakaru Mizoguchi and Shinji Okazaki of Gigaphoton. 
Other significant results:

–      Hiroo Kinoshita of the University of Hyogo, reporting on the feasibility of BEUV systems at 6.x nm, pointed that at BEUV wavelengths, transmission and penetration depth for BEUV CAR resists increase, but resist sensitivity decreases.
–      Takeshi Higashiguchi of Utsunomiya University reported conversion efficiency (CE) of 0.6% for gadolinium (Gd) plasma at 6.x nm, using low-density Gd targets. He believes that droplet generation for Gd, the leading source material for BEUV, may be difficult to achieve.
–      Shannon Hill of NIST reported that the carbon contamination rate of EUV optics may not increase proportionately with power. At higher power, however, carbon may be more difficult to clean with atomic hydrogen since the density of deposited carbon approaches that of graphite.
–      Perera of EUV Technology described differences in outgassing and carbon deposition for EUV resists subjected to electronic beam (e-beam) and EUV sources. His are the first results showing that resist outgassing is not the same for these two energy sources, thus challenging current e-beam based resist outgassing testing protocol.
–      Sergey Yulin of Fraunhofer gave the Workshop’s EUV Optics Technology review. He mentioned the loss of Ru, TiO2 and Nb2O5 cap layers in the atomic hydrogen based cleaning process for carbon removal due to high diffusion through cap material. He believes that the lifetime of EUVL optics remains an issue for the EUVL community.
–      Yuriy Platonov of RIT presented new reflectivity data for RIT’s collector optics. The reflectivity variation has improved to +/-0.5% PV across the area of ~400mm in diameter, with maximum reflectivity of 67% for the collector optics. For Illuminator optics, he showed an average 66% reflectivity. He noted the reported reflectivity of 49.8% is still the best measured value for RIT’s multilayer (ML) for 6.x nm.
–      Gigaphoton updated results of their Sn LPP source performance to 90 K Hz, 30% duty cycle, and 4.7% CE. This is highest CE reported to date for a commercial Sn LPP source.
–      Akira Endo of Waseda University and HiLASE Project shared data on reducing debris and increasing CE. He reported experimental data showing that picoseconds (ps) laser is better for pre-pulse than nanosecond (ns) laser. He pointed to the need to improve beam quality for 10 µm spot size focusing and reduction in pedestal in CO2 laser pulses, which pre-heat the target.
–      Takahiro Kozawa of Osaka University gave an overview of EUV resist. He noted that the advantage of high NA in EUV tools is lost due to increased transparency in the resist. For 6.x nm lithography, he said, we need high absorption resists – an assertion supported by results from Kinoshita, who reported low absorption at 6.x nm for EUV resists).
–      Describing his work on improving EUV resists, Takeo Watanabe of Hyogo University pointed that the ionization reaction and photo acid generator (PAG) excitation must be taken into account to understand and potentially increase EUV resist sensitivity.
–      Tooru Kimura reported on EUV resist development at JSR Corporation. He was able to reduce the acid diffusion length of EUV resist by 86% by changing the PAG backbone to a rigid structure, resulting in higher resolution. He showed that the development of underlayer for silicon hard mask helps with pattern collapse issues. He also noted that for CAR, short development time helps with the process window. He provided results for 16 nm HP with 3.3 nm line edge roughness (LER) for 16 mJ resists.
–      Padraig Dunne, NewLambda technologies, described his EUV source for metrology. This source has an etendue of 10-4 mm2sr, and brightness of 80 W/mm2sr. During 24-hour continuous operation, he measured 34 x 55 µm source size with CE of > 1%.
–      Debbie Gustafson demonstrated the performance of Energetiq’s 6.7 nm DPP source, which is being used for BEUV resist development. It is based on transitions of Ne VII at 70 mW of power.

Additional analysis and discussions on the topic of of EUVL Insertion Timing and EUV sources will be presented in this blog in the coming weeks. Proceedings of 2012 EUVL Workshop are available for download at www.euvlitho.com.

SPIE -JM3 Journal publishes special issue on EUV lithography sources

During the 2011 SPIE Advanced Lithography Symposium (SPIE), Tony Yen of TSMC proposed to the editorial board of The Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3) a special issue on EUV sources in which experts could share new ideas on how to further advance the EUV source technology. Chris Mack suggested that Tony and I co-edit this issue, which I happily agreed to do as EUV sources are of much interest to me. EUV source power was as critical an issue then as it is today. Knowing that power requirements would only increase for next generation scanners,  we also wanted to hear from source experts on how far we can take the current technologies, and what to do next to get to power levels of 250 W (or more) at intermediate focus (IF).

After more than a year of peer reviews of submitted articles, we will  publish the  JM3 special issue in July, with 23 papers covering such topics as laser produced plasma (LPP) and  discharge produced plasma (DPP) sources,  mask metrology sources, modeling source components (debris mitigation, spectral purity filter [SPF] and lasers) and papers on many alternate concepts for EUV sources.  Although  all of them are well worth reading, I want to highlight papers that analyze technology limits, offer solutions on how to advance current technology,  and provide alternate EUV source concepts.

DPP sources have some definite advantages. They are simpler and cheaper than LPP, and I can personally testify that they can run continuously for eight hours and more. However, since 2007, the power for installed DPP sources has remained in the 7-10 W range, although their reliability has improved. My guess is that thermal mitigation is still the issue. Over the last five years, I have seen convincing data on power scaling potential for these sources, and I see even more conclusive scaling data now. However, I will withhold judgment on how well these sources can scale in power, until end customers report on their long term operation at higher power.

A paper by Koshelev et al. on metal jet offers an interesting approach to DPP power scaling.  It was shown to be more than a concept when he provided experimental results at the 2011 Source Workshop. Koshelev expects to soon scale his source power to 800 W at source (80 W at IF) by using 32 kW input and 2.5% conversion efficiency (CE), and details his new DPP approach in this issue. As with all new concepts, it will need engineering work to become a commercial product.

LPP source power has improved from the mW range in 2007 to ~10 W today. The physics of scaling seems straightforward for these sources as well. Now that many LPP sources are in the field, much more attention is paid to them today. But in fairness, I must withhold judgment on the power scaling potential of LPP sources as well, until I see more field data from customers.

Papers from Toshio Tomie and Gerry O’Sullivan provide excellent reviews of LPP technology and offer opinions on its limits. Also worthwhile is a theoretical paper from Koshelev et al. on distributed targeting for LPP (Akira Endo expanded on this concept in his talk at the 2011 Source Workshop). The distributed target approach is interesting  and promises higher CE and better debris control, but it needs to be brought into practice and then into manufactured products.

Alternate concepts for EUV sources are explored in papers on EUV lasers, the Laser Compton effect, tabletop synchrotron, inverse laser Compton effect, EUV lasers, electron cyclotron resonance (ECR)-based plasma and free electron lasers (FEL) lasers. Of these approaches, FEL, tabletop synchrotrons, and ECR plasma papers claim the ability to scale up for high EUV source power requirements.  Other alternate concept papers focus on metrology applications. All of these papers provide experimental proof at some level.

An FEL paper delivered by William Barletta at the 2012 SPIE Advanced Lithography conference claimed a 500 W source with an estimated cost of $100 million. I support serious examination of these concepts, most probably by a group of experts that include end users as well as scanner makers. Even so, it’s difficult to find funding for alternate technology development when conventional suppliers are claiming that such high source power capability lies within reach of their technology in the near future. But if we do not see significant power scaling results this year, a serious review (not development) of alternate technology would be desirable. We owe it to ourselves, and it is very much worth the effort, to at least do a serious assessment. In any case, I encourage you to read the papers on current and alternate concepts and share your comments with me.  

EUVL insertion timing, readiness and scaling

Currently, EUV source suppliers are working on increasing source power for EUVL scanners. The ASML 3300 Series scanners, designed for high-volume manufacturing, are scheduled for delivery later this year. Most probably, high power sources will not be quite ready in 2012 to support HVM requirements, and will need to be upgraded on site.  So the questions still needing to be answered are:

  • When will these HVM-level EUVL scanners be used to make products?
  •  What will trigger the industry-wide insertion of EUV scanners in HVM production lines?
  • Will it be a certain source power level, throughput, yield, or cost that raises the confidence of users?
  •  Who will be the first users of EUVL in HVM, and for what products and which node?

Similar questions can be posed for EUVL mask defect metrology tools. With scanners, we have an approximate throughput model that is widely known, so we can estimate throughput and cost of ownership at a given source power level. This is not quite so for mask defection inspection tools, as they are still being designed and need brighter EUV sources.  The leading option for sources for defect metrology tools (and the only one for a 24 x 7 operation) is the Energetiq Xe discharge-produced plasma (DPP) source. However, current performance levels for this source allow only development of prototypes.

In my opinion, memory makers probably will be the first adopters of EUVL technology. Throughput as high as 40 wafers per hour (WPH) will convince chip-makers that EUVL is a viable technology, and sales of EUVL scanners and associated tools and products will start soaring. Mask defect metrology tools will remain unready for HVM until a brighter source becomes available. We can expect a déjà vu: low throughout metrology tools waiting to be upgraded.

In the case of high-power sources, we have three major suppliers with the commitment and resources to continue development. Not so for metrology sources, and the end customers will have only themselves to blame this time. I have read that end users are spending up to $150 million on metrology tool development, but not a dime on developing EUV sources for metrology. A source supplier told me that promises of support for metrology source development have not materialized,  even though EUV sources for metrology are the weakest link in the chain. With virtually all of the money going to engineering development of tools and none to this weakest link, the results are very predictable.

As the industry Roadmap moves to smaller nodes of resolution (10 nm and below), will we choose EUVL with double patterning, or change the wavelength once again and move toward Beyond EUV (BEUV)? Gadolinium (Gd) at 6.8 nm is the current leading option for BEUV source material, as we saw from the latest development results on source and optics in last year’s EUVL Source Workshop. Increased optical proximity correction (OPC), off-axis illumination (OAI), and double patterning may require more power at these nodes than 13.5 nm sources can provide, so it might make sense to move to BEUV. For BEUV, we have a leading source material for multilayer (ML) optics and resist development has already started.  We also can apply lessons learned from 13.5 nm to BEUV tools, although more infrastructure work will be required.

These and related topics will debated by panelists from Intel, GlobalFoundries, Toshiba and Applied Materials (AMAT) at the 2012 EUVL Workshop being held June 4-8 in Maui, Hawaii. The panel will be moderated by Sushil Padiyar of AMAT. The Workshop also will feature many papers on BEUV and EUVL R&D from some of the world’s leading researchers. I will be blogging here about these new developments after the EUVL Workshop.

SPIE 2012: The Spring of EUVL

The SPIE Advanced Lithography EUVL Conference is usually held close to spring, but was pulled into week of Valentine’s Day this year. Fittingly, 2012 may be the year of EUVL’s early spring. This year even the loudest criticism of EUVL was not about “if” but “when,” and the predicted range of insertion for EUVL in high volume manufacturing (HVM) is now 2013-15. (Samsung wants to start using EUVL in 2013 and Intel is planning to use EUVL its fabs in 2015). Discussions are now more focused in the product development area.

Status of EUVL
The EUVL conference started with an invited talk from IMEC, which presented process development data from ASML’s NXE3100 beta level EUVL scanner. The scanner’s throughput is now 5 wafers per hour (WPH) for ~7 W of power. They are patterning at 16 nm half-pitch (HP) using dipole illumination, and can get 5 nm machine-to-machine overlay in order to mix and match with another ASML 193 immersion (193i) scanner.

Scanner Development
ASML now has six NXE3100 scanners operating in the field, five of them in process development and one in qualification. Line and space (LS) of 16 has been achieved with a 33 mJ resist. These scanners currently add 0.05 particles per reticle pass (or 1 particle in 20 passes). This recent 20x improvement is critical, since an EUVL mask does not have a pellicle.

ASML plans to ship the HVM version of their NXE3300B scanner in the second half of 2012. For this tool, numerical aperture (NA) will go to 0.33 from 0.25, with 4% flare optics. This tool has specs of > 69 WPH, and I am sure source availability will drive this number. ASML also presented their EUVL roadmap to 10 nm HP and below, utilizing double patterning (DP) or a switch to 6.8 nm.

Source Progress
EUV source remains the key driver of scanner throughput and EUVL’s introduction into HVM. Current power reported for NXE3100 in the field is 7W for Xtreme and 10W for Cymer. Gigaphoton has a 7W source in their lab and plans to ship a higher-power source later this year for integration. Xtreme, which has shipped a 20W source for NXE3100B and is working on 50W-100 W sources, described in detail their new electrode design for high-power sources.

Cymer is working to upgrade its current sources in NXE3100 to 20W and plans to have 50W sources in Q3 this year. The 20W upgrade is based on a double pulse approach, which has been proven effective for many years. So this upgrade should be successful, although perfectly aligning two lasers, both pointing at 30 microns droplets moving at the speed of 50 k Hz with 100% accuracy is no small task.

Gigaphoton plans to ship 50 W sources in Q4 this year. They presented 4% conversion efficiency (CE), the highest so far for laser-produced plasma (LPP), and progress on their debris mitigation design. I am looking forward to their sources in the field this year.

In terms of delay in source technology development, the main issues for LPP seems to be debris mitigation and droplet stability, plus engineering to ensure 24 x 7 operation. For discharged-produced plasma (DPP), the issue is thermal mitigation.

Two years ago, ASML introduced “exposure power” as a new way to describe source power. The term is based on the concept that due to plasma stability and losses from spectral purity filter (SPF) use, only half of EUVL source power at intermediate focus (IF) reaches its target. In other words, 100W of source power at IF produces only 50W of usable “exposure power.” I believe that as sources make progress, the gap between IF and exposure power will get smaller. However, the difference was not made clear in presentations, leaving us to guess whether the 20W or 50W that suppliers plan to have in the second half of 2012 is exposure power or IF power.

EUVL and the Art of Auto Repair: EUVL Success Stories
Last year my friend Bob tried to fix a small issue with my Suburban, the auto with the now famous “EUVL” license plate. Bob is always working on cars and expected this repair to be a piece of cake. But after several tries he gave up, saying: “Nowadays cars are too complex, now you need a computer to fix anything.” If only it had been an older model, he would have been able to help.

Not too long ago, the EUVL alpha scanner was criticized by an expert as looking “like you rolled an electromagnet through an automotive junkyard,” while others called it a “science experiment.” Now that early prototype has evolved into a smooth machine, although still a slow one. Stepping away for a minute from the issue of low throughput due to source power, I do not hear any complaints about the scanner, which is a very complex machine in itself. Lithography in vacuum seemed impossible to many not too long ago. This is an incredible machine: a scanner that was never supposed to work at all now performs so well that the tool itself is apparently not an issue.

Unfortunately, I did not hear any praise of ASML (who integrate sources but do not build them) for all that they have achieved so far. Maybe that’s because this year’s SPIE AL seemed pretty tense. One of my colleagues, who has been coming to these meetings for years, said he did not hear anybody laughing or joking over the entire three days. Instead, people were walking around as if the world was going to end in 2012, per the Mayan calendar.

When I started in the EUVL business, sources were not yet the main challenge, but optics contamination, optics quality and masking without a pellicle were said to be limitations that would doom EUVL. Now these former threats have been tamed. Yes, the technology is lot more complex, but increasing complexity is part of both life and a next-generation, better machine.

Comparing Apples to Oranges: Looking Beyond Throughput to System COO
EUVL has attracted a fair bit of criticism, and I believe that comes from its being the front runner of NGL technologies. One of most frequent criticisms of EUVL is throughput. While 193i scanners can process 200 wafers per hour, EUVL is at 5 WPH and is expected to climb to just 40+ this year. So how can EUVL ever compete with immersion Lithography?

The answer lies in the simple fact that we need to consider the throughput and cost of ownership (COO) of the entire lithography module, rather than just looking at the exposure tool. Double patterning has more than doubled the cost and processing steps, resulting in some tools with low throughput. A COO model accounts for this. And even ASML, which sells lots of 193i scanners, has said that it is much more cost-effective to go with EUVL. So the real question we should ask is, at what throughput will the COO of EUVL become the same or less than 193i? Although I have not seen an analysis of this question, I have heard that 40 WPH throughput will be a favorable turning point for EUVL, and at 60 WPH most chip-makers will adopt it in HVM. We are not at these throughputs yet, but how far along are we really? Answers will depend on our assessment of rate of progress of EUV Sources.

Critical Issues: Do We Know How to Make HVM EUV Sources?
The most positive aspect of EUV source status is supplier commitment. Gigaphoton and Cymer, who also supply light sources for 193 nm lithography, are investing heavily in EUV source development. Ushio, another light source supplier, is also very committed and investing in the source business. However, to move to next generation sources, we may need innovation and new technology in addition to supplier commitment.

At the November 2011 Source Workshop, EUV experts gathered to discuss how we can get to higher power levels for EUV sources. It was time for honest introspection. Konstantin Koshelev, whose lab built original prototypes for Sn DPP, delivered a plenary talk entitled, “Do We Know How to Make HVM EUV Sources?”

The current design of DPP introduces high thermal load on electrodes, and droplet-based tin delivery systems introduce debris and stability issues which create great engineering challenges. Koshelev’s proposals for new DPP and LPP design, along with many other ideas presented in the workshop, need careful consideration and support for further exploration. Based on current publications, I see only Gigaphoton actively involved in R&D to continue looking for new ideas for their next generation sources.

How Do We Address the Critical Source Power Gap to Bring EUVL to HVM as Soon as
Possible?
EUVL has attracted attention as it is a multi-node technology, but it will need more and more power at coming nodes. I can get behind 100W or even plans to get 150W. However, I cannot see how the 250W or 350W levels on EUVL roadmaps can be achieved without new technical approaches.
Leading consortia have left source development to the suppliers, which are great engineering firms but not necessarily places for developing new technology. Even after years of delay, there is no change in policy to address this critical gap. Lots of money gets spent every year to help suppliers make progress on various EUVL-related issues, but almost nothing goes to develop EUV sources which are #1 issue for EUVL.

This is surely insanity. You will not hear a supplier say, “I do not have the technology for next generation sources and need help," but many will claim, "I have the technology and just need more money and time.” How can a supplier do otherwise, when their competitor is promising "lots of power tomorrow with proven technology?"

Our industry needs to step up and say, “Enough of this. Let’s generate more technical solutions and make them available to the source suppliers so they can increase source power.” With a steady stream of funded innovation flowing from Universities and National Labs, I am confident existing suppliers will be able to take care of source power needs.

Here are my ideas on what needs to be done to increase and sustain EUVL technology development:

(1) Create a consortium that focuses on development of next generation EUV source technology. We need innovative solutions to address debris, thermal management, low conversion efficiency, out-of-band (OOB) radiation, and plasma stability to take us to 500W source designs. I believe that a $10M annual budget for three to five years is needed for such studies. We can have Small Business Innovation Research (SBIR)-type programs where solutions that meet technical criteria move on the next stage to receive additional funding from the consortium and industry. Which existing consortium can take on this challenge?

(2) Although EUV double patterning combined with optical proximity correction (OPC) is suggested for taking EUVL scanners to the end of the Roadmap, the power required is too high at 13.5 nm but can be reduced by changing the wavelength to 6.7 nm. Work has already started on 6.7 nm optics, sources and resists (see workshop proceedings at www.euvlitho.com), but we need to put a lot more emphasis on this wavelength switch and be ready to provide solutions that can produce commercial products.
(3) Perhaps most important is that Nikon has slowed down its EUVL development work. They, like ASML, developed two alpha level scanners but chose Xe DPP sources over ASML’ choice of Sn DPP sources. Xenon plasma source size is greater than a tin plasma source; hence, Nikon tools hit power limits sooner than ASML’s alpha demo tool (ADT).

Currently, Nikon has programs in optics and contamination, but they are not developing an EUVL scanner. They are very capable of doing so, but will not be able to catch up with ASML if they wait any longer. I have been known to say that you do not get a second chance in this business. Is it good for the computer chip industry to have only one supplier for its most critical tool? As this question directly relates to corporate bottom lines, chip-makers should be concerned about answering it.

Lotus Bet Update
During the conference, a couple of colleagues congratulated me after they incorrectly assumed that I already have the Lotus keys from my wager with Litho Guru Chris Mack. (Chris took the dubious side of a bet that there would be no papers presented on EUVL in 2011, or that EUVL would not be in HVM by 2013-14). There appeared to be no shortage of EUVL papers in this year’s conferences, and audiences spilled over from EUVL sessions until they were moved to larger rooms. I am still confident that EUVL will be in HVM soon. By the way, the Litho Guru was praised highly by at least one supplier for his contributions to the development of EUV resists, and for his help in reducing line edge roughness (LER), a critical challenge of EUVL.

As a leading litho expert, I am confident that Chris and many others in the 193nm litho community can continue doing much to help EUVL, especially in the areas of LER and EUVL resist development. I look forward to our becoming “one big, happy family” of litho experts as we work together on the latest optical lithography that will take us to the end of the Roadmap.