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At The ConFab 2014: The Outlook for the Semiconductor Industry

The semiconductor market will continue at a steady growth rate for the next several years. For a semiconductor company to achieve significant growth in this ultra-competitive environment, it needs to identify market opportunities and predict the future, in terms of markets, both regionally and globally, anticipate technological advancements, as well as envision new applications. At The ConFab in June, Session 1 will provide an overview of these critical issues.

The presenters will be:

Vijay Ullal, COO, Fairchild Semiconductor

Dave Anderson, President and CEO, Novati Technologies

Gopal Rao, Senior Director Business Development, SEMATECH

Adrian Maynes, Program Manager, F450C

Bill McClean, President, IC Insights

Here’s an overview of what each presenter plans to cover:

The Economics of Semiconductor Manufacturing and the Escalating Cost of R&D

Vijay Ullal, COO, Fairchild Semiconductor

While innovation in semiconductor technology is driving change in industries from automotive to mobile, and the sophistication of computers, mobile devices, automobiles, industrial systems and consumer goods evolves, greater pressure is placed on semiconductor research and development (R&D) as well as Supply Chain Management (SCM). Now, the bar has been raised from not only delivering leading-edge technology, but also to delivering far greater value to an organization. This presentation will use examples of to focus R&D as well as revitalize your supply chain in order to highlight your competitive advantages, and better meet these market place demands by moving beyond the “product sell” to an approach that focuses instead on the key attributes customer’s value.

More-than-Moore: A New Era of Innovation

Dave Anderson, CEO, Novati Technologies

The semiconductor industry has focused on Moore’s Law for more than 40 years in its quest for ever shrinking geometries to squeeze more transistors on a chip and improve device speed and performance. Digital microcircuits have benefited immensely from this extreme scaling but, with fewer companies having the ability to support further scaling, More-than-Moore (MtM) has emerged to apply decades of semiconductor process knowledge to novel applications to produce state-of-the-art biochips, sensors, actuators, imagers and more. Perhaps most importantly, MtM technology is enabling companies to build these components more cost-effectively and with better performance and smaller size than ever before.

Providing a significant advantage over traditional volume foundries, a new wave of boutique nanotechnology development centers is in a unique position to integrate new materials with custom processes. This provides a rapid acceleration of development and production for world-leading ideas and breakthrough MtM products.

The result is a new era of innovation that couples the best of the past with future demands to create valuable applications and markets. The era for enabling the most rapid, but affordable, new product development and deployment has begun.

Enabling the Supply Chain to Accelerate R&D

Gopal Rao, Senior Director of Business Development, SEMATECH

There is a push/pull market energy that is now, more than ever, influencing the device makers, suppliers and the consumers who are thirsty for innovative mobile computing and connected devices. The IC industry has relied on a push based roadmaps to bring products to market. It is important that we acknowledge that the consumer appetite for innovative and cool products has created a pull system that may be considered a roadmap. The challenge facing the whole IC industry is how to recognize, rationalize and leverage these push/pull roadmaps. This talk examines this IC industry challenge and opportunity, specifically in moving the vast supply chain to feed into this fast moving market. The pace of R&D through entire supply chain is essential in staying ahead of the curve and driving down cost of technology and manufacturing. Radical, innovative product designs to meet consumer demand will push into the IC supply chain the need to identify and develop significant cost/performance improvements in IC device performance. What are these improvements? Are the current roadmaps highlighting them or do we need to better, integrated intelligent roadmap that helps the supply chain stay on treadmill of innovation and cost reduction?

450mm Transition towards Sustainability: Facility & Infrastructure Requirements

Adrian Maynes, F450C Program Manager

It is widely accepted that in the next few years the semiconductor industry will begin to transition to the next generation 450mm wafer size. Experts throughout the semiconductor industry are striving to make 450mm a reality from a technical and manufacturing standpoint. Along with the increase in wafer size, the industry is closely examining impacts to the facility infrastructure, as merely scaling the manufacturing process is not a practical option. The size of the 450mm facility infrastructure and its associated utility consumption projections would simply exceed affordability and resource availability.

The facility experts involved in establishing and later implementing 450mm infrastructure requirements are facing the same degree of challenges as the IC and equipment manufacturers. For the first time in semiconductor history, facility professionals are collaborating closely with the industry’s top five consolidated IC manufacturers to bring their collective expertise to bear on the most pressing 450mm fab issues. With special focus on safety, cost, schedule, sustainability, and environmental footprint, this global consortium of industry specialists is aiming to reduce the cost of production, increase productivity for manufacturers, and reduce the environmental footprint on a per chip basis

This presentation will address these various infrastructure requirements and potential issues for a more sustainable manufacturing process. The session will be co-presented by leaders of the Facilities 450mm Consortium (F450C) and the Global 450mm Consortium (G450C). These two groups are collaborating as experts from across the entire supply chain to ensure a smooth transition to the 450mm technology.

Major Trends Impacting the IC Industry of the Future

Bill McClean, Presdient, IC Insights

IC Insights forecasts that 2014 will continue the integrated circuit industry cyclical upturn that began in 2013. This cyclical upturn is expected to gain momentum over the next several years, resulting in a 6.4% IC market CAGR over the 2013-2018 time period, which would be more than 3x the 1.7% CAGR the IC market displayed from 2007-2012. Although a high level of uncertainty still looms over the global economy, sales of smartphones and tablet PCs continue to soar. IC Insights will present its forecast for the IC market in the context of the IC industry cycle model. In order to make sense out of the current turmoil, a top-down analysis of the IC market will be given and include trends in worldwide GDP growth, electronic system sales, and semiconductor industry capital spending and capacity.

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The ConFab R&D Panel is Set

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A panel session at The ConFab, to be held June 22-25 in Las Vegas, will focus on how the semiconductor industry can continue to innovate in an environment where lower revenue growth is combined with rising development costs and consolidation. The panel will discuss where the next big growth drivers will come from and the ability of the industry to continue scaling and remain on Moore’s Law through the introduction of new technologies such as EUV, Advanced Packaging and 450mm. How will the costs to develop these and other technologies affect innovation and what levers can be utilized to gain more efficiencies in R&D. The panel will also discuss what role startups will play in the industries going forward and how can increased collaboration benefit the industry.

The panel, to be moderated by Scott Jones of Alix Partners, will consist of:

Rory McInerny, Vice President Platform Engineering Group, Intel

Chris Danely, Senior Analyst, JP Morgan

Mike Noonen, Co-founder, Silicon Catalyst

Lode Lauwers, Senior Director of Business Development, imec

Some of the subjects that will be covered:

Where does do the next growth drivers come from?

When will wearables, medical devices and the internet of things really drive revenue growth?

What challenges do we have on the R&D side in servicing the growth areas more quickly?

How are the costs of scaling and the development costs of SOCs affecting growth?

What advances from the chip design and architecture side are compensating for the challenges in scaling?

What view does the institutional investing community have on investing in innovation versus acquiring it?

What is the state of the Start-up environment in Semiconductors?

How do we leverage collaboration more to improve on our return on R&D investment?

Click here for more information on The ConFab 2014 agenda.

Webcast on 3D Integration/Advanced Packaging, Lithography

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If you’ve been following the field of 3D integration for any time at all, then you’re familiar with Sitaram Arkalgud. In addition to being a great guy, he led the charge on 3D integration at SEMATECH in the early days. He’s now at Invensas and I’m very much looking forward to hearing from him again, this Thursday at 1:00 Eastern. You can hear from him too, by tuning into our webcast. But first you’ll have to register: https://event.webcasts.com/starthere.jsp?ei=1032084

Sitaram will be joined by Rich Rogoff, vp and general manager of the Lithography Systems Group at Rudolph Technologies. Rich recently wrote an interesting article “A square peg in a round hole: The economics of panel-based lithography for advanced packaging” and he’s going to expand on that in the second part of the webcast on Thursday.

Here’s a little more information on the webcast, Sitaram and Rich.

2.5/3D integration and advanced packaging enable better chip performance in a smaller form factor, meeting the needs of smartphones, tablets, and other advanced devices. However, 2.5/3D packaging creates a new set of manufacturing challenges, such as the need to fabricate copper pillars, TSVs, wafer bumping and redistribution layers – which may involve thicker photoresists, spin-on dielectrics and BCB coatings — and processing may be done on panels instead of round wafers. In this webcast, experts will detail various options, future scenarios and challenges that must still be overcome.

Sitaram Arkalgud is Vice President, 3D technology at Invensas Corp., where he leads the company’s 3D-IC research and development efforts. Prior to Invensas, he started and led 3D-IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for 3D interconnects. Previously, Sitaram worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. He is the author of several publications and holds 14 U.S. patents. Sitaram holds a master’s degree and a Ph.D. in materials engineering from Rensselaer Polytechnic Institute in Troy, N.Y., and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College, Surathkal, India.

Richard Rogoff is Vice President and General Manager of the Lithography Systems Group at Rudolph Technologies. Prior to joining Rudolph he spent 23 years with ASML in various executive, operational and engineering positions. Most recently he served as Vice President of ASML optics business unit. He received a B.S. in Microelectronic Engineering from Rochester Institute of Technology and a M.B.A. from INSEAD Business School.

Qualcomm’s Dr. Roawen Chen to keynote at The ConFab

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I’m delighted to report that Dr. Roawen Chen, Senior Vice Present of global operations at Qualcomm, has accepted our invitation to deliver the keynote talk at The ConFab, on Monday June 23^rd. As previously announced, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, will deliver the keynote on the second day, on Tuesday June 24^th. I’m thrilled to have these two visionaries speak to The ConFab audience.

In his role at Qualcomm, Roawen oversees the worldwide operations and supply chain, silicon and package technology, quality/reliability, and procurement functions for the Qualcomm semiconductor business. He has overall responsibility for driving the global integrated fabless strategy and execution.

Roawen is an experienced leader in all aspects of semiconductor operations and supply chain management with a solid background in leading large-scale fabless operations. In addition to his strong technical depth, he has proven experience in building close supplier and vendor relationships and executing to support customer demand and product development. Prior to Qualcomm, Roawen was Vice President of Manufacturing Operations at Marvell Semiconductor in Santa Clara, California. During his more than 12 years at Marvell, Roawen held a variety of leadership roles, including Vice President and General Manager of the Communications and Computing business unit and Vice President and General Manager of the Connectivity business unit. He has also served in management roles in Marvell’s Foundry Operations and Manufacturing Technology groups.

Prior to Marvell, Roawen held technical positions at TSMC-USA and Intel. He earned a bachelor’s degree in Physics from National Tsing-Hua University in Taiwan, a master’s degree in Materials Science from the University of California, San Diego and a PhD in Electrical Engineering and Computer Science from the University of California, Berkeley.

The ConFab will be held June 22-25 at The Encore at The Wynn in Las Vegas.

Dr. Gary Patton to provide keynote at The ConFab

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I’m very pleased to announce that IBM’s Dr. Gary Patton will provide the keynote talk at The ConFab on Tuesday, June 24^th. Gary is Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York. He has responsibility for IBM’s semiconductor R&D roadmap, operations, and technology development alliances, with primary locations in East Fishkill, New York, Burlington, Vermont, and the Albany Nanotech Research Center in Albany, New York. During his career at IBM, Dr. Patton has held various management and executive positions in IBM’s Microelectronics, Storage Technology, and Research Divisions, including positions in technology and product development, manufacturing, and business line management. Dr. Patton received his B.S. degree in electrical engineering from UCLA and his M.S. and Ph.D. degrees in electrical engineering from Stanford University. He is also a Fellow of the IEEE.

After Gary’s keynote, we’ll have a panel session focused on R&D collaboration. Moderated by Scott Jones of Alix Partners, the panel will include Rory McInerney, VP of the platform engineering group at Intel; Chris Danely, the Managing Director and global coordinator for J.P. Morgan’s semiconductor research team; and Mike Noonen, co-founder of Silicon Catalyst, the industry’s first semiconductor startup “incubator”.

It promises to be a very interesting morning! The ConFab will be held June 22-25 at The Encore at The Wynn in Las Vegas.

Mission accomplished. Now what?

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In the late ‘80s and ‘90s, when our magazine staff gathered for dinner we often made a toast: “Here’s to chip silicon!” I really believed (and still do) that making electronics more affordable would increase their use and make our lives better and the world a better place to be.

I haven’t toasted to cheap silicon for a while. Why? Because that mission has been accomplished.

At SEMI’s ISS, Paul Farrar, manager of the G450C consortium put the industry progress over the last 40+ years in perspective. “1 Megabyte of memory in 1970 was $750,000. It was sold as an IBM add-on,” he said. “The great technology was made of 57mm wafers, five masking levels, and one level of metal. Today, it’s is less than a penny. That is a 100 million X improvement.”

Of course, most people would like to see this trend continue, but it’s highly unlikely that we’ll see such dramatic progress. Scaling is getting too expensive. The transition to 450mm looks feasible from a technical standpoint (see my column on pg. 10) but it’s not yet clear if it will be less expensive than 300mm, particularly when you factor in 450mm lithography.

So if the scaling mission is accomplished, what’s next? There’s exploding interest in the “Internet of Things” where almost everything is tagged and connected. That will require some big upgrades in the server/network infrastructure, but that can be done with existing technology. It will also require inexpensive sensors and wireless communication. By some estimates, the technology to achieve that is not ready. We need about a 10X improvement in price/performance. Ditto for wearable electronics and a whole host of applications in medical, automotive and the smart grid.

In the future, perhaps electronics will be printed like potato chip bags on roll-to-roll machines with ink-jet-like deposition of materials. Perhaps tiny MEMS with integrated sensors, thin-film batteries, energy harvesting, microprocessors and other functions will be produced for less than a penny. Perhaps everyone will have inexpensive body area networks embedded in their clothing that constantly monitor their health.

It’s all possible, but it will take some innovation in processing equipment and materials.

Take the NCMS survey, but first figure out your nano position

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I recommend taking the new survey out by the National Center for Manufacturing Sciences (NCMS) – www.usnanosurvey.org — but you may first want to give some thought as to what is and what isn’t “nanotechnology.” That’s been something of a puzzle for the semiconductor and related industries over the last 10+ years. Some put semiconductor manufacturing, where matter is regularly manipulated on an atomic scale, squarely in the nanotechnology camp. Judging by Nanotechnology Initiative (NNI) definitions, this is surely the case: “Nanotechnology is the creation, characterization and application of novel materials, devices and systems by control or restructuring of matter at dimensions of roughly 1 – 100 nanometers,” read the NNI definition, which includes nanomanufacturing as “the repeatable building of materials, structures, components, devices and systems designed with nanoscale features.”

Others say no, that’s just really small, it’s only nanotechnology when it takes advantage of the very unique properties of carbon nanotubes, silicon nanowires, quantum dots and other materials and structures which operate on the nanoscale.

Of course, compounding the confusion is the chase for nanotechnology-earmarked funding. Seven or eight years ago, it seems as if overnight everything that was branded semiconductor technology was relabeled as nanotechology. Although it seems to be the fervor has died down a bit, there’s clearly been been increased interest in materials such as CNTs and silicon nanowires in the semiconductor industry lately, particularly as the search for next generation “gate-all-around” transistors and post-CMOS switching technology heats up.

Perhaps there are ways for the U.S. government to help fund such efforts? Figuring that out is one of the goals of the survey.

Themed “Achieving Sustainable Nanotechnology Products,” the goal of the 2014 study is to document best practices in nano-product development and integration, and identify the common challenges organizations (academia, government labs, start-ups or established corporations) face in transitioning nano-scale advances from the laboratory into sustainable commercial applications. Due to the importance of the subject and massive public-private investments made in nanotechnology, NCMS is polling a broad cross-section of U.S. industry.

For this survey, “sustainable nanotechnology products” are defined as market-oriented products engineered by leveraging nano-scale features using materials and processes that minimize negative environmental impacts, conserve energy and resources, are safe for employees, end-users and consumers, and are economically sound.

You are urged to the brief survey if your organization’s activities in nanotechnology meet one of the following National Nanotechnology Initiative (NNI) definitions:

Nanotechnology is the creation, characterization and application of novel materials, devices and systems by control or restructuring of matter at dimensions of roughly 1 – 100 nanometers.

Nanomanufacturing is the repeatable building of materials, structures, components, devices and systems designed with nanoscale features.

The National Center for Manufacturing Sciences (NCMS) has partnered with the National Science Foundation under the National Nanotechnology Initiative (NNI) to launch this latest study of commercialization trends in nanotechnology and nanofabrication– previous studies were performed in 2003, 2006 and 2009.

In the 2009 study, aggregate results indicated that nearly 25% respondents’ organizations were already marketing products and instruments incorporating nanotechnology, and about 85% expected to commercialize products by 2013. Current applications were dominated by nanomaterials (e.g. nano-structured catalysts, carbon nanotubes, quantum dots, nanowires and dopants), complementary metal-oxide semiconductor (CMOS)-based electronics/semiconductor manufacturing processes, as well as other silicon-based energy conversion process industries that leverage similar large-scale fabrication equipment, thin-film coating processes, and closed-environment handling systems. Diverse nanotechnology-enabled, miniaturized biomedical and diagnostic devices, designer drugs and targeted therapies were also progressing, with early products such as nanoemulsions and viricides in advanced clinical trials.

Senior executives and researchers in stakeholder organizations are encouraged to share their experience and opinions about nanotechnology development in the U.S. Individual responses are kept confidential and the data will only be used in the aggregate. NCMS’ insightful reports are widely distributed to federal and state agencies, and elected representatives. All survey respondents will receive the insightful study results in advance of public release this summer. The 15-minute interactive survey may be accessed at www.usnanosurvey.org until March 15, 2014. www.usnanosurvey.org

Questions cover the stage of your commercial entity, the top 3 goals, the urgency of your commercialization efforts, overall capacity, infrastructure, prioritization challenges and what you view as the government’s role in the development of nanotechnologies.

Although the survey is directed at U.S.-based companies, all are welcome to participate.

No technical barriers seen for 450mm

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Paul Farrar, general manager of the G450C consortium, said early work has demonstrated good results and that he sees no real barriers to implementing 450mm wafers from a technical standpoint. Speaking at the SEMI ISS meeting in January, Farrar showed impressive results from, etch, CVD, PVD, CMP, furnaces, electroplating, wet cleans and lithography processes and said the inspection/metrology tools were in place to measure results. “I don’t believe we will find fundamental technology limiters,” he said. “But we will have to keep working to find ways to maximize the efficiency.” Gaining such efficiencies are critical in order to meet the cost-saving goals of the program. “In the end, if this isn’t cheaper, no one is going to do it,” he said.

G450C is a consortium based at the CNSE campus in Albany, NY. It is financed by Intel, TSMC, Samsung, IBM, GLOBALFOUNDRIES, and New York State (CNSE). “Our job is to make it as easy as possible to innovation and be collaborative between the semiconductor makers and our key friends in the industry who enable the 450 work to be done in an economic way,” Farrar said.

At the end of 2013, G450C at 34 tools delivered to its 50,000ft² fab in Albany, with another 7 tools in place at partner’s facilities. “The FOUPS are going, the overhead transport is well underway and some of the cleanroom is actually starting to look like a cleanroom,” Farrar said.

Farrar started with etch results, saying they were “starting to see some pretty good data – 3 sigma at about 2%. Yes, there’s still some work to get to the very edge of the wafer but relatively good progress and good jobs on gas delivery, etc.

He showed good results with both oxide and silicon nitride CVD, with close to 1.5mm edge exclusion. “It’s very representation data from early in the program,” Farrar said, noting that they were starting to pattern some of the more complex oxides.

He said the goal for PVD was to demonstrate better than 5% uniformity. “We know we have step coverage challenges for both the 10 and 7nm nodes. There’s tremendous work going on in the injection rings for gases, high density plasmas from multiple RF sources, but again some progress to me made but pretty good data for right out of the chute,” he said.

CMP results demonstrated repeatability less than 4%. “Very good job done by our suppliers,” Farrar said.

Farrar described data from furnaces as reasonably good. “We still need to do more characterization at what I call the micro level,” he said. “We see some hot spots on the edge, but we’re starting to work on those.”

Also “pretty good data” from electrochemical plating (ECP) of copper. “Well done here,” Farrar said. “The challenge is thermal and pattern loading effects, and gap fill.”

More of the same with wet cleans. “We’re starting to see some pretty good particle data. We’re cleaning wafers relatively well. We are seeing a few things like what I would call micro-metallic contamination that can grow some things so we’re still working on that. But from a particle removal standpoint, pretty good unit process work,” Farrar said.

Farrar acknowledged that lithography remained as one of the biggest challenges in the 450mm transition, but showed good results from directed self assembly across a 450mm wafer, and said the consortium had a very strong partnership with Nikon. “We’re working with them and we’ve seen some tremendous progress at their factory,” he said. “I’m fully confident that we’ll have capability by July to run patterned wafers. Immersion is going to be the workhorse. I think that’s a key enabler to get to 450mm.” He said the industry would have to see how the economics of EUV played out later in time. “I don’t think it’s going to be early in time,” he said.

Farrar seemed to draw hope from the earlier transition from 200mm to 300mm wafers, which started around 1998. “By 2008, we were getting more than 2X the number of wafers per tool out compared to what was going in 2003. There was about a 70% improvement over 5 years,” he said.

50 years ago: February 1964

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In February of 1964, The Beatles landed for the first time at JFK in New Work and appeared on the Ed Sullivan show on February 9^th. Their song “I want to hold your hand” – their 1^st #1 hit – was still #1 after 7 weeks. France & Great-Britain signed an accord over building the channel tunnel (construction for the “chunnel” began in 1988; it opened in 1992). The GI Joe toy (it is not a doll!) was introduced to the U.S. market.

In the electronics arena, it was a time when undersea telephone cables were being installed. In the February 1964 issue of Solid State Technology, Bell Laboratories described scientific advances that made possible a telephone cable system across the Atlantic Ocean. “In service beginning October 14, 1963, it transmits 128 simultaneous two-way telephone conversations,” an ad boasts. “In 1964, a cable of this kind will be laid between Hawaii and Japan, providing an extension across the Pacific Ocean of the telephone cable system now in service to Hawaii.”

In the area of R&D, the development of two experimental NPN transistors for solid-state memory applications was reported by scientists of IBM. From the 1964 issue: “One of the transistors is a high voltage, high speed, medium power device; and the other is an ultra-fast, medium power, low voltage device. Both are silicon, epitaxial, planar, double-diffused types. The high voltage transistor is capable of switching 600 mA of current through a 90V swing in less than 25 ns.The low-voltage device can switch one ampere of current through a 25V swing in less than 8 ns.” The developments were described at the 1963 meeting of the IEEE Profession Group on Electron Devices in two papers, presented by P. P. Castrucci. I believe that has to be the same Paul P. Castrucci who went on to start IBM’s 200mm line. I knew him personally and enjoyed his many stories, many of which are recounted in a discussion for the Computer History Museum.

Sadly, Paul passed away in June of last year.

Another interesting story in February 1964: How solid state electronics helped save space at the Voice of America (the official external broadcast institution of the U.S. federal government) installation in Bethany, Ohio. The Bethany Relay Station operated from 1944 to 1994. In 1962, high voltage stacks replaced the expensive 870A and 872A tubes.

The February Solid State Technology contained features on GaAs IR emitters, tunnel diode amplifiers, and an article focused on the ways to determine thermal resistance by flux plotting.

The Editorial examined the potential of thermionic energy converters. “The observation of the Edison effect, a phenomenon describing the collection of electrons emitted from a thermionic cathode, may be considered the starting conception of a family of energy converters which have no moving parts and which are being developed rapidly to achieve efficiency better than 10 percent and power outputs in the order of hundreds of watts.” Sam Marshall wrote that in 1964. 50 years later, the potential is still being explored,” wrote Sam Marshall.

Today, 50 years later, the potential of these devices is still being explored today. Stanford University and the SLAC National Accelerator Laboratory, are working on applying thermionic energy convertors to applications in the field of Concentrating Solar Power (CSP). The research team is creating a “new solid-state energy conversion technology based on microfabricated and photon-enhanced thermionic energy converters (PTECs). When used as a topping cycle in concentrated solar thermal electricity generation, PTECs will enable system efficiencies in excess of 50%.”

Microscale-enhanced thermionic emitters will enable high efficiency solar to electrical conversion by taking advantage of both heat and light.

The goals of this project are to:

Design thermally isolated thermionic arrays and microelectromechanical systems (MEMS)-based wafer-stack technologies for PTEC fabrication that could exceed the SunShot Initiative targets for system conversion efficiency and cost

Fabricate heterostructure semiconductor cathodes based on active-layer absorbers with the addition of band-engineered passivating layers to demonstrate PTECs with high quantum efficiency

Demonstrate a next-generation thermionic energy converter device with a stand-alone laboratory efficiency >15% as a significant intermediate step toward a stand-alone unit of >30%.

“Through the use of modern design tools and wafer-scale microfabrication methods, this project is demonstrating for the first time a manufacturable approach to thermionic energy converter production that overcomes the space-charge-induced efficiency limitations of traditional thermionic devices. Also, through the novel application of appropriately designed and fabricated semiconductor heterostructure cathodes, the efficiency is being further improved by the photon-enhanced thermionic emission process,” a press release notes. Interesting, but I’d like to know why it’s taken 50 years to get there.

Check out a few of the ads from the issue:

High cost per wafer, long design cycles may delay 20nm and beyond

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Handel Jones, founder and CEO of International Business Strategies (IBS), spoke at SEMI’s Industry Strategy Symposium last week, focusing on key trends, factors impacting the growth of the industry and the migration to smaller feature dimensions. He is bullish about 2014 and industry innovation, but cautious about how quickly the industry will move to new technology nodes due to higher costs, and long design cycles. Overall, he said he believed semiconductor market growth this year will be slightly better than 2013, due in part to the strength of the global GDP.

Perhaps most surprisingly, he had a fair amount of uncertainly about 20nm. “Will 20nm be a high tech technology node and when will that occur?” he said. “We’re tracking design starts and design completions and we see a few 20nm designs but not a lot. Frankly, whether 20nm will be big or not will really depend on two customers: one is Qualcomm and the other is Apple.” Handel said “there is a significant challenge in getting lower cost at 20nm” compared to 28nm due to a lack of increase in the gate density and the potential yield impact. “We think 20nm, if it does go into volume production, it will not be in 2014. Potentially 2015 and maybe 2016,” he said.

Similarly, Handel believes there will be a postponement of 16/14nm. “We expect initial production in late 2016, beginning of 2017. That’s for the SoC business. The FPGA markets will be different,” he said. “There will also be delays in 10nm. Delays mean you can’t really go on the 2 year cycle or even the 3 year. I know people will vehemently disagree with that, but if you look at what’s really happening from a design start point of view and also the end customers, I think you’ll agree with our conclusion,” he said.

“If you look at the reality of the industry, 28nm high-k metal gate went into high volume production toward the end of 2013,” said, adding that they define high volume as 10% of the output. “It took almost 4 years for 28nm high-k metal gate to go into high volume production. Now we’re basically starting 20nm. Even if the fabs are ready what you have is the design cycle time. Preparing libraries and IP can take six months at least. Doing a complex design in 20nm can take you at least a year. Validating the design can take you another half a year. If it’s a modem, and you need approval from the carriers, that’s another half a year. Even if the fab is ready, you start these things and it’s two years,” he said. “We have an industry that is trying to adopt three technologies in three years. It’s impossible,” he said. “It’s not realistic from an infrastructure point of view, even if it the fabs are there, for three technology nodes to ramp in three years.”

Handel said that application processor (AP)/modem design can cost about $450-500 million in 16/14nm, with a timeframe of around 18 months. “You need 10X revenue so for that design, so if you’re spending $450 million, you need $4.5 billion in revenue. A few companies can get that, but not many,” he added.

“The economics of the industry are forcing changes. You’ve seen them already. The long ramp up time for 28nm HKMG, and 20nm with double patterning is clearly a major challenge from a technology point of view, and a bigger challenge from a cost point of view. FinFETs will be an even bigger challenge. Intel is having delays in their 14nm FinFETs, whether in high volume at 22nm, how will companies that have never done FinFETS before, how will design companies that have never designed in FinFETs before, how will they ramp faster?” he asked.

Not surprisingly, Handel also had a dim outlook for 10nm. He estimates that 10,000 wafers/month at 10nm will cost more than $2billion. “If you want to install 40,000 wafers/month, it’s going to be an $8 billion bill. If you want to install 100,000 wafers/month, it’s going to be $20 billion. Even before you get to 450mm, it’s going to be significantly more capital intensive,” he said.

Just looking at the location of the headquarters of semiconductor companies, he said the U.S. was still strong, but there was also strong growth from Korea – mostly in the form of Samsung – but also China and Taiwan. “We see a relatively flat Europe and then a continuing decline in Japan. In fact, we don’t see Japan strengthening unless we see some major changes,” he said.

That also has an impact in terms of the technology requirements. In terms of minimal dimensions, Handel most of the advanced technology designs are in the U.S., with advanced technology defined as being 28, 20 and now starting 16/14nm. “In developing countries, many of the designs are still at 40nm. 28 is a new technology and the next technology after 28 is going from polysilicon up to high-k metal gate,” he said.

Handel also sees uncertainly in the use of FinFET devices due to higher wafer cost. “We see quite a few new designs. The problem again is the cost per wafer. For 28nm, we have about $2600 and for 20nm we have about $3200 and for 16/14 we have about $4000. You now have this increasing cost per wafer and can you get the higher gate density and can you also get higher parametric yields?” he asked.

Handel said the gate utilization is an issue because of limitations of the design tools and parasitic effects. “The other factor is parametric yields, which are strictly tied into leakage control for the 20nm and of course for the 16nm FinFETs,” he said. “You can break this. Intel has shown that it can be broken and of course that’s an excellent achievement. But, it’s based on very high design costs, potentially $1 billion per design, so you need $10 billion in revenue. It also takes a number of years,” he said. He noted that, in the smartphone market, designs move very fast. “You can’t make that kind of investments in designs.”