Semiconductors

SEMICONDUCTORS ARTICLES



KLAC: Yields are key to low costs, in traditional chips and emerging LEDs

05/17/2011 

High performance and low power consumption are expected of today's chips and LEDs. Today's chip makers still expect to keep their costs down. The key to making this work, says Brian Trafas, KLAC, is yield optimization. Trafas, speaking at The ConFab 2011 in Las Vegas, touches on tool supplier/user collaborations as well.

ASMC 2011: Rain doesn't damper the spirit

05/17/2011 

Intermolecular's John Behnke offers his impressions from Day 1 of this year's SEMI/IEEE Advanced Semiconductor Manufacturing Conference (ASMC) in New York. Highlights: a keynote from a suddenly famous GlobalFoundries exec, on-the-fly edge inspection, equipment health monitoring, and a TSV overview.

Wafer bonding: Many options for many devices

05/17/2011 

Wafer bonding. SOURCE: Yole May 2011. Wafer bonding is a complex process, used on 2" to 12" wafers for MEMS, image sensors, advanced packaging, LEDs, and other chips. Yole Développement published a technology study and market research report, "Permanent wafer bonding," to derive trends in the market and technology through 2016.

Bring lithography <11nm with materials, not new steppers, says Brewer Science

05/17/2011 

New innovative processes and materials could be the least costly way to get to <10nm lithography, says Lori Nye, Brewer Science, at The ConFab. With the right use of materials, one can go 2 or 3 nodes beyond currently accepted lithography limits on exposure tools.

Customers, logic reshaping supplier collaboration landscape

05/17/2011 

Harvey Frye, vice-chairman of TEL America, summarized the new supplier landscape in his Confab talk, taking both a macro point of view of trends, and how his company as a top supplier is addressing them: collaboration among suppliers, and an increasing focus on consumer needs.

Connecting investments to industry trends

05/17/2011 

Bob Krakauer, CFO of GlobalFoundries, summarized industry trends in manufacturing and end-applications, a changing foundry landscape, and his company's own long-term investments in semiconductor manufacturing, in his Confab presentation.

More Moore & More than Moore require fabless, foundry, and packaging houses on board

05/17/2011 

Complex supply chain. SOURCE: Yu, The ConFabToday at The ConFab, John Chen (Nvidia), Jeong-ki Min (Samsung Electronics), and Abraham Yee (Nvidia) gathered foundry, OSAT, and chip maker leaders to discuss what happens beyond Moore's Law. The following are key points from "Collaboration to Strengthen the IC Supply Chain."

Silicon Valley upstate: NY's semiconductor manufacturing ambitions

05/16/2011 

Silicon Valley's NY cousin, Mohawk Valley, is attracting investment with university-industry collaborations on leading edge semiconductor manufacturing. Mark Reynolds, Marcy Nanocenter and Mohawk Valley Edge and David Rooney, Center for Economic Growth, speak with Debra Vogler at The ConFab 2011.

2012 and onward for semiconductor fab managers at The ConFab

05/16/2011 

Bill Tobey, ConFab advisory board member and president of ACT InternationalBill Tobey, ConFab advisory board member and president of ACT International, discusses the role of fab managers in today's chip manufacturing environment. After the 2008 financial fallout, and 3 years of recovery, 2012 and onward present challenges and opportunities for research and development, collaboration, etc.

Transistor phenomenon could revive clock speed advancement

05/13/2011 

A sample of the lanthanum aluminate-strontium titanate composite, which looks like a slab of thick glass, with thin electrodes deposited on top of it. SOURCE: MITMIT and University of Augsburg researchers discovered that layered insulators lanthanum aluminate and strontium titanate create a capacitance -- at room temperature -- that cannot be explained by existing physics. The discovery could create entirely new transistors that do not rely on silicon semiconductors.

Benchmark "mid-end" tools and materials for 3DIC and wafer-level packaging (WLP)

05/13/2011 

Yole Développement released "Equipment & Materials for 3DIC and Wafer-Level-Packaging," a database and complete report analyzing in detail the equipment and materials tool-box for wafer-level packaging (WLP). This semiconductor packaging technology falls into the "mid-end," where frontend semiconductor wafer fabs and backend packaging facilities both operate.

3D packaging disrupts the IC supply chain -- ConFab session dedicated to the OSAT/foundry/fabless relationship

05/13/2011 

The ConFab gathers semiconductor industry leaders to discuss the biggest trends in the chip manufacturing sector. One of these major trends is 3D packaging, and Session 2 on Monday (May 16) will combine packaging house, fabless, and foundry approaches to the new supply chain, with speakers from Amkor, GLOBALFOUNDRIES, STATS ChipPAC, and Qualcomm.

Wafer analysis system is "point and shoot" Nanotronics technology

05/13/2011 

Nanotronics Imaging LLC launched the nSPEC semiconductor analysis system with proprietary software and hardware for rapid and detailed analysis of wafer defects. Complete system automation with cassette-to-cassette loading of 2-8" wafers is available.

Verity Instruments spectrograph features improved line-shape uniformity

05/13/2011 

The SD1024FL spectrograph replaces Verity Instruments' SD1024DL with improved line-shape uniformity, resolution, and noise equivalent power, as well as a second-order blocking addition.

CCD pioneer, Dr. Willard S. Boyle, dies at 86

05/13/2011 

Dr. Willard S. Boyle, along with George E. Smith, invented the charge coupled device (CCD) that, until recently, dominated the digital image capture market. Boyle and Smith developed the CCD some 4 decades ago at Bell Laboratories (NJ). The men were awarded the 2009 Nobel Prize in Physics for this work.

Rudolph's 3D package inspection system meets TSV, RDL, bump inspection needs

05/12/2011 

Rudolph Technologies' Wafer Scanner 3880 inspection and measurement systemRudolph Technologies (NASDAQ: RTEC) released the Wafer Scanner 3880 to inspect micro and standard bumps, through silicon via (TSV) post-via-fill copper protrusions (nails) and re-distribution layers (RDL) used in 3D IC packaging.

Ultratech plans HB-LED dev center in Taiwan

05/12/2011 

Ultratech, Inc. (Nasdaq: UTEK) announced an Asia Technology Center (ATC) in Taiwan to develop processes for HB-LED manufacture on its Sapphire 100 lithography system.

CMOS image sensors see growth beyond cellphones

05/11/2011 

Figure. CMOS vs CCD image sensor dollar volumes. Source: IC Insights May 2011.CMOS image sensors did not see the same strong rebound in 2010 that the semiconductor industry at large experienced. New momentum, driven by new system applications outside of camera phones and digital still cameras, could focus CMOS image sensors on growth from 2011 on, says IC Insights.

Silicon semiconductor wafer shipments edged up from Q1 2010 to Q1 2011

05/11/2011 

Worldwide silicon wafer area shipments decreased slightly during the first quarter 2011 when compared to fourth quarter 2010 area shipments, and were marginally higher than first quarter 2010, according to the SEMI Silicon Manufacturers Group.

Day 2, 3 talks on process integration, reliability, 3Di

05/11/2011 

John Iacoponi, IITC 2011 co-chair, reviews Day 2-3 discussions at IITC/MAM, including interconnect reliability, BEOL memory, 3D integration, process integration, ultralow-k, and future-looking talks on graphene and carbon nanotubes.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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