07/15/2010 

WLP has always faced cost challenges on the mass-market sectors, like consumer devices. WLP can reduce power consumption and package size. Novellus introduced several products at SEMICON West to increase deposition and removal productivity and advance the technology.

07/13/2010 

This report from Research and Markets covers new and established technologies for embedded package integration. Benefits of embedded package integration include miniaturization, improvement of electrical and thermal performance, cost reduction and simplification of logistic for OEMs.  

07/13/2010 

In this video, Matt Nowak, Qualcomm, talks about his keynote at ASMC on through silicon technologies for stacking die in advanced packaging applications.

07/06/2010 

Integrated Microelectronics Inc. (IMI), a leading electronics manufacturing service (EMS) provider to OEMs, announced an agreement to acquire 67% of PSi Technologies Inc. (PSi), an independent semiconductor assembly and test services (SATS) provider.

06/25/2010 

Aries Electronics, manufacturer of interconnection products, now offers a CSP test socket with a window that optically exposes 100% of the top of the device under test (DUT) for failure analysis (FA) testing for emission microscopy (EMMI) or optical sensor applications.

06/15/2010 

At the Electronic Components & Technology  Conference (ECTC)  this month in Las Vegas the CPMT (Components, Packaging and Manufacturing Technology) Society of IEEE bought out their long time partners ECA (formerly EIA). Other news: STATSChipPAC expanded its presence in eWLB, copper-copper bonding in 3D was reviewed, and Doublecheck Semiconductors, working with Disco and the Fraunhoffer IZM claims to have developed technology that enables standard silicon wafers to be thinned down to less than 100µm.

06/04/2010 

In a SiP chip stack, space constraints can lead to large parasitic inductances in the packaging. Planarity, processing, high-temperature exposure, and other factors also present challenges. A new anisotropic conductive adhesive technology could enable low-cost flexible packaging via a multi-layer particle structure. S. Manian Ramkumar, Ph.D., RIT, reviews the adhesives benefits to various levels of electronics interconnect.

05/14/2010 

Buoyed by improved demand and a brightening macroeconomic environment, NOR flash memory market revenue is projected to return to growth in 2010, according to iSuppli Corp. The climb will be modest: from $4.6 billion in 2009 to $4.8 billion in 2010.

04/27/2010 

Vage Oganesian of Tessera and Vern Solberg, Tessera consultant, discuss the advanced packaging options available with 3D contact features on substrate interposers for complex, high-pin-count flip chip applications.

04/27/2010 

Imbedded component/die technology is a method of imbedding active and passives into cavities within a multi-layer PCB to decrease the surface area required to implement the circuit design and increase the robustness of the overall assembly. Casey H. Cooper, STI, discusses the design methodology, packaging processes, and test data gathered during imbedded die/component packaging implementation in a mixed-signal prototype. The prototype was subjected to reliability testing and demonstrated in a test flight.

04/23/2010 

A seminar held at last month's Semicon China reiterated points made earlier in the year by an industry group that there are still questions about using copper bonding wire vs. gold in semiconductor packaging applications.

04/22/2010 

Fairchild Semiconductor and Infineon Technologies formed a packaging partnership for their power MOSFETs in the MLP 3x3 (Power33 or S3O8) and PowerStage 3x3 packages.

03/22/2010 

The semiconductor industry is at its most profitable point now than any other time in the past decade thanks to industrywide efforts to aggressively manage costs and capacity -- but wild optimism about surging growth forgets the truth that this recovery only resets to levels from three years ago, according to iSuppli.

02/26/2010 

The Burn-in & Test Socket (BiTS) Workshop will take place March 7–10, 2010 at the Hilton Phoenix East/Mesa Hotel in Mesa, AZ. More than 30 papers and posters will be presented; participants include end users and suppliers of sockets, boards, burn-in systems, handlers, and packages; and other related equipment, materials, and services. The TechTalk session on PCB design, fabrication and assembly is booked full, as is the tutorial on RF socket characterization by Gert Hohenwarter, Ph.D. of Gatewave Northern Inc. Here are some of the show highlights.

02/19/2010 

Tessera Technologies Inc. (Nasdaq:TSRA) semiconductor packaging subsidiary, Tessera Inc., signed a technology licensing agreement with Nanium S.A. Nanium, formerly known as Qimonda Portugal, previously was the largest semiconductor packaging assembly and test operation within Qimonda. Nanium has now reorganized as an independent company and will focus on providing assembly and test services for the DRAM memory market and other semiconductor products. Products manufactured by Nanium will be incorporated into computers, servers and various electronic devices such as MP3 players, mobile phones, cameras, and game consoles. The initial term of the license agreement runs through the end of 2017.

02/17/2010 

System Plus Consulting released its new reverse costing analysis of the enhanced Wafer Level BGA (eWLB) packaging used in the X-GOLD 213 circuit from Infineon. eWLB is a ball grid array (BGA) package based on the emerging fan-out wafer-level package (FO-WLP) concept. All the packaging operations are done at the wafer level, and a fan-out area is provided to extend the package size beyond the IC surface area to allow for higher ball counts. The ball pitch is 0.5mm and only one redistribution layer is used for this 217 balls, 8 × 8mm package.

02/08/2010 

In a deal that will generate economical new process options for the 3D integration market, Alchimer S.A., a provider of nanometric deposition technology for semiconductor interconnects and through-silicon vias (TSV), and KPM Tech Co. Ltd., a manufacturer of plating materials and systems, announced a multi-level collaboration that gives KPM Tech exclusive rights to produce chemicals in Korea for Alchimer’s technology. The agreement also includes the manufacture of various configurations of wet processing tools to support the Alchimer TSV platform.

02/01/2010 

ICAP Ocean Tomo, the intellectual property brokerage division of ICAP Plc (IAP.L), is offering for sale a patent portfolio relating to wafer-level semiconductor packaging owned by Hymite A/S. The 77 issued U.S. and foreign patents and patent applications cover new packaging technologies for optical communications components, LED emitters, and semiconductor fabrication.

01/26/2010 

On behalf of the World Gold Council (WGC), SEMI conducted a survey titled “Semiconductor Industry Opinions Concerning the Selection of Bonding Wire Material.” The survey was intended to gauge the semiconductor industry’s use of copper bonding wire versus gold for packaging applications. The WGC is a commercially driven organization focused on creating demand for gold. While 41% of semiconductor companies surveyed use copper bonding wire, none use it in the majority of their products. However, the majority of respondents will consider copper bonding wire in their new products.

01/08/2010 

Fabless giant Qualcomm has made two deals to reserve leading-edge semiconductor manufacturing capacity: one with longtime partner TSMC, and the other with upstart GlobalFoundries.