07/16/2009  Ric Borges of Synopsys discusses the application of TCAD simulation to multijunction and CPV solar cells.

07/15/2009  Paul Siblerud of Semitool discusses 3D integration challenges and announces the latest news from the EMC-3D Consortium.

07/15/2009  Soitec's president and CEO, André-Jacques Auberton-Hervé, discusses the three pillars of 3D integration at the wafer level, as well as bonding at room temperature. Also noted is Soitec's partnership with IBM, announced during SEMICON West.

07/15/2009  Soitec's president and CEO, André-Jacques Auberton-Hervé, discusses the three pillars of 3D integration at the wafer level, as well as bonding at room temperature. Also noted is Soitec's partnership with IBM, announced during SEMICON West.

07/14/2009  3D IC technology, an alternative approach to wire-bonded chip stacking utilizing interconnets with through-silicon vias (TSVs) fabricated with front-end-like processes, is a hot topic at SEMICON West, and the focus of an on-line virtual forum hosted by public relations firm MCA.

07/14/2009  3D IC technology, an alternative approach to wire-bonded chip stacking utilizing interconnets with through-silicon vias (TSVs) fabricated with front-end-like processes, is a hot topic at SEMICON West, and the focus of an on-line virtual forum hosted by public relations firm MCA.

07/08/2009  SUSS MicroTec and Thin Materials, a semiconductor process development company, are cooperating on a temporary bonding solution to be used for challenging thin wafer handling technologies required for emerging 3D integration and packaging technologies. With this cooperation SUSS MicroTec extends its solution portfolio for temporary bonding and thin wafer handling.

06/29/2009  Alchimer CEO Steve Lerner tells SST how its improved eG ViaCoat wet deposition process of copper seed metallization of through-silicon vias (TSV) can now be used on existing dry equipment -- and provides reliability test results.

06/09/2009  Amid preparations for IMEC's 25th anniversary celebration, SST spoke with Luc Van den hove, now president/CEO of European R&D consortium IMEC, who discussed the research center's strategy and the keys to its success over the years.

06/02/2009  The 2009 3D Architectures for Semiconductor Integration and Packaging Conference and Exhibition will bring together industry leaders to examine the practical and competitive landscape on the path to implementation of 3D integration and packaging technologies, December 9 through 11, 2009, in Burlingame, CA.

06/01/2009  The Applied Materials' Charger UBM PVD system was designed for under-bump metallization (UBM), redistribution layer and CMOS image sensor applications. Its linear architecture is said to more than double the wafer output of other systems. In addition, its proprietary Isani wafer treatment technology allows the UBM system to process ten times more wafers between servicing.

06/01/2009  In a time when R&D is at the forefront of the industry, events like ECTC 2009 become critical for showcasing research achievements, as well as providing venues for learning about the latest developments across the spectrum of device manufacturing. With 16 professional courses, 39 sessions of 6 papers each, two poster sessions, and the opportunity to mix it up with prestigious members of academia and research institutes, calling the event informative would be an understatement.

05/29/2009  Professor Rao Tummala, Advanced Packaging Editorial Advisory Board Member, will keynote the 6^th Annual International Wafer-Level Packaging Conference (IWLPC), October 27–30, 2009 at the Santa Clara Marriott Hotel in Santa Clara, CA.

05/15/2009  The MetaPULSE thin film measurement tool from Rudolph Technologies is optimized specifically for copper via fill in 3D IC applications, as well as copper damascene processes at 45nm through 22nm technology nodes and copper via fill in 3D IC applications. Copper thickness and overburden measurements are critical in optimizing the CMP process that follows deposition during through-silicon via (TSV) manufacturing.

05/15/2009  New integration trends and disruptive packaging technologies, notably 3D TSVs, will cause major technical changes in the memory semiconductor sector, but ultimately pave the way for future growth, according to a recent report from Yole Développement.

05/08/2009  The memory semiconductor industry is about to go through major technological changes as new integration trends and disruptive packaging technologies pave the way to the future growth, reports Yole. The study presents the end applications driving the use of 3D integrated memories and their key players. It also includes an overview of the memory packaging market, its forecasted evolutions with new applications and growth in flash and DRAM.

04/14/2009  By Francoise von Trapp, contributing editor
3D embedded technologies just got closer to volume manufacturing. We've been hearing variations on the embedding theme for quite some time, but as of yet, none have made it to high volume manufacturing. However, one embedded solution, Imbera's integrated module board (IMB) technolog appears to be on its way, after the company's announcement of successful Series B funding, which the company expects will take it into high-volume production.

04/14/2009  Non-traditional Applications of Jet Dispensing
by George A. Riley, Contributing Editor
While jetting is common in semiconductor packaging, it is finding new applications in emerging fields. At the recent SMTA Pan Pacific Symposium, Alec Barbiarz of Asymtek described jetting opportunities in medical analytics, high-intensity lighting, active-matrix displays, green energy, and 3D assemblies.

04/13/2009  By Paul Enquist and Chris Sanders, Ziptronix, Inc.
In 3D IC technology, thinned, planar circuits are stacked and interconnected using through silicon vias (TSVs). 3D ICs have the potential to alleviate scaling limitations, increase performance by reducing signal delays, and reduce cost. Enabling technologies for 3D IC include TSV formation, thinning, and alignment and bonding. Realizing the full potential of this technology requires a scaleable approach to 3D IC fabrication.

03/17/2009  by Fran