Category Archives: 3D Integration

by Ed Korczynski, senior technical editor, Solid State Technology

May 21, 2008 – While manufacturing of 3D ICs is today limited mostly to memory chip stacks and cell-phone camera modules, the next huge application seems to be the embedded memory in microprocessors. Subramanian Iyer, distinguished engineer and chief technologist of IBM’s Systems and Technology Group, explained the economic considerations behind 3D microprocessors at the ConFab 2008 in Las Vegas, Nevada.

The economics of any new technology need to be assessed with respect to the advantages of other competing approaches that provide the same or similar benefits. Both embedded DRAM in a system-on-chip (SoC) and stand-alone DRAM as part of a system-in-package (SiP) have been well established as 2D solutions, so any 3D approach must be compared to these proven techniques. Iyer made his case by examining the relatively straightforward but very important challenge of balancing memory with 64 processor cores in a system.

It is certain that 3D integration promises improved functionality in reduced physical volume when compared to the same circuitry running only in 2D. However, optimizing circuitry for 3D through re-design offers the potential for even greater benefits such as system-level co-design and the use of different fab technologies to create the different IC levels. For example, memory and logic manufacturing can be independently optimized on different production lines to reduce overall system cost.

In today’s microprocessor SoC, the first consideration in embedded memory is whether to choose IT-IC DRAM or 6T SRAM. Compared to DRAM, SRAM is about twice as fast and ~3.5× less dense in Mb/mm2. Since SRAM is built using only transistors, it can be integrated with no additional processing steps over those needed for logic. DRAM, however, needs the charge-storage capacitor and associated unique masks and processing steps, such that embedding it with logic adds to the cost of node manufacturing.

The result of all of the modeling is the conclusion that if much of the die area is eSRAM, then it will be cost-effective to replace it with eDRAM. There has been a general trend in modern microprocessor layouts that the percentage of silicon area devoted to memory has increased as the circuitry has shrunk. As a result, eDRAM has become ever more attractive, and new technology solutions such as 3D must be explores.

For multicore cache-starved microprocessors, the case for 3D integration is very favorable. There is no known alternative which could provide similar functionality, and TSV manufacturing technology has made significant advances recently. However, lack of design tools and clear directions for thermal/power management remain as stumbling blocks. It also seems certain that significantly increased functionality will have to be shown, since cost/area of silicon will probably have to increase for the use of TSV.

The motivation to develop 3D IC manufacturing technology is strong across the industry today, in part due to the challenges of pushing 2D IC integration to ever smaller dimensions. Traditional 2D scaling now must contend with the costs involved in pushing optical lithography below 1/4 wavelength as well as the inherent challenges of controlling atomic-scale films. 3D has a place in the future, but Iyer reminds us that — like any engineering problem — there are inherent tradeoffs, and each unique application needs to be considered independently to arrive at the optimal solution. — E.K.

by Ed Korczynski, senior technical editor, Solid State Technology

Masaaki Kinugawa, GM of Toshiba’s Oita operations, discussed the tough challenges faced by fabs developing advanced processes today. Both process technologies and device technologies continue to increase in complexity, and costs rise proportionally. Alliances to share costs, such as the IBM-centric one for bulk CMOS to which Toshiba belongs, are essential to continue IC shrinks to the 32nm node.

While the core bulk CMOS process is common, each of the partners in the alliance develops different optional processes and technologies to serve each of their targeted SoC markets. For example, Toshiba has invested in FeRAM and MRAM embedded memory with logic, MEMS, and through-silicon vias (TSV) for die stacking as power differentiators. Other optional technologies could include eDRAM, RF-CMOS, and sensors.

Even with careful management of process and technology development through the use of partners and alliances, owning a profitable fab is still getting to be very difficult. In the past, one process node in an IDM fab could be used over 10 or more years to manufacture a series of profitable products such as first SoCs then image sensors and finally MCUs. As the industry moves to 32nm and beyond, the sharply escalating costs of both IC product development and fab equipment may combine to slow down the historic chip cost reduction trendline.

The total cost to develop a chip product — including all EDA functions as well as maskmaking — has been nearly doubling each node from 90nm to 65nm to 45nm. Moving on to 32nm is projected to raise costs only ~50% over 45nm, but the absolute numbers are now making design-teams pause to consider their choice of manufacturing node. Kinugawa predicted that neither Japanese fabless nor customers nor IDM-internal designers are prepared to jump to the next node — such that a “several year gap” will appear between the availability of 32nm node fab capacity and substantial demand!

Only products with very high projected volume can enjoy the benefit of early access to advanced processes. With fab setup costs soaring, even well established IDMs need strategic fabless customers to take up some of the capacity. Toshiba expects that the majority of the initial volume for its 32nm node and beyond fab technology will come from fabless companies, before the established product migration from SoC to MCU finally begins. With a lot of new device materials and novel device structures, any fabless company interested in 32nm node chips will have to work intimately with its foundry. As a major IDM, Toshiba is ready to provide anything from traditional IC foundry work to full ASIC turnkey service including design help starting at the gate-level netlist, Kinugawa said. The company also claims to have 1000 engineers “for IDM foundry service.”

In some cases, a large IDM like Toshiba will also be differentiated from pure-play foundries by special capabilities, such as MEMS, sensors, and 3D techniques based on TSVs, for example.

For 3D packaging, Toshiba has taken aggressive steps to develop cost-effective die-stacking technology. The current offering is 60μm pitch micro-bumps which can be combined with die-thinning, flip-chipping, and wire-bonding to stack three layers of silicon. By 2010, the plan is to have 60μm thin silicon chips with TSV stackable on a silicon interposer for system LSI with lower power consumption and higher performance. Toshiba claims to have developed models such that stacked dice can be simulated as one chip for thermal analysis, power integrity, IR drop, noise, and ESD.

Whether automotive customers who need long-term commitments or consumer electronics customers who need advanced processes, Japanese customers are said to prefer Japanese fabs run by Japanese companies, Kinugawa noted. High quality and quick delivery are mentioned as decision factors, and the IDM may sometimes be able to establish bi-directional business for mutual benefit. The IDM foundry model is based on choosing a small number of key customers, and then servicing them with technology capability from design through test, assembly, and packaging. — E.K.

“The growth we’ve seen in our customer base thus far, coupled with the market potential, makes this move a clear and natural progression for us.” stated Hermann Waltl, senior V.P of sales, EVG. Korea’s increase in technological development efforts to compete in the global semiconductor and MEMS arenas, make it “a hotbed” for adoption of enabling manufacturing technologies, creating market potential for EVG in areas such as 3D stacking, advanced chip-to-wafer integration, as well as wafer-to-wafer bonding, he said.

(May 15, 2008) Redwood City, CA &#151 EoPlex Technologies disclosed $4M additional funding to build its first full-scale production plant for the manufacture of state-of-the-art cell phone antennas. The company had previously announced its Series C funding of $8M in 2007. That round was lead by ATA Ventures with the backing of all current investors, including Draper Fisher Jurvetson, Labrador Ventures and Draper-Richards. The current increase brings the total for the C-round to $12M.

(May 7, 2008) Burlingame, CA &#151 When the IEEE International Interconnect Technology Conference convenes at the Hyatt Regency San Francisco Airport Hotel, Burlingame, CA, June 1-4, the focus will be squarely on 3D technologies. Attendees will have the opportunity to gain both fundamental knowledge and practical manufacturing advice from 3D experts at chip companies and universities from around the world.

Kurt Trippacher, Head of Oerlikon Esec and Segment CEO, who spoke at the ceremony, said the first machines are producing in high volumes at customer locations in Europe and in Asia.

By Daniel F. Baldwin, Ph.D. and Paul Houston, ENGENT, Inc.
Current 3D packaging solutions involve a mix of high density circuit boards with stacked ICs using wire bond interconnect. With advances in wafer-thinning technology, 3D packaging now provides a robust platform for achieving high levels of integration, small package footprints, and thin package profiles. For emerging applications, further component miniaturization with the added benefit of 3D integration can be realized by face-to-face bonding of fine-pitch flip chip components and low-profile passives onto a redistribution layer (RDL) of another silicon component (a wafer level chip scale package

The Trouble with News


May 1, 2008

You would think that because I’m a National Public Radio junkie, news would be of vital importance to me – any type of news. Just between us, sometimes it doesn’t make the impression intended.

Let’s consider the economy. In Q1 2008, the Commerce Department reported 0.6% growth. Therefore, a recession isn’t happening, right? Two quarters of negative growth officially defines a recession. When I drive through Anytown, USA, and see the yard sales, foreclosure notices, and layoffs in manufacturing plants, it certainly feels like a recession. Just fill up at any gas station or pay for a few groceries and you see inflated prices. Home values are still falling; Standard & Poor’s reported an annual 12.7% drop.

Then some good news perks up the outlook. Just last week Stan Myers, president and CEO of SEMI, indicated that global semiconductor equipment sales are expected to decline by 15-20% on year in 2008. But he added – and this gets my attention instantly –the IC packaging and testing sector is anticipated to grow in shipments, which will in turn call for more materials. The IC packaging and testing materials market will grow by at least 9% this year, he added. The world looks rosier.

Suddenly the news doesn’t seem so bleak. It doesn’t seem to matter any more what Obama’s past minister said or how long Clinton will battle for the nomination.

Here’s the news that really makes a difference, at least to me. Companies are partnering to tackle manufacturing 3D integrated packages. Take the 3D Integration and Packaging Roadshow sponsored by SUSS MicroTec, STS, and NEXX Systems presented in May in Raleigh, NC; Dallas, TX; and San Jose, CA. Now there’s creative cooperation at its best. Advanced Packaging magazine is sponsoring a symposium with MEPTEC called Packaging Developments and Innovations: From System Design to Integrated Delivery on Nov. 13, 2008, Wyndham Hotel, San Jose. This will have all types of emerging technology issues as topics of discussion and the movers and shakers of the industry as presenters.

There is lots of other news as well. A leading foundry, TSMC, announced recently about expanding beyond design and manufacturing to offer testing and packaging (wafer-level packaging). Packaging has become attractive to front-end foundry players, moving up the food chain. Also, many traditional SATs providers are doing well. For instance, STATS ChipPAC Ltd. announced results for the first quarter 2008 with revenues of $427.2M, increased by 9.4% over the first quarter of 2007. Nemotek has licensed the Shellcase MVP wafer-level chip-scale packaging (WLCSP) solution from Tessera. Shellcase MVP was announced by Tessera in March. This will enable Nemotek to provide OEMs and camera module manufacturers with the ability to build smaller, thinner, and more functional devices, such as camera phones, digital cameras, and laptops.

This is the type of news that gets me excited. I guess that all news, like all politics, is local or at least personal.

Click here to enlarge image

Gail Flower
Editor-in-Chief

(April 23, 2008) Palo Alto, CA&#151 3D packaging is expected to emerge as a dominant performing solution in the electronic/chip packaging industry. Its performance promises to drive efforts across the entire supply chain to successfully deploy it, according to analysis reports from Frost & Sullivan’s Global Trends in Electronic/Chip Packaging. Analysis indicates that the industry is moving beyond system on chip (SoC) to explore various forms of system in package (SiP).

Belgacem Haba, Ph.D., Fellow and CTO of advanced packaging and interconnect, Tessera Inc. San Jose, CA, gave an insightful speech on Sunday, March 9, 2008, the tutorial day of the show, titled “Catching the Mobile Wave: Packaging Is Going 3D”. Haba claimed that hand-held communication and entertainment products will dominate and control the technological direction of consumer markets worldwide. With each successive generation, miniaturization and systems-level integration become more important. Though product functionality increases, customers expect smaller, lighter, less expensive products. Taking the cell phone as an example of how new technologies can be applied to improve performance and functionality, he discussed the types of materials packed into every new cell phone including oscillators, filters, capacitors, resistors, connectors, and cables. One method of thinning layers of electronics is through using 3D stacked packages. Then Haba concluded by reviewing exciting new methods for building 3D packages to fit future needs including the use of thru silicon vias (TSVs) for interconnect, wafer thinning, and embedded packages.

By Patrick Carrier, Mentor Graphics

EMC3D aims to address technical, integration, and economic issues of creating 3-D interconnects using TSV technology for chip stacking and advanced MEMS/sensors packaging. Through collaboration with research partners, the consortium will develop unit processes for creating micro-vias between 5 and 30 &#181m on 50-&#181m thinned 200 and 300-mm wafers using via-first and die-to-wafer techniques. The primary goals of the consortium are reportedly to create a robust integrated process flow at a cost of less than $200 USD per wafer.

(April 10, 2008) Scottsdale, AZ &#151 – MEMS accelerometers have hit the limelight with all the consumer applications in gaming devices, such as the Nintendo Wii, and smart phones like Apple’s iPhone. But these popular products are only the high-profile advance wave of what will be a rising tide of new and innovative uses for the tiny motion sensors, says Douglas McEuen, senior analyst at ABI Research.