April 13, 2007 – IBM says it has developed a way to incorporate through-silicon vias (TSV) into its chipmaking process that shortens data-travel distances by up to 1000x and allows for 100x more pathways than 2D chips. Samples of chips using the 3D stacking technique will be shipped by year’s end, with production ramping in 2008.

IBM says it is fabricating a prototype SRAM design using 3D stacking technology and through-silicon vias with 300mm/65nm process technology, with samples starting in 2H07 and production in 2008. First products will be wireless communications chips in power amplifiers in wireless LAN and cellular applications. Future plans target high-performance server and supercomputer chips.

IBM says the 3D stacking technique offers the following benefits:

– Offers 40% better power efficiency in SiGe-based wireless products, and replaces less-efficient wire bonds for transferring signals off the chip;

– Increases processor speed while reducing power consumption by up to 20%, through uniform power delivery to all parts of the chip;

– Allows stacking of high-performance chips, e.g. processor-on-processor or memory-on-processor — e.g., the chip powering IBM’s Blue Gene supercomputer

IBM is one of many chipmakers pursuing 3D stacking technology. At IEDM in December, IMEC described how it has stacked and interconnected extremely thinned bulk silicon die containing through-silicon vias by direct copper-to-copper thermo-compression bonding, achieving functional through-silicon 3D-via chains. Meanwhile, NEC Electronics, Elpida Memory, and Oki Electric also have demonstrated a new 3D high-performance DRAM package using bumps and through-silicon vias. And a year ago, Samsung said it developed a wafer-level processed stack package (WSP) of high-density memory chips using “through silicon via” interconnections, that is 15% smaller and 30% thinner than an equivalent wire-bonded multichip package.

[IMAGE CAPTION: Cross-section image of IBM’s “through-silicon-via” technology in a stacked chip. (Source: IBM)]

April 5, 2007 – Ziptronix Inc. and Raytheon Vision Systems (RVS) say they have demonstrated compatibility of Ziptronix’s “direct bond interconnect” (DBI) interconnect technology with multilayer CMOS IC processes, involving 3D integration of five-layer metal 0.5-micron CMOS devices with silicon PIN detector devices.

RVS parts were built in a die-to-wafer format (DBI also supports wafer-to-wafer format) with 8-micron interconnect pitch. The majority of initial device yields were 100% for parts with >1M vertical connections, the companies said in a statement. Targeted application is high-performance imaging including focal plane imagers and sensor arrays.

“With the Raytheon project, we successfully applied our planar DBI technology to achieve a very high 3D integration density with a multilevel CMOS process,” said Paul Enquist, Ziptronix CTO and VP of R&D.

The DBI interconnect technology achieves high-density vertical interconnections without volume exclusions, supporting >10-micron pitch and typical width of 2 microns and 1-micron alignment accuracy, the company says. Enquist noted that the technology utilizes existing equipment operating at room temperature without applying external pressure.

In Oct. 2005 the company said it had developed a 3D system-on-chip combining memory, microprocessor, and programmable logic die into a single multilevel silicon die as a demo for a customer for use in wireless communication applications.

March 14, 2007 – Elpida Memory Inc., a Japanese supplier of dynamic random access memory (DRAM), has entered into a multi-year partnership with IMEC, an independent nanoelectronics research center, to perform R&D for beyond 50nm DRAM process generations, said IMEC today. With this agreement, four of the top five leading DRAM suppliers, including Elpida, Micron, Samsung, and Qimonda, collaborate within IMEC’s global research platform, together with other logic IDMs and foundries.

Building on more than 20 years of experience with nonvolatile memory research, in 2006 IMEC extended its sub-32nm CMOS research platform towards memory scaling. Thereby, IMEC’s package of (sub-)32nm CMOS research programs addresses the challenges of both logic and memory-oriented roadmaps.

Starting April 1, a team of researchers of Elpida will start collaborating closely with IMEC’s researchers to build up a fundamental understanding and to develop robust solutions for front-end-of-line memory technologies in order to perform research and development for beyond 50nm DRAM process generations.

“We are excited that Elpida has joined our research platform. We are convinced that their valuable know-how in memory scaling will be an important asset for our global research platform,” said Prof. Gilbert Declerck, president and CEO of IMEC.

Recent IMEC news:

March 12, 2007 – IMEC signs frame agreement with Flemish government

December 11, 2006 – IEDM roundup: IMEC shows off 3D ICs, sub-32nm Cu contacts, laser anneal, Ge pMOS

November 6, 2006 – IMEC, India groups tie knot for chip R&D

January 5, 2007 – SEMATECH has appointed Sitaram Arkalgud, appointee from Qimonda/Infineon Technologies, as director of its new 3D interconnect initiative, in addition to his duties leading SEMATECH’s interconnect division.

In his new role, Arkalgud will lead an expanded 3D program that will define and map 3D technology options, develop unit processes and metrology, and ultimately demonstrate 3D’s functionality and reliability. SEMATECH launched the new 3D project in Feb. 2006 to explore the feasibility of three-dimensional (3D) interconnect technology for the semiconductor industry, with initial work focusing on developing a cost model for 3D migration and a list of infrastructure needs as well as building consensus on 3D technology standards. Future activities involve proving feasibility of the technology for materials, unit processes, integration, and reliability.

In an interview with WaferNEWS last year, Arkalgud indicated the program will focus on wafer-on-wafer and die-on-wafer structures, seeking answers for both high-performance and low-cost products, with a working group of ~20 SEMATECH member companies assessing key challenges of 3D interconnect and available options, and developing a 3D roadmap with the ultimate goal of transferring the process to the ITRS. The new 3D interconnect project will augment SEMATECH’s low-k development program emphasizing chemical vapor deposition (CVD) films, he said.

Arkalgud has directed SEMATECH’s interconnect division for the past four years, leading efforts to screen, characterize, and improve the performance of low-k dielectric materials for the 45nm and 32nm nodes, and also initiated the exploration of next-generation 3D interconnects. Prior to his SEMATECH assignment, he was director of Infineon’s MRAM development alliance with IBM, and before that was technology officer for Infineon’s memory product division, and product manager for ferroelectric RAM development.

October 19, 2006 – Samsung Electronics Co. Ltd. says it has developed a 50nm DDR2 DRAM chip utilizing 3D design and multilayered dielectrics, a process that enhances performance and data storage capabilities.

Production efficiency is improved by 55% vs. a 60nm process shrink, thanks in part to use of a 3D selective epitaxial growth (SEG) transistor with broader electron channel that optimizes electron speeds, reducing power consumption and leading to higher performance. A multilayered dielectric layer (ZrO₂/Al₂O₃/ZrO₂) helps resolve weak electrical signals, and sustains higher volumes of electron to increase storage capacity.

In addition, the 50nm DRAMs use Samsung’s proprietary “recess channel array transistor” (RCAT) 3D technology, which effectively doubles the refresh term of DRAM and is a “critical technology” for enabling higher scalability in DRAM chip development, the company said.

Samsung’s new 50nm process could be applied to its DRAM line including graphics and mobile chips. Mass production is slated for 2008.

Most recent scaling announcements from Samsung, which recently ramped to mass production of 80nm 1Gbit DDR2 DRAM memory, have actually been for NAND flash devices. In September, Samsung said it created a 32Gb NAND flash device using 40nm process technologies, featuring a “charge trap flash” (CTF) architecture that “sharply” reduces intercell noise levels, and enables higher scalability to enable transition from 40nm to 30nm and even 20nm processes. And two months earlier, Samsung qualified its 65nm low-power process technology at its S1 300mm logic fab line in Giheung, Korea, and ramped to volume production of its 8Gbit NAND flash memory based on multilevel cell (MLC) architecture and 60nm process technologies, two years after announcing development of the technology.