Category Archives: Wafer Level Packaging

(October 1, 2010) — DEK has launched ProActiv process technology to enable electronics manufacturers to print pastes with high-density heterogeneous PCBs and ultra fine pitch assemblies such as advanced package assembly. Advanced printing can take place with a conventional printing process with a single thickness stencil.

As the stencil aperture area ratio decreases with the emergence of miniaturization and heterogeneous assemblies, the chance of successful printing decreases. Each ProActiv installation contains a control subsystem and a set of squeegees featuring embedded electronics. When activated, ProActiv energizes the paste that is in contact with or in very close proximity to the squeegee blade. This energizing action does not alter the paste but causes it to be far more compliant, improving the packing density of solder particles into apertures and enhancing the bond between those particles. In turn, this transforms solder paste transfer efficiency to deliver incremental improvements in quality, yield and throughput, even with today’s subassemblies.

DEK reports strong results after a ProActiv Beta Test program, enabling finer pitches, longer intervals between under-stencil cleaning, and fewer paste-print defects.

DEK is a global provider of advanced materials deposition technologies and support solutions including printing equipment platforms, stencils, precision screens and mass imaging processes used across a wide range of applications in electronics pre-placement subassembly, semiconductor wafer manufacture, and alternative energy component production. The technology is covered at www.dek.com/proactiv

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(September 30, 2010) — Research in China put out this new report chronicling the advanced semiconductor packaging industry happenings and key companies from 2009 to 2010. The study mainly focuses on CSP and BGA packaging. Technology adoption and costs are analyzed, from eWLB and other wafer-level packaging (WLP) techs to TSV.

Advanced packaging is mainly applied in mobile phone, CPU, GPU, Chipset, digital camera, digital video camera, and FPTV, of which mobile phone sectors use advanced packaging the most, since an average of approximately 12-18 pieces of IC in every mobile phone is in need of advanced packaging. Mobile telecom shapes the advanced packaging market of almost 18 billion pieces; followed by computer CPU, GPU and Chipset whose unit price and gross profit are far higher than that of mobile phone IC packaging despite the smaller quantity.

In 2010, the global packaging & testing industry will have an output value of nearly $46.15 billion, among which, the IDM sector enjoys $24.01 billion, and the outsourcing semiconductor assembly & testing providers (OSATs) occupy $22.14 billion. The proportion of world’s packaging & testing industry in the output value of global semiconductor industry climbed to 18.1% in 2009 from 17.5% in 2004, and it can promisingly reach 19.5% by 2013. The packaging and test industry has become increasingly important in semiconductor fab. The output value of packaging and test worldwide in 2010 will rise 22.8% or so from 2009 and the growth margin of SATS is close to 30.5%. In particular, advanced packaging providers will experience an even higher average growth of about 36.5%, the highest level since 2000.
 
QFN
Take the baseband MT6253, a highly integrated IC of MediaTek, as an example. If it adopts MediaTek’s consistent TFBGA packaging, the packaging area will be around 14mm2 with poor EMI/ESD performance and heat dissipation. So, MediaTek seeks help from ASE Inc., which developed a QFN package that reduced the area to 11.5mm2, with material cost of QFN packaging leadframe only one-third that of the BGA. In fact, cooperating with Mitsui in patent, ASE Inc. started R&D in 2007Q3, purchased machines from 2007Q4 and accomplished verification in 2008Q3. However, the pitch of aQFN packaging is relatively small, creating trouble for SMT assembly houses in China, resulting in the low yield rate at the initial stage. The yield rate has been much improved after considerable effort. MT6516, the mobile phone baseband of MediaTek, has a pitch of only 0.378mm, far smaller than that of MT6253.

WLCSP
In 2008, Infineon launched PMB8810, using eWLB packaging provided by STATS ChipPAC Ltd. eWLB, embedded wafer level packaging, is an upgraded version of wafer-level chipscale packaging (WLCSP), with a package size of 8mm2. As a small, highly integrated baseband processor, it also favors 6-layer PCB and reduces cost. LG has largely adopted PMB8810, e.g. GU230, T310, T300, GD350, GB220, and GS170; so have Samsung’s S3350 and Nokia. The global shipment of PMB8810 in 2009 hit 35 million.

TSV
The popular through-silicon via (TSV) technology is making slow progress. TSV has to solve quite a few technical problems and holds high cost against still immature technology and no unified standards, 3-5x higher than that of SoC or SiP designs of the same function or performance. TSV memory, originally anticipated to mushroom in 2010, failed to make its debut so far and it is predicted to be rolled out massively in 2011, while the Logic +Memory type TSV IC emerged roughly 1-3 years later than expected with not-so-large application numbers. In the future, TSV will be still primarily applied in CMOS image sensor and stack memory. Fan-Out WLCSP packaging starts to stand out conspicuously in 2010.

Packaging company ranks
In regard to industry, ASE Inc. (an average of 2-3 acquisitions per annum), the global No.1 packaging & test company, purchased 59% equities of Universal Scientific Industrial Co., Ltd. (USI) for nearly TWD13.5 billion in February 2010 and the shareholding ratio of ASE Inc. reached 77%. USI is the downstream manufacturer of ASE Inc.’s clients, and after the acquisition, ASE Inc. has further stabilized the orders, the estimated main business revenue in 2010 will see a growth close to 50%. In August 2010, ASE Inc. invested $67.68 million to acquire Singapore’s EEMS, intensifying its strength in test business. In December 2009, the global No.2 LCD packaging & test company Chipbond acquired International Semiconductor Technology Ltd. to become the world’s largest LCD packaging & test enterprise, and the revenue of Chipbond will experience a growth of 165.8% in 2010. At the end of December 2009, Unimicron officially amalgamated with Camel Precision Co., Ltd., and its revenue in 2010 is predicted to witness a growth margin of 142.6%, and it will climb to the global No.3 IC substrate manufacturer from the current 5th position worldwide. Subordinated to Samsung, South Korean STS Semiconductor has flooded into logic IC packaging & test field from memory packaging & test, and its revenue is expected to see a growth margin of 130.2% in 2010.

The full report includes a discussion of the status quo and future of IC advanced packaging, covering SOP, QFP & LQFP, FBGA, TEBGA, FC-BGA, WLCSP, Fan-out WLCSP (FOWLCSP), and more. It covers the global, and particularly China, semiconductor industry and wafer foundries. Features cover the future of copper wire bonding, horizontal package type comparisons, analysis of the industry and downstream markets, and top companies.

Advanced packaging companies covered by the study include Greatek Electronics; Formosa Advanced Technologies Co., Ltd. (FATC); Powertech Technology Inc. (PTI); ChipMOS TECHNOLOGIES (Bermuda) LTD. (ChipMOS); King Yuan Electronics Co., Ltd. (KYEC); Amkor; Siliconware Precision Industries Co., Ltd. (SPIL); STATS ChipPAC Ltd.; Advanced Semiconductor Engineering Inc. (ASE Inc.); Kinsus Interconnect Technology Corp.; Nan Ya PCB Corporation; Unimicron; Camel Precision Co., Ltd.; IBIDEN; Shinko Electric Industries Co., Ltd.; Nepes; STS Semiconductor; SEMCO; Jiangsu Changjiang Electronics Technology Co., Ltd (JCET); Unisem; CARSEM; Nantong Fujitsu Microelectronics Co., Ltd.; and Chipbond Technology Corporation (Chipbond).

The report can be ordered from provider Electronics.Ca Publications at http://www.electronics.ca/publications/products/Global-and-China-Advanced-Packaging-Industry-Report%2C-2009%252d2010.html

Also read the recently released NVR report on the global IC packaging market.

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(September 29, 2010) — Endicott Interconnect Technologies Inc. (EI) entered into a strategic partnership agreement with Harris Corporation to jointly develop innovative microelectronic solutions and collaborative services for new products serving key markets and customers. 

The agreement builds upon the established relationship between the parties and lays the framework for the strategic partnership which includes shared executive business reviews, program assessment, technology roadmap and new business opportunity discussions as well as cost reduction strategies.  Harris Corporation’s selection criteria included demonstration of EI’s AS 9100 certification and a comprehensive audit of EI processes. “Our collaboration will accelerate product development and enhance quality,” commented James J. McNamara Jr., president and CEO at EI.

Learn more at http://www.endicottinterconnect.com

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(September 28, 2010) — Indium Corporation’s global product manager, Andy C. Mackie, Ph. D., MSc, is presenting at the International Wafer-Level Packaging Conference (IWLPC), October 11-14, 2010 in Santa Clara, CA.

Dr. Mackie is presenting "Supply and Testing of Ultralow Alpha (<0.002cph/cm2) Assembly Materials" as part of the session on wafer level packaging. In addition, Dr. Mackie is a member of the 2010 IWLPC technical committee and is also chairing a session for the 3D packaging track.

More IWLPC news:

Mackie has over 20 years of experience in new product and process development and materials marketing in all areas of electronics manufacturing, including wafer fabrication, electronics assembly, and semiconductor packaging. He is an electronics industry expert in physical chemistry, surface chemistry, rheology, solder materials properties and processes (including solder paste printing), and reflow processes.

Dr. Mackie received the prestigious IPC President’s Award in 2001 for his leadership in both the Solder Paste Task Group and the Assembly and Joining Materials sub-committee. He is formally trained in Six Sigma "Design of Experiments" and has written papers and lectured internationally on subjects ranging from sub-ppb metals analysis in supercritical carbon dioxide to pin-probe testing of flux residues. Additionally, Dr. Mackie holds patents in novel polymers, gas analysis, and solder paste formulation.

He has a PhD in Physical Chemistry from the University of Nottingham, UK, and a Masters of Science (MSc) in Surface and Colloid Chemistry from the University of Bristol, UK. Dr. Mackie is based at Indium’s global headquarters in Clinton, NY, USA. He is also the author of the Semiconductor / Power Semiconductor Assembly blog. 

Sponsored jointly by the SMTA and Chip Scale Review Magazine, the annual IWLPC explores cutting edge topics in wafer-level packaging and IC/MEMS/MOEMS packaging, including 3D/Stacked/CSP/SiP/SoP and mixed technology packages.

For more information or to register for the conference, visit www.iwlpc.com. For more information about Indium Corporation visit www.indium.com

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(September 27, 2010) — Picotest released a new family of Signal Injectors, or adapters, to improve voltage regulator, LDO, and power supply testing accuracy. Increased bandwidth and higher resolution measurements are enabled for PSRR, stability, crosstalk, reverse transfer, input impedance, Bode plots, and crosstalk tests along with non-invasive in-circuit testing (ICT) for load transients, stability and output impedance. The Signal Injectors work with network analyzers, oscilloscopes, and arbitrary waveform generators from all manufacturers.

The family consists of two injection transformers, a DC bias injector, a line injector, a solid state voltage injector, and a unique solid state current injector along with cascadable attenuators.

“These signal injectors will change how engineers and IC manufacturers test voltage regulators and other power circuitry,” states Steve Sandler, managing director of Picotest.com. “Engineers currently connect their expensive network analyzers to devices under test (DUT) via poor performing test adapters, such as audio, video, or 60Hz transformers or home-brewed interconnect schemes. The data they get is often erroneous. In many cases, the data may look reasonable, but is not accurate.” The same is true of voltage regulator and LDO data sheets. “Much of what we find in the data sheet graphs is either incorrect or incomplete. The signal injectors solve these problems and allow analyzers and oscilloscopes to make higher resolution, higher bandwidth measurements to the point where the true circuit performance can be revealed.”

The J2111A current injector is capable of performing a small signal step loading at switching speeds and bandwidths that electronic loads cannot (40MHz, 20ns Rise/Fall times). The capacitance of an electronic load, which is generally too high and impacts the measurement, is not an issue for the current injector. Incorporating a 40MHz current monitor, the current injector can also be used to measure output impedance, as well as, the stability of a three-terminal regulator or a filter combined with the negative resistance of a switching converter or power supply. One of the key benefits is that load step, stability, and impedance measurements can all be made non-invasively while connected to hardware that is already integrated in its production form. For example, the control loop for a fixed output LDO cannot be broken and its stability directly measured since the loop is within the IC. Load step testing is currently the only way to check stability besides simulation. Such testing does not produce an exact phase margin result. While the J2111A current injector can perform the load step testing, it can also allow the output impedance to be recorded and from that, an exact phase margin result can be computed.

The J2120A line injector allows the input DC supply voltage to be modulated by the analyzer source signal, as in the case of a PSRR measurement. The line injector supports a frequency range that is generally well below the AC line frequency and above control loop bandwidths (10Hz-10MHz). The line injector is capable of operating levels that include 5 Amps maximum current and 50VDC maximum input voltage, while minimizing the power dissipation within the injector.

The injection transformers (J2100A 1Hz – 5MHz & J2101A 10Hz – 45MHz) and the J2110A Solid State Voltage Injector, also known as a Bode box, greatly extend the usefulness of any network analyzer for Bode plot tests. They enable network analyzers to better measure stability, input and output impedance, PSRR, component impedances, reverse transfer, crosstalk and Middlebrook filter stability. The J2100A, with its excellent low frequency performance, is ideal for PFC testing, while the J2101A is better suited for general power supply testing. When lower (DC) or higher bandwidths of up to 50MHz are needed, the J2110A solid state injector can be employed. The injection transformers each feature a 23 Octave range, low distortion for superior precision, and a 5 Ohm termination impedance for minimum impact to the loop.

The solid state voltage injector features a DC-45MHz bandwidth to support thermal and mechanical controls, as well as the highest performance regulators and amplifiers, low distortion for superior precision, 25 Ohm insertion resistance, 50 Ohm oscillator input, and less then 3uA typical bias current. A very high PSRR low noise power supply with universal input range is included.

The J2130A DC bias injector has a 10Hz-10MHz usable bandwidth and can easily measure varactors, junction capacitance, capacitors voltage sensitivity, as well as bias low power transistor amplifiers and diodes for parameter extraction.

While most engineers own a network analyzer, few own the necessary Signal Injectors to make accurate and repeatable high resolution measurements. With the Picotest family of signal injectors, you can make these measurements with confidence that your results will be accurate to the bandwidth and resolution levels necessary for your application.

The Signal Injectors are available from Picotest (www.Picotest.com) individually and in bundles.

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(September 24, 2010) — Fujipoly released Sarcon 100GR-FL, a low resistance, durable thermal interface gap filler pad. The gel-like material is manufactured with an integrated nylon mesh layer that prevents distortion and stretching during die-cut operations.

When placed between a heat source such as a high-performance semiconductor and a nearby heat sink, Sarcon 100GR-FL will transfer heat with a thermal conductivity of 2.8W/m-K and a thermal resistance of .67°Cin2/W at 14.5 PSI. This 1.0mm thick, flame retardant thermal interface material (TIM) is available in sheets up to 300 × 200mm.

Fujipoly America Corporation, is a wholly owned subsidiary of Fuji Polymer Industries Co., Ltd. of Japan. Fujipoly America specializes in the fabrication of silicone rubber technology. Learn more at http://www.fujipoly.com.

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(September 24, 2010) — SEMICON Europa will take place October 19-21 in Dresden, Germany. The SEMI Europe team is closely working with their supporting committees and the manufacturing and R&D organizations to tailor the SEMICON Europa programs. Program development is matched to the specific needs of the European semiconductor industry in the current environment.

  • 12 Technology conferences
  • 13 Free technology and standardization session
  • 4 Executive and networking events
  • 12 Courses

The Advanced packaging and test track of SEMICON Europa will deal with the industry shift away from high-lead solders, digital test and testing integrated analog/mixed-signal packages, package design in the electronics design workflow, and LEDs, among other topics.

The theme of the Advanced Packaging Conference in 2010 will be "Enabling Packaging Technologies for System Integration."

The 12th European Manufacturing Test Conference (EMTC) is set to cover "Mapping Digital Test and Diagnosis Approaches on the Emerging Integrated Analog Mixed Signal Arena." Test will also be the focus of the 2nd CAST Workshop – Collaborative Alliance for Semiconductor Test, which will target docking and mounting.

Keynote speakers include Peter Robinson, Package Design and Development Director, CSR, presenting "System Design, Drives Package Design, Drives Silicon Design;" Raimund Schwarz, Senior Director, Osram Opto Semiconductors, who will deliver "High Brightness Phosphor Converted White LEDs — Challenges and Solutions;" and Andreas Fischer, Automotive Electronics, Development ASIC & Power Packages, Robert Bosch GmbH, giving the talk "Substitute material(s) for High-Lead Solders," about different ways to bond high-power packages in the increasingly lead-free electronics arena.

For the semiconductor packaging and test track agendas, including speakers and times, visit http://www.semiconeuropa.org/ProgramsandEvents/TestPackaging/index.htm

Program tracks (Click on the links to view a track overview):

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(September 23, 2010) — The latest developments in advanced microelectronics packaging, including focused tracks on 3D integration, LED technology, MEMS packaging and thermal management, will be part of the technical program at the International Symposium on Microelectronics, sponsored by the International Microelectronics And Packaging Society (IMAPS). Scientists, engineers and researchers in the field of advanced semiconductor packaging will showcase their work in a program of technical papers, poster sessions, forums, professional development courses, exhibitions and other events designed to cover the entire microelectronics supply chain.

The 43rd annual IMAPS Symposium will be held at the Raleigh Convention Center near Research Triangle Park, NC from October 31 through November 4, 2010. A full program of 18 professional development courses will be held on October 31 and November 1 in conjunction with the conference, and more than 180 papers will be presented in the main technical program.

The technical program is arranged around five main topics, or tracks, including:

  • 3D Packaging & Integration – 3D IC integration and packaging is one of the fastest-growing areas in microelectronics, with some of the industry’s leading work being done in the Research Triangle Park area. IMAPS 2010 has assembled a series of invited papers from RTP researchers and companies to inform attendees about the latest advancements in 3-D packaging, including TSVs, die stacking, and wafer thinning.
  • Next Generation Materials – These sessions focus on the use of advanced materials for microelectronics packaging, including conductive adhesives, advanced ceramics, high-performance interconnects, and thermal management issues.
  • Assembly & Packaging – This track includes package reliability, with research on experimental testing and simulation methods of evaluating solder ball joints, interconnects, and multichip modules; lead-free solder materials, and wirebonding techniques.
  • Advanced Technologies – Highlights include advances in LED technology, wafer-level and chipscale packaging developments, MEMS and sensor packaging, and emerging technologies such as printed electronics.
  • Modeling & Reliability – Papers in this track discuss new modeling approaches for emerging technologies such as 3D and multichip modules; signal/power integrity issues, and flip-chip and wafer-bonding processes.

A complete list of the technical program sessions is available at: www.imaps.org/imaps2010/program.htm

In addition to the main technical papers, an interactive session consisting of more than 30 poster presentations will be held, giving conference participants the opportunity for detailed interaction with the researchers.

IMAPS 2010 offers a comprehensive offering of Professional Development Courses that provide detailed information on topics of immediate interest to the microelectronics and packaging community. Held for two days prior to the conference and exhibition, on October 31 and November 1, there are 18 Professional Development Courses, taught by recognized industry experts, designed to give attendees an opportunity to integrate the latest advances in materials and technologies to help them stay competitive in today’s global microelectronics market. A complete list of the IMAPS 2010 PDCs is available at: www.imaps.org/imaps2010/pdcs.htm

The IMAPS 2010 Global Business Council Marketing Forum is a business session open to all IMAPS 2010 attendees. Held on Wednesday November 3, 2010 at 5:00pm, this year’s session is titled "Materials for Photovoltaics & 3D Packaging," and includes:

  • An Electronic Material Supplier’s Perspective on Challenges & Opportunities in 3D Packaging" by Leo Linehan, Global Business Director of Advanced Packaging Technologies, Dow Electronic Materials
  • "The Critical Role of Materials in the Photovoltaic Industry" by David Miller, President of DuPont Electronics & Communications

IMAPS 2010 will feature two world-renown keynote presentations:

  • Dr. John Edmond, co-founder, CREE Research – "High Efficiency Blue & White LEDs for the New Lightbulb"
  • Dr. Rao Tummala, professor & director of 3D Systems Packaging Research Center at the Georgia Institute of Technology – Grand Challenges & Potential Solutions in the Changing World of Nanoelectronics from ICs to 3D ICs to 3D Systems"

IMAPS 2010 will also include a comprehensive student program for both university and high school students that features a student paper competition, a student booth competition, and a tour of the DuPont Microcircuit Material Headquarters in RTP.  An employment center for students will also be available.

IMAPS 2010 has an exhibit hall as well, with exhibits from companies representing all sectors of the microelectronics supply chain.

Early registration for IMAPS 2010 is open until September 28, 2010. Complete information is available at: www.imaps.org/

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(September 23, 2010) — RJR Polymers, developer of high-performance semiconductor packaging, debuted a new generation of Liquid Crystal Polymer (LCP) quad flat-pack no-lead (QFN), air-cavity packages that will support finer lead pitches, thinner leadframes and shorter wire bond lengths in a near hermetic, ROHS-compliant solution.

Able to withstand three non-lead reflows while remaining leak tight, these new MSL III packages will support leadframes as thin as 0.008in (0.20mm) and greater.

In early testing the new QFN packages have repeatedly passed over 500 thermal cycles from -65° to +150°C with no gross leak failures. The packages have also been successfully tested with a variety of plating types including NiAu and NiPdAu finishes. The packages can be tailored to address specific conditions and requirements of any assembly process.

RJR Polymer’s line of LCP QFN solutions offers a number of advantages over traditional ceramic QFN packaging options. These air cavity packages support high frequency performance up to 38 GHz, and demonstrate a return loss (S11) of more than -15 dB and insertion loss (S21) of less than -0.5 dB in the Ku-band. At the same time the technology’s use of a solid metal die pad delivers significantly better thermal management capabilities than traditional ceramic solutions. The technology’s 0.02% moisture absorption rate enables the development of near-hermetic packages. The LCP process is said to have a relatively low cost of entry for a proven platform.

“Over the last few years or so our LCP QFN packages have offered a highly attractive solution for commercial microwave and millimeter wave applications, but have been limited by lead pitch and package frame dimensions,” noted Dave DeWire, director of sales and marketing. “With finer lead pitches and thinner lead frames, LCP-based QFN solutions can reach a wider array of applications.”

RJR Polymers, Inc. is a developer of LCP semiconductor packaging, epoxies, epoxy-coated lids and sealing equipment for a wide variety of applications in the RF, cellular, automotive, optical, imaging, avionics and sensor markets as well as emerging applications in solar power, high-power LEDs and system-level solutions that require extremely high levels of integration. For more information, visit the company’s website at www.rjrpolymers.com.

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Also read: Wafer-level Microbumping for Flip Chips, by JEAN-CHARLES SOURIAU, JEAN BRUN, RÉMI FRANIATTE, LYDIE MATHIEU, GÉRARD PONTHENIER, AND NICOLAS SILLON
and Wafer-level Hermetic Cavity Packaging by George A. Riley

(September 22, 2010 – BUSINESS WIRE) — Tessera Technologies, Inc. (Nasdaq:TSRA) announced that Fujitsu Limited, provider of ICT-based business solutions, renewed its worldwide licensing agreement with Tessera’s semiconductor packaging subsidiary, Tessera Inc. Under the agreement, which was renewed in accordance with its original terms, Fujitsu is licensed to Tessera’s semiconductor packaging technology covering a broad range of chipscale and multi-chip package types.

“We are pleased Fujitsu has renewed its license agreement with us, extending the long-term commercial relationship between our two companies," said Henry R. Nothhaft, chairman and CEO, Tessera. “Tessera provides royalty-bearing licenses to a broad portfolio of semiconductor packaging intellectual property, which is used by leading members of the semiconductor industry worldwide. We continue our efforts to make our innovative technologies widely available, helping to enable the long-term growth of our served semiconductor markets.”

Tessera Technologies, Inc. invests in, licenses and delivers innovative miniaturization technologies for next-generation electronic devices. The company’s micro-electronics solutions enable smaller, higher-functionality devices through chip-scale, 3D and wafer-level packaging technology, as well as high-density substrate and silent air cooling technology. For information, go to www.tessera.com.

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