Category Archives: Semicon West

by Debra Vogler, senior technical editor

SEMATECH is continuing to discuss many of the themes from papers it presented at the VLSI Symposium (see our previous reports on the VLSI Symposium by SST editorial board member John Borland: Part 1 and Part 2). According to Raj Jammy, director of front end processes at SEMATECH, the consortia has settled on a gate first/high-k metal-inserted poly stack (MIPS) electrode approach instead of FUSI or replacement gates. “We’ve been doing high-k/metal gate [research] for quite a while and we chose a path that was more manufacturable and that fits in more easily with existing technologies in terms of scalability, contamination prevention, and integration,” said Jammy, in a pre-show interview with WaferNEWS.

Noting that FUSI hasn’t played a role in recent announcements from IC manufacturers, Jammy told WaferNEWS that it has a long way to go until it is manufacturable. “Replacement gate is an option; a couple of companies have pursued it,” he said, though he noted that scalability of this approach is also a big issue.

SEMATECH continues to remain mum about exactly which materials systems are preferred for pFET metals — details are reserved for consortia members, but Jammy did say that three or four solutions have been discussed. For nFET metals, two candidate systems within the lanthanide series have been identified, but which of these is the best is, again, only available to member companies.

Along with materials selection, annealing is another “hot” topic at SEMICON West. Jammy noted that at 45nm, some companies will use millisecond annealing (flash or laser), though some may only need spike annealing at this node. By 32nm, however, he projects that almost everyone will have to use millisecond annealing, with the possibility that some applications may need a combination of the two anneals. — D.V.

(July 19, 2007) SAN FRANCISCO &#151 SEMICON West, July 16–20 in San Francisco, is featuring next-generation semiconductor and package test technologies on the exhibit floor, in presentations, and during the show’s TechXPOTS. Following are the probe-testing product announcements from Scanimetrics, Wentworth Labs, and SUSS.

by M. David Levenson, Editor-In-Chief, Microlithography World

The main topics for discussion at Applied Materials’ press event at SEMICON West on Tuesday (July 17) were about high-k/metal gate processes (HK+MG) and double patterning lithography, though much of the talks concentrated on the gate technology. Still, the self-aligned double patterning results described in a handout seemed really impressive. To make a 22nm half-pitch structure, Applied first printed 22nm lines at 88nm pitch in APF using an immersion stepper at Albany Nanotech, according to Kenneth MacWilliams, VP and GM of the Mayden Technology Center. Then they deposited 22nm of nitride on the APF and removed the sacrificial APF structure. The result was a 22nm half-pitch nitride that could be etched into the substrate (see Fig.1 above). Ultimately that method could be used on a complex TANOS flash memory gate stack at 32nm (see Fig.2, below).

Complicated gate stacks will be used in the next generation of flash memory as well as for future logic. The ability to etch perpendicular walls in all the complex films — without footing or undercutting — will be key to making future generation technologies work. The complex multi-chamber cluster tools introduced at the Applied lunch can now do that, at very small dimension.

To emphasize the lunchtime event’s theme that “The transistor is cool again,” the centerpiece of every table was a foot-square cube of clear ice, with the topic and Applied logo printed on two sides in porous white ice. Verlyn Fischer, senior product marketing manager, etch products business group, suggested that a damascene process was used to make them. First the cube of clear glass was frozen out of de-aerated water and then trenches forming the logo and lettering were milled into the very-cold crystal. Those trenches were then filled with carbonated water that froze as bubbly white ice, and then capped with a thin layer of slowly frozen air-free water. A final CMP-like polish insured optical quality surfaces. — M.D.L.

by Bob Haavind, Editorial Director, Solid State Technology

In one of his famous tour-de-force portraits of the progression of semiconductor technology, Paolo Gargini, Intel Fellow and director of technology strategy, linked past developments to the future in a SEMICON West keynote talk. An overflow room with piped-in video was needed to accommodate attendees.

Because of high carrier mobility, he suggested that indium antimonide (InSb) as well as germanium (Ge) might play an important role in future chips, perhaps deposited locally. He pointed out that when it became clear that ultrathin gate oxide would finally choke off traditional transistor scaling that had allowed smooth circuit shrinks for three decades, many engineers began to quake. He suggested that while physical limits do exist, innovative ideas can often find a way around them.

In developing the first semiconductor devices, for example, Shockley’s concept for using a field effect to modulate charge flow didn’t work in practice. John Bardeen showed that the problem lay in free surface states that trapped charge carriers and choked off flow. In trying to overcome this problem, the point contact transistor, a bipolar rather than a field-effect device, emerged instead.

Later, when Dennard explained scaling concepts in the early 1970s (see past references in SST/WaferNEWS here and here), hundreds of device companies emerged. Now, a new period of innovative thinking is required to push progress further. In addition to higher mobility materials, Gargini showed how a tri-gate transistor structure offers promise for dense circuits in future generations.

Occasionally Gargini showed patents from the 1920s and 1930s that presaged today’s MOS field effect concepts, and suggested that it is worthwhile to try to identify ideal device structures and mechanisms even if they aren’t yet practical to make. The struggle to overcome limits often suggests new and fruitful directions to those willing to see the potential. — B.H.

By Fran&#231oise von Trapp, managing editor, Advanced Packaging

Participants in Tuesday’s Interconnect Symposium at SEMICON West, hosted by Kulicke & Soffa and Advanced Packaging magazine, shared insights into a list of trends, challenges, and opportunities in advanced packaging (e.g., wire-bonding and flip-chips) that are being thrust into the semiconductor manufacturing spotlight.

“This is one of the most exciting years in the industry with all the developments happening,” noted TechSearch International founder/president E. Jan Vardaman. “If you’re an advanced packaging engineer, you’re finally getting the recognition you deserve.”

Speaking to a packed audience, Vardaman led off with an analysis between wire-bonding and flip-chip trends. Advanced packaging accounted for 30% of the total packaging market in 2006, and will grow to 36.5% in 2010, according to Vardaman. “A lot of companies will tell you that their money is being made in advanced packaging,” she said.

The usual casts of characters — mobile phones, PDAs, and MP3 players — are driving the market, and the thin-is-in craze that started with Apple’s iPod is expected to continue with the iPhone, which reportedly sold more than 700,000 units in the first weekend. “There’s cool packaging inside this thing,” Vardaman noted, showing images of an iPhone teardown to identify many wire-bonded parts and a few wafer-level packages, including an Intel stacked-die package, and package-on-package (PoP) technology from Samsung consisting of a microprocessor in the bottom package with two stacked die in the top.

Stacked-die packaging reached 2.2 million units in 2006, and TechSearch expects that to hit 3.2 billion units in 2010. It has been demonstrated that 16 die can successfully be stacked, though 4-5 is more commonly seen, Vardaman noted, adding that most of these stacks are wire bonded and gold-stud bump bonded.

Looking ahead, Vardaman said that stacked package trends forecast thinner packages with higher levels of stacking and multifunctional chips. Challenges include wafer thinning and die attach, wire bonding, material selection, thermal performance, and business issues of logic and memory — the latter having driven PoP development. At least 10 major OEMS in handset and digital-still-camera markets have adopted PoP, due to the ability to use known-good-die (KDG). In 2006, 67 million PoPs shipped, and that number is expected to grow, Vardaman noted.

For IC packages, wire bonding contributes 124 billion units, or about 90% of the total available market. The remaining 10% are bumped die, though market penetration could increase to 14.9% by 2010, Vardaman suggested. Advanced packaging continues to grow in units and revenue, and 67% of all advanced packages are wire bonded — so why doesn’t flip-chip dominate? “We use what’s best suited to the technology at hand,” said Vardaman, explaining that flip-chip is used when needed for performance or for pad-limited designs. But because it’s more expensive (~30%) to build, “it’s used because you have to use it, not just for grins.” She noted that Intel has delayed major flip-chip adoption out to 2009, because wire bonding still produces viable products. And wire-bond technologies continue to advance, making the transition to flip-chip less critical. “Conventional technologies don’t stand still while novel technologies are developed,” Vardaman concluded.

Other Interconnect Symposium presenters included Stephen Lee, chief scientist at Freescale, who talked about the company’s bond-over-active (BOA) evolution and addressed the issue of metal lift failures; and Flynn Carson, STATS ChipPAC, who addressed advancements in stacked die packaging and interconnect schemes. Carson says we’re headed to increased density with through-silicon vias and 3D systems-on-chip, but that these processing developments are still a few years out. All levels of interconnection integrated together will support the next generation of highly functional cell phones, he added. Bob Chylak, Kulicke & Soffa, explained how to control pad structural damage for ultra-fine pitch copper wire. –F.v.T.

The SEMICON West Interconnect Symposium presentations will be available online at “http://www.kns.com.

July 18, 2007 – Tiger Optics LLC has unveiled at SEMICON West the HALO+, a mini-cavity ring-down spectroscopy (CRDS) analyzer capable of measuring at parts-per-trillion (PPT) levels. Sibling to Tiger’s HALO, the new HALO+ is a compact CRDS tool that can analyze moisture in gases down to ultra-low levels.

The HALO+ addresses the heretofore-unmet need for fast, accurate, calibration-free measurement of moisture in the parts-per-trillion (PPT) to parts-per-million (PPM) range. The HALO+ is suited to many challenging processes where accurate moisture measurement is particularly critical, including fixed bulk gas continuous quality control, portable mobile analytical carts, process tool monitoring, air separation and gas cylinder quality control.

Designated as a transfer standard by many of the world’s leading national laboratories, and addressing over 400 points worldwide, Tiger’s analyzers are based on an absolute principle — the Beer-Lambert Law, where the analyzers do not require costly and frequent calibration. Plus, they require no consumables and are robust and durable, as well as easier to operate than most measurement solutions

July 18, 2007 – Today at SEMICON West, SUSS MicroTec launched the ELAN CBC300SOI, its new 300mm SOI wafer bonding system, and said that it has already shipped the SOI bonding system to a leading manufacturer of SOI wafers.

At the core of the cluster tool is SUSS’ patented single-station bond technology, which allows for 300mm cleaning, aligning, and bonding to occur within a single process module. SUSS’ unique unibody dual-nozzle megasonic cleaner and programmable IR-assisted spin drying reportedly result in extremely clean wafers and controlled surface drying. Users can now control their clean and dry parameters very specifically, which is said to guarantee repeatable wafer bonding results.

The standard ELAN SOI system includes two single station bond modules, a high-resolution IR inspection module, a central material handling unit with a robust wafer handling robot and precise prealigner, and two FOUP loadports — all within a small cleanroom footprint.

July 18, 2007 – Novellus Systems Inc. has launched the VECTOR Extreme plasma enhanced chemical vapor deposition (PECVD) system and the INOVA NExT with HCM IONX ionized physical vapor deposition (PVD) source at SEMICON West.

The Vector Extreme has a throughput of up to 250 wafers/hour and is said to help chipmakers reduce average process cycle times by more than 40% as compared to other systems available in the market. Wafer inventory in the fab is also substantially reduced, giving users the flexibility to respond to ongoing changes in semiconductor market demand. Novellus’ VECTOR Extreme platform integrates up to three multistation sequential process modules with as many as 12 deposition stations onto a central wafer-handling chamber. Shipments of VECTOR Extreme for volume production are expected to start in the 2H07.

The other new product, the HCM (hollow cathode magnetron) IONX source, enables thin film barrier and copper seed deposition scalability for the 32nm node. The system is capable of copper seed re-sputter and provides improved metallic film overhang, step coverage and film quality for tantalum barrier and copper seed processes. This differentiated source technology can be applied to other thin film metal applications, including titanium and aluminum. INOVA NExT with HCM IONX is currently being qualified by multiple memory and logic manufacturers, while other customers have already adopted it as their tool of record.

July 18, 2007 – Carl Zeiss SMT AG announced at SEMICON West today its new optical lithography system for KrF, the Starlith 1000, with a numerical aperture (NA) of 0.93, which will reportedly be the highest NA for 248nm exposure wavelength available in the market.

The high NA is said to provide a more cost-effective solution for patterning of features down to 80nm in volume chip production. The Starlith 1000 system will be part of ASML’s new TWINSCAN XT:1000, which will begin shipping next year.

“Together with our strategic partner ASML, we have investigated customer needs, initiating the development of Starlith 1000. With Starlith 1000, the application range of KrF lithography is further extended,” said Winfried Kaiser, VP, product strategy at Carl Zeiss SMT’s Lithography Optics Division.