Device Architecture

DEVICE ARCHITECTURE ARTICLES



Analyst take: Inside Intel/Micron's 25nm NAND device

02/03/2010 

The move to the 2Xnm NAND flash node gives Intel and Micron a big step ahead of competitors in terms of cost and pricing, an advantage they will likely ride out as profit instead of squeezing prices further, according to an analyst.

Analysts: Samsung, TSMC comments calm capex peak fears

02/02/2010 

Breaking down the quarterly numbers and forecasts from top chip spenders TSMC and Samsung, analysts determine the main thrust is that the anticipated spending cycle isn't peaking in 1H10 after all, and could instead become heavier in 2H10 and spill into 2011.

Reader me this: The evolution and future of e-reader technology

01/27/2010 

After slow adoption, 2009 became "the year of the e-reader." Semico Research's Michell Prunty breaks down the rise of e-readers and the technology inside them, and what new functionalities, content, and technology are next.

ASM's PowerFill epi enables power management devices

01/22/2010 

ASM exec Shawn Thomas explains to SST how the company's new PowerFill process, which enables void-free filling of deep trenches with doped, epitaxial silicon, addresses needs for smaller die sizes and on-state resistance of power management devices.

Analyst: Emerging from slumber, inventories not a problem

01/12/2010 

After quickly moving to work down bloated inventories amid the onset of the 2009 industry slowdown, global semiconductor suppliers are seen with lean stockpiles heading into 1Q10, according to data from iSuppli Corp.

DARPA asks industry for affordable, low-volume integrated circuit manufacturing

01/06/2010 

Scientists at the US Defense Advanced Research Projects Agency (DARPA) are asking industry to come up with new ways of designing integrated circuits for affordable, low-volume nanofabrication for US Department of Defense (DOD) applications.

Electromigration improvement for advanced technology nodes

01/04/2010 

Hui-Jung Wu, et al., from Novellus discuss process developments and mechanisms of improving electromigration reliability, a growing concern for copper interconnects at advanced technology nodes.

Report: Toshiba, Elpida ramping capex again

01/04/2010 

Toshiba and Elpida Memory are opening their wallets again to increase capacity as demand rises, and also keep pace with market-leading Samsung, according to a local report.

Power savings of embedded computing modules (ECMs) over FR-4 implementations

12/31/2009 

Silicon circuit board (SiCB) technology allows bare-die FPGAs, CPUs, and memory to be placed together on a single silicon substrate. Embedded computing modules using SiCB offer better performance than FR-4 material -- notably 22% reduced power consumption in a typical system, reports David Blaker from siXis Inc.

IEDM 2009: NEC tips low-resistance Cu interconnects, GaN power transistors on Si

12/14/2009 

NEC Electronics disclosed two areas of work at the International Electron Devices Meeting (IEDM): a low-resistance copper interconnects with partially thickened local structure (PTL) to address resisitivity increases (and thus RF performance) in analog conductors, and high-threshold voltage-control gallium nitride (GaN) power transistors on a silicon substrate.

Gartner: Chip capex recovery marches on

12/14/2009 

The latest semiconductor capital spending forecast from Gartner solidifies the 2009 outlook with another positive bump-up, and the firm sees the climate significantly improving for almost all sectors well into the future. Gartner research VP Dean Freeman helps SST break down some of the numbers.

SEMATECH, SUSS MicroTec collaborate on next-gen device testing solutions

12/10/2009 

SUSS MicroTec will collaborate with SEMATECH’s FEP device and reliability experts to investigate complex semiconductor probing and measurement solutions for next-generation semiconductor and emerging technologies.

IEDM 2009: Intel sets records for silicon-based devices with III-V channels

12/09/2009 

Mike Mayberry, VP of Intel's technology and manufacturing group, offers SST a summary of the company's presentations at this week's International Electron Devices Meeting (IEDM) in Baltimore focused on using III-V materials in leading-edge transistors, with some record-breaking achievements in drive current and peak transconductance.

IEDM 2009: Toshiba discloses 20nm CMOS channel structure, spintronics-based MOSFET

12/09/2009 

At this week's International Electronics Devices Meeting (IEDM) in Baltimore, Toshiba has disclosed a new process step that can push bulk CMOS to the 20nm node; and the first fabrication with verified stable performance of a spintronics-based MOSFET cell.

IMEC tips GaN-on-Si for power switches

12/08/2009 

At this week's International Electron Devices Meeting (IEDM), IMEC has debuted a new GaN-on-Si double heterostructure field-effect transistor (FET) device offering low leakage and high breakdown voltage to help reduce power loss in high-power switching applications.

IEDM: Scaling to continue, but with fully depleted "disruption"

12/08/2009 

Scaling will continue to follow the Moore's Law pace and will continue to rely on silicon to the 11nm node and beyond, although the emergence of fully depleted devices will disrupt device architectures, predicted Ghavam Shahidi from IBM research division, in a talk at this week's International Electron Devices Meeting (IEDM).

IEDM 2009: HKMG gate-first vs gate-last options

12/07/2009 

Speaking at the International Electron Devices Meeting (IEDM) in Baltimore, IMEC’s Thomas Hoffman outlined challenges and possible options of high-k metal-gate (HKMG) transistor stack materials and processes for future device generations.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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