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Nakamura on blue light history and future

Nobel Laureate Shuji Nakamura provided the keynote address to the attendees at the 57th annual Electronic Materials Conference held this week in Columbus, Ohio. His talk on “The History and Developments of InGaN-based LEDs and Laser Diodes” informed and entertained the audience of materials researchers, particularly since he followed first-principles of materials science and his natural inspiration to create the world’s first commercially viable blue LEDs over 20 years ago.
Nakamura-sensei is now legendary for showing excellent GaN-based blue LED functionality in an era when ZnSe was the main material explored by almost all scientists in the world due to six orders of magnitude superior defectivity level for the latter material (due to near zero lattice mismatch between ZnSe and GaAs, instead of the extreme mismatch between GaN and sapphire). In the 57th EMC keynote, he confessed that the only reason he began work on GaN was that almost everyone else was ignoring it so he could easily get papers published on the way to earning a Ph.D., and he initially had no plans to try to create a blue LED with the material.
However, when he bought a new MOCVD reactor to grow GaN on sapphire substrates he found the capabilities of the tool to be lacking so he began daily hardware modifications and test runs, and after some months began to get surprisingly strong data. Soon his group at Nichia was reporting world record GaN optoelectronic properties, and had developed both n- and p-type GaN. However, from first principles it was known that a double-heterojunction (DH) structure would allow for band-gap and hence wavelength tuning, so he then developed the world’s first useful InGaN MOCVD process and by 1993 was able to issue a press release claiming 1000 mcd LED output. “Indium gallium nitride is the most important material, but the Nobel committee didn’t say anything about Indium gallium nitride,” reminded Nakamura.
Most of the rest of the story is well known by now, including his precedent-setting lawsuit with Nichia, move to UCSB, and founding of Soraa.
Nakamura’s vision for the the future of blue (and through integration with phosphors “white”) light can be summed up as LEDs are good but lasers are better. Relatively speaking, with lasers the current density can by many times higher, and BMW and Audi have prototype laser headlamps that can reach 2-3x farther down the road compared to the best lamps today. The challenges today are to improve efficiency and cost. Efficiency for blue LEDs are now 50-60% while lasers are only ~30%. Also, blue laser production cost is now ~10x higher than that for blue LEDs.
—E.K.

ALD of Crystalline High-K SHTO on Ge

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Alternative channel materials (ACM) such as germanium (Ge) will need to be integrated into future CMOS ICs, and one part of the integration was shown at the recent Materials Research Society (MRS) spring meeting by John Ekerdt, Associate Dean for Research in Chemical Engineering at the University of Texas at Austin, in his presentation on “Atomic Layer Deposition of Crystalline SrHfxTi1-xO3 Directly on Ge (001) for High-K Dielectric Applications.”

Strontium hafnate, SrHfO3 (SHO), and strontium titanate, SrTiO3 (STO), with dielectric constants of ~15 and ~90 (respectively) can be grown directly on Ge using atomic layer deposition (ALD). Following a post-deposition anneal at 550-590°C for 5 minutes, the perovskite films become crystalline with epitaxial registry to the underlying Ge (001) substrate. Capacitor structures using the crystalline STO dielectric show a k~90 but also high leakage current. In efforts to optimize electrical performance including leakage current and dielectric constant, crystalline SrHfxTi1-xO3 (SHTO) can be grown directly on Ge by ALD. SHTO benefits from a reduced leakage current over STO and a higher k value than SHO. By minimizing the epitaxial strain and maintaining an abrupt interface, the SHTO films are expected to reduce dielectric interface-traps (Dit) at the oxide-Ge interface.

Much of the recent conference has been archived, and can now be accessed online.

—E.K.

Bottoms-up ELD of Cobalt Plugs

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As reported in more detail at Solid State Technology, during the IEEE IITC now happening in Grenoble, imec and Lam showed a new Electroless Deposition (ELD) cobalt (Co) process that is claimed to provide void-free bottoms-up pre-filling of vias and contacts. The unit-process is intended to be integrated into flows to produce scaled interconnects for logic and DRAM ICs at the 7nm node and below. Co-incidentally at IITC this year, imec and Lam also presented on a new ELD copper (Cu) process for micron-plus-scale through-silicon vias (TSV).

The bulk resistivities of metals commonly used in IC fabrication are as follows (E-8 Ω⋅m):
Cu – 1.70,
Al – 2.74,
W – 5.3, and
Co – 5.8.
Of course, the above values for bulk materials assume minimal influence of grain sizes and boundary layers. However, in scaled on-chip interconnect structures using in today’s advanced ICs, the resistivity is dominated by grain-boundaries and interfacial materials. Consequently, the resistivity of vias in 7nm node and beyond interconnects may be similar for Cu and Co depending upon the grain-sizes and barrier layers.

The melting temperatures of these metals are as follows (°C):
Al – 660,
Cu – 1084,
Co – 1495, and
W – 3400.
With higher melting temperature compared to Cu, Co contacts/plugs would provide some of the thermal stability of W to allow for easier integration of transistors and interconnects. Seemingly, the main reason to use Co instead of W is that the latter requires CVD processing that intrinsically does not allow for bottom-up deposition.

—E.K.

CMP Slurry Trade-offs in R&D

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As covered at SemiMD.com, the CMP Users Group (of the Northern California Chapter of The American Vacuum Society) recently held a meeting in Albany, New York in collaboration with CNSE, SUNY Polytechnic Institute, and SEMATECH. Among the presentations were deep dives into the inherent challenges of CMP slurry R&D.
Daniel Dickmann of Ferro Corporation discussed trade-offs in designing CMP slurries in his presentation, “Advances in Ceria Slurries to Address Challenges in Fabricating Next Generation Devices.” Adding H2O2 to ceria slurry dramatically alters the zeta-potential of the particles and thereby alters the removal rates and selectivities. For CMP of Shallow Trench Isolation (STI) structures, adding H2O2 to the slurry allows for lowering of the particle concentration from 4% to <2% while maintaining the same removal rate. Reducing the average ceria particle size from 130nm to 70nm results in a reduction in scratch defects while maintaining the same removal rate by tuning the chemistry, but the company has not yet found chemistries that allow for reasonable removal rates with 40nm diameter particles. The ceria morphology is another variable that must be controlled according to Dickmann, “It can seem counter-intuitive, but we’ve seen that non-spherical particles can demonstrate superior removal-rates and defectivities compared to more perfect spheres.”
Selectivity is one of the most critical and difficult aspects of the CMP process, and arguably the key distinction between CMP and mere polishing. The more similarity between the two or more exposed materials, the more difficult to design high selectivity in a slurry. Generally, dielectric:dielectric selectivity is difficult, and how to develop a slurry that is highly selective to nitride (Si3N4) instead of TEOS-oxide (PECVD SiO2 using tetra-ethyl-ortho-silicate precursor) was discussed by Takeda-san of Fujimi Corporation. In general, dielectric CMP is dominated by mechanical forces, so the slurry chemistry must be tuned to achieve selectivity. Choosing <5 pH for the slurry allows for reducing the oxide removal rate while maintaining the rate of nitride removal. Legacy nitride slurries have acceptable selectivities but unacceptable edge-over-erosion (EOE) – the localized over-planarization often seen near pattern edges. Reducing the particle size reduces the mechanical force across the surface such that chemical forces dominate the removal even more, while EOE can be reduced because negatively charged particles are attracted to the positively charged nitride surface resulting in local accumulation.
—E.K.

Batteries? We don’t need no stinking batteries.

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We’re still used to thinking that low-power chips for “mobile” or “Internet-of-Things (IoT)” applications will be battery powered…but the near ubiquity of lithium-ion cells powering batteries could be threatened by capacitors and energy-harvesting circuits connected to photovoltaic/thermoelectric/piezoelectric micro-power sources. At ISSCC2015 in San Francisco last week, there were several presentations on novel chip designs that run on mere milliWatts (µW) of power, and the most energy efficient circuit blocks now target nanoWatt (nW) levels of power consumption. Two presentations covered nW-scale microprocessor designs based on the ARM Cortex-M0+ core, and a 500nW energy-harvesting interface based on a DC-DC converter operating from 1µm available power was shown by a team from Holst Centre/imec/KU Leuven working with industrial partner OMRON.

Read more on this in MicroWatt Chips shown at ISSCC available at SemiMD.

—E.K.

Oscar for DMD Inventor Hornbeck

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Kudos to Dr. Larry J. Hornbeck, the extended team at Texas Instruments (TI) that has worked on Digital Micromirror Device (DMD) technology, and to the TI executives who continued to fund the R&D through years of initial investment losses. Hornbeck has been awarded an Academy Award® of Merit (Oscar® statuette) for his contribution to revolutionizing how motion pictures are created, distributed, and viewed using DMD technology (branded as the DLP® chip for DLP Cinema® display technology from TI).

The technology now powers more than eight out of 10 digital movie theatre screens globally. Produced with different resolutions and packages, DLP chips also see use in personal electronics, industrial, and automotive markets. The present good-times with DMD are enjoyed only because TI was willing to make a major long-term bet on this novel way to modulate pixel-arrays, which required building the most complex Micro-Electro-Mechanical System (MEMS) the world had ever seen.

Development of the DLP chip began in TI’s Central Research Laboratories in 1977 when Hornbeck first created an array of “deformable mirrors” controlled with analog circuits. In 1987 he invented the DMD, and TI invested in developing multiple money-losing generations of the technology over the next 12 years. Finally, in 1999 the first full-length motion picture was shown with DLP Cinema technology, and since then TI claims that the technology has been installed in more than 118,000 theaters around the globe. We understand that TI now makes a nice profit from each chip.

“It’s wonderful to be recognized by the Academy. Following the initial inventions that defined the core technology, I was fortunate to work with a team of brilliant Texas Instruments engineers to turn the first DMD into a disruptive innovation,” said Hornbeck, who has 34 U.S. patents for his groundbreaking work in DMD technology. “Clearly, the early and continuing development of innovative digital cinema technologies by the DLP Cinema team created a definitive advancement in the motion picture industry beyond anyone’s wildest dreams.”

—E.K.

Micro-Buckled 3D Silicon Scaffolds

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A new silicon microstructural solution announced this month is so powerful in creating 3D patterns from 2D surface machining that I just have to share. The figure shows 3D silicon microstructures formed by compressive buckling. The method can be used to create objects with features as small as 100 nm that could be useful for developing new technologies for medicine, energy storage and even brain-like electronic networks. Note that the silicon is surface-machined using standard MEMS processes, and that all manner of silicon circuitry and thin-film sensors could be integrated into this silicon.

Colleagues from the University of Illinois at Urbana-Champaign, Northwestern University, Zhejiang University, East China University of Science and Technology, and Hanyang University created the new 2D-to-3D fabrication technique. Their trick is that after all other surface machining they chemically modify the square anchors in the surface pattern such that they are sticky. After the 2D pattern is released it is transferred onto a sheet of stretched silicone rubber. Allowing the rubber to relax back to its natural shape draws the squares toward each other, while the rest of the silicon buckles upwards. Using this type of controlled buckling, the team managed to produce a variety of elaborate 3D shapes.

The researchers even produced structures with multiple levels of elevation by designing shapes in which the relief of stress in the initial 2D shape would create further buckling, raising another part of the shape further. John Rogers of the University of Illinois at Urbana-Champaign, who is part of the micro-buckling team looks forward to an electronic cell or tissue scaffold, “A lot of the people that we talk to are enthusiastic about what you can do when you go from a passive scaffold to something that embeds full electronic functionality.”

The research is published in Science.

—E.K.

Ferromagnetic Room Temperature Switching

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Bismuth-ferrite could make spin-valves that use 1/10th the power of STT

A research team led by folks at Cornel University (along with University of California, Berkeley; Tsinghua University; and Swiss Federal Institute of Technology in Zurich) have discovered how to make a single-phase multiferroic switch out of bismuth ferrite (BiFeO3) as shown in an online letter to Nature. Multiferroics, allowing for the control of magnetism with an electric field, have been investigated as a potential solid-state memory cell for many years but this is the first time that reversible room-temperature switching has been reportedly achieved at room temperature. Most importantly, the energy per unit area required to switch these new cells is approximately an order of magnitude less than that needed for spin-transfer torque (STT) switching.

“The advantage here is low energy consumption,” said Cornell postdoctoral associate John Heron, in a press release. “It requires a low voltage, without current, to switch it. Devices that use currents consume more energy and dissipate a significant amount of that energy in the form of heat.”

The trick that Heron and others discovered involves a two-step sequence of partial switching events—using only applied voltages—that add up to full magnetic reversal. Previous theory had shown that single-step switching was thermodynamically impossible, and no other groups had reported work on similar two-step switching. Also published in the News & Views section of Nature is “Materials science: Two steps for a magnetoelectric switch” written by other researchers, which explores the possibilities of using this phenomenon in nanoscale memory chips.

While the thermodynamics of all of this seem incredibly positive, the kinetics of this two-step process have yet to be reported. Also, the effect seems to require specific crystal stuctures such as that of SrRuO3 in a particular orientation as electrical contacts, instead of the inherently less-expensive randomly oriented metal contacts to STT cells. Consequently, this could be inherently slow and expensive technology, and thus limited to niche applications.

—E.K.

NanoParticle Self-Assembly at UofM

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Theory and Practice synergize R&D

Sharon C. Glotzer and Nicholas A. Kotov are both researchers at the University of Michigan who were just awarded a MRS Medal at the Materials Research Society (MRS) Fall Meeting in San Francisco for their work on “Integration of Computation and Experiment for Discovery and Design of Nanoparticle Self-Assembly.” Due to the fact that surface atoms compose a large percent of the mass of nanoparticles, the functional properties of quasi-1D nanoparticles differ significantly from 2D thin-films and from 3D bulk materials. An example of such a unique functional property is seen in self-assembly of nanoparticles to form complex structures, which could find applications in renewable energy production, optoelectronics, and medical electronics.
While self-assembly has been understood as an emergent property of nanoparticles, research and development (R&D) has been somewhat limited to experimental trial-and-error due to a lack of theory. Glotzer and Kotov along with their colleagues have moved past this limit using a tight collaboration between computational prediction and experimental observation. The computational theorist Glotzer provides modeling on shapes and symmetric structures, while the experimentalist Kotov’s explores areas involving atomic composition and finite interactions. Kotov and his students create a nanoparticle and look for Glotzer and her group to explan the structure. Conversely, Glotzer predicts the formation of certain structures and has those predictions confirmed experimentally by Kotov.
One specific area the two scientists have explored is the formation of supraparticles—agglomerations of tightly packed nanoparticles that are self-limiting in size. The supraparticles are so regular in size and sphericality that they would actually pack to form face-centered-cubic (fcc) lattice-like structures. The theoretical and computational work, followed by experimental verification, further proved that these supraparticles could be formed from a vast variety of nanoparticles and even proteins, provided they were small enough and had significant van der Waals and electronic repulsion forces. This exciting development creates a whole new class of “bionic” materials that may combine biomaterials and inorganics.
—E.K.

ASML Books Production EUV Orders

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TSMC commits to two tools for delivery next year

Maybe, just maybe, ASML Holding N.V. (ASML) has made the near-impossible a reality by creating a cost-effective Extreme Ultra-Violet (EUV @ ~13.5nm wavelength) all-reflective lithographic tool. The company has announced that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has ordered two NXE:3350B EUV systems for delivery in 2015 with the intention to use those systems in production. In addition, two NXE:3300B systems already delivered to TSMC will be upgraded to NXE:3350B performance. While costs and throughputs are conspicuously not-mentioned, this is still an important step for the industry.
Perhaps acquiring Cymer to get the source-technology in-house for tighter integration was important. Perhaps evolutionary improvements crept along by tough engineering rigor. Perhaps the industry got lucky. One way or the other, ASML has had the goal of delivering not just hardware but functional uptime/availability using very complex EUV technology, and now it seems to be on the cusp of making it happen. The company claims that current EUV tools are available 50% of the time, at unspecified source power levels.
At its Investor Day in London today, ASML outlined its expected opportunity to grow net sales to about EUR 10 billion and to triple earnings per share by 2020, an indication of the confidence the company has in its technology and employees. Much of the growth will be in Deep-UV immersion tools, and in so-called “Holistic Lithography” products to deliver advanced correction capabilities. An example of Holistic Litho is Source-Mask-Optimization (SMO) that can be used for triple-patterning of a 48nm minimum pitch metal layer using DUV immersion in a Litho-Etch-Litho-Etch-Litho-Etch (LELELE) flow, such that the Depth-of-Focus (DoF) can be increased from 70 to 86nm. Holistic EUV means that SMO can reduce the dose required to get 120nm DoF from 46 to 20 mJ/cm2 for a 45nm minimum pitch metal layer.
The presentations can be found at the company’s website.
— E. K.