Tag Archives: chip

PCM + ReRAM = OUM as XPoint

The good people at TECHINSIGHTS have reverse-engineered an Intel “Optane” SSD to cross-section the XPoint cells within (http://www.eetimes.com/author.asp?section_id=36&doc_id=1331865&), so we have confirmation that the devices use chalcogenide glasses for both the switching layer and the selector diode. That the latter is labeled “OTS” (for Ovonic Threshold Switch) explains the confusion over the last year as to whether this device is a Phase-Change Memory (PCM) or Resistive Random Access Memory (ReRAM)…it seems to be the special variant of ReRAM using PCM material that has been branded Ovonic Unified Memory or “OUM” (https://www.researchgate.net/publication/260107322_Programming_Speed_in_Ovonic_Unified_Memory).

As a reminder, cross-bar ReRAM devices function by voltage-driven pulses creating resistance changes in some material. The cross-bars allow for reading and writing all the bits in a word-string in a manner similar to Flash arrays.

In complete contrast, Phase Change Memory (PCM) cells—as per the name—rely upon the change between crystalline and amorphous material phases to alter resistance. The standard way to change phases is with thermal energy from an integrated set of heater elements. The standard PCM architecture also requires one transistor for each memory cell in a manner similar to DRAM arrays.

Then we have the OUM variant of PCM as previously branded by Energy Conversion Devices (ECD) and affiliated shell-campanies founded by tap-dancer-extraordinaire Stanford Ovshinsky (https://en.wikipedia.org/wiki/Stanford_R._Ovshinsky). So-called “Ovonic” PCM cells see phase-changes driven by voltage pulses without separate heater elements, such that from a circuit architecture perspective they are cross-bar ReRAMs.

Ovshinsky et al. successfully sold this technology to industry many times. In 2000, it was licensed to STMicroelectronics. Also in 2000, it was used to launch Ovonyx with Intel investment (http://www.eetimes.com/document.asp?doc_id=1176621), at which time Intel said the technology would take a long time to commercialize. In 2005 Intel re-invested (http://www.businesswire.com/news/home/20051019005145/en/Ovonyx-Receives-Additional-Investment-Intel-Capital). Finally in 2009, Intel and Numonyx showed a functional 64Mb XPoint test chip at IEDM (http://www.eetimes.com/document.asp?doc_id=1176621).

In 2007, Ovonxyx licensed it to Hynix (http://www.eetimes.com/document.asp?doc_id=1167173), and Qimonda (https://www.design-reuse.com/news/15022/ovonyx-qimonda-sign-technology-licensing-agreement-phase-change-memory.html), and others. All of those license obligations were absorbed by Micron when acquiring Ovonyx (https://seekingalpha.com/article/3774746-micron-tainted-love). ECD is still in bankruptcy (http://www.kccllc.net/ecd/document/list/3153).

So, years of R&D and JVs are behind the XPoint Optane(TM) SSDs. They are cross-bar architecture ReRAM arrays of PCM materials, and had the term not been ruined by 17-years of over-promising and under-delivering they would likely have been called OUM chips. Many others tried and failed, but Intel/Micron finally figured out how to make commercial gigabit-scale cross-bar NVMs using OUM arrays. Now they just have to yield the profits…

—E.K.

Moore’s Law Smells Funny

…maybe we need “Integrated Cleverness Law”

“Jazz is not dead, it just smells funny.” – Frank Zappa 1973
from Be-Bop Tango (Of The Old Jazzmen’s Church)

Marketing is about managing expectations. IC marketing must position next-generation chips as adding significant new/improved functionalities, and for over 50 years the IC fab industry has leaned on the conceptual crutch of “so-called Moore’s Law” (as Gordon Moore always refers to it) to do so. For 40 years the raw device count was a good proxy for a better IC, but since the end of Dennard Scaling the raw transistor count on a chip is no longer the primary determinant of value.

Intel’s has recently released official positions on Moore’s Law, and the main position is certainly correct:  “Advances in Semi Manufacturing Continue to Make Products Better and More Affordable,” as per the sub-headline of the blog post by Stacy Smith, executive vice president leading manufacturing, operations, and sales for Intel. Smith adds that “We have seen that it won’t end from lack of benefits, and that progress won’t be choked off by economics.” This is what has been meant by “Moore’s Law” all along.

When I interviewed Gordon Moore about all of this 20 years ago (“The Return of Cleverness” Solid State Technology, July 1997, 359), he wisely reminded us that before the industry reaches the limits of physical scaling we will be working with billions of transistors in a square centimeter of silicon. There are no ends to the possibilities of cleverly combining billions of transistors with sensors and communications technologies to add more value to our world. Intel’s recent spend of US$15B to acquire MobileEye is based on a plan to cost-effective integrate novel functionalities, not to merely make the most dense IC.

EETimes reports that at the International Symposium on Physical Design (ISPD 2017) Intel described more than a dozen technologies it is developing with universities and the SRC to transcend the limitations of CMOS. Ian Young, a senior fellow with Intel’s Technology Manufacturing Group and director of exploratory integrated circuits in components research, recently became the editor-in-chief of a new technical journal called the IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, which explores these new CMOS-fab compatible processes.

Meanwhile, Intel’s Mark Bohr does an admirable job of advocating for reason when discussing the size of minimally scaled ICs. Bohr is completely correct in touting Intel’s hard-won lead in making devices smaller, and the company’s fab prowess remains unparalleled.

As I posted here three years ago in my “Moore’s Law Is Dead” blog series, our industry would be better served by retiring the now-obsolete simplification that more = better. As Moore himself says, cleverness in design and manufacturing will always allow us to make more valuable ICs. Maybe it is time to retire “Moore’s Law” and begin leveraging a term like “Integrated Cleverness Law” when telling the world that the next generation of ICs will be better.

—E.K.

300mm ams Fab Bet on IoT

Leading-edge IC fab investments are multi-billion-dollar risky bets. Insufficient demand for ICs dooms the line to economic failure regardless of the quality of design and manufacturing. Thus, it is a big deal that Austrian-headquartered ams AG—world leader in production of IC sensors, RFID chips, and power-supplies—has announced plans to set up a new silicon wafer manufacturing line in up-state New York.
To date, ams’ leading fabs run 200mm diameter silicon wafers, while the new line that is planned for 2017 will run both 200mm and 300mm diameter. With ~2.4x more chips/wafer, the commitment to a 300mm line is a sign that ams expects a major increase in demand for certain products. The vision for the Internet of Things (IoT) is that ubiquitous “smart objects” will be able to connect and exchange useful information without human direction, and the foundation of smart is sensing combined with decision-making. While other companies provide logic chips to allow for decision making, ams provides chips that can sense the world in various ways.
The investment into Marcy, New York represents a bet that there will be sustained demand for analog and sensor chips to provide much of the “smarts” for the IoT. Thus ams is planning to spend >US$2 billion over the next 20 years on capital purchases, operating expenses, and other investments in the facility. Pete Singer provides all the details in his thorough report.
—E.K.

Batteries? We don’t need no stinking batteries.

We’re still used to thinking that low-power chips for “mobile” or “Internet-of-Things (IoT)” applications will be battery powered…but the near ubiquity of lithium-ion cells powering batteries could be threatened by capacitors and energy-harvesting circuits connected to photovoltaic/thermoelectric/piezoelectric micro-power sources. At ISSCC2015 in San Francisco last week, there were several presentations on novel chip designs that run on mere milliWatts (µW) of power, and the most energy efficient circuit blocks now target nanoWatt (nW) levels of power consumption. Two presentations covered nW-scale microprocessor designs based on the ARM Cortex-M0+ core, and a 500nW energy-harvesting interface based on a DC-DC converter operating from 1µm available power was shown by a team from Holst Centre/imec/KU Leuven working with industrial partner OMRON.

Read more on this in MicroWatt Chips shown at ISSCC available at SemiMD.

—E.K.