Despite some economic woes in recent years, Europe remains dedicated to building a strong electronics industry. This was brought home to me recently when, in advance of Semicon Europa (October 7-10 in Dresden), I had a chance to talk with Heinz Kundert, president of SEMI Europe. “There are several initiatives like the KET (key enabling technology) initiative that are working on the same goals to increase the competitiveness but also to get more manufacturing back to Europe,” he said. One of these is the Horizon 2020 effort, the EU’s new program for research and innovation is part of the drive to create new growth and jobs in Europe, which will run from 2014 to 2020 with a budget of just over €70 billion (some announcement during Europa is planned). France also announced Nano 2017 and plans to invest approximately €3.5 billion in France up to 2017 in nanoelectronics.

Another interesting project, specifically aimed at boosting semiconductor manufacturing in Europe is the 10/100/20 program, which has a goal of generating €10 Billion in public/private funding for R&D, €100 billion euros investment for manufacturing, and 20% share of global chip production market by 2020. Neelie Kroes, European Commission Vice-President, commented in May of this year: “I want to double our chip production to around 20% of global production. It’s a realistic goal if we channel our investments properly. A rapid and strong coordination of public investment at EU, Member State and regional level is needed to ensure that transformation.”

Already, some significant progress has been made. Five new pilot lines were launched in May 2013 under the ENIAC Joint Undertaking (EU public-private funding program), worth over €700 million and bringing together over 120 partners. These pilot lines allow research centers and companies to cooperate across borders to test and perfect new technologies and tools, such as: technologies and equipment for GaN-based substrates; 450mm equipment and materials; 300 mm power semiconductors; new MEMS materials and packaging; and 28/20nm FD SOI.

In the past, Europe was home to around 17% of global semiconductor manufacturing, but that has declined to around 6-7% today. Turning that around to reach 20% in the next seven years will be a challenge, but where there’s a will there’s a way. “Although there are a lot of issues, and a lot of details that need to be clarified – many people are questioning whether it’s possible or not possible — but what I see is positive thinking and this is most important,” Kundert said.

If you plan to visit Semicon Europa and want to learn more, you’re in luck. “We will address all these issues on public funding, public/private partnership vision at Semicon,” Kundert said. There will be an executive summit this is addressing that issue, as well as sessions on funding to explain how SMEs (equipment suppliers) can participate. “Projects are going to be presented so people understand what’s behind all these initiatives and visions and big numbers,” he added.

Please join us for a free webcast on Advanced Packaging, to be held on September 30^th, at 11:00am Eastern, 10:00am Central and 8:00am Pacific. You can register in advance at this link: https://event.webcasts.com/starthere.jsp?ei=1021830

The webcast, which will feature presenters from Texas Instruments and Micron, will address how today’s packaging technology is driven by a combination of cost, performance, form factor and reliability. The presenters will examine new advances in conventional back-end packaging, including wafer bumping and copper wire bonding, as well as the role of new 2.5D and 3D integration. They will also focus on issues related to cost, performance (speed, power and noise immunity), form factor (thickness, weight, PCB area consumption), and testability, as well as the tradeoff of technical maturity versus risk in high-volume manufacturing. The webcast will also include new information on the Hybrid Memory Cube, a three-dimensional structure with a logic device at its base and a plurality of DRAMs vertically stacked above it using through-silicon via (TSV) connections. This is a revolution in 3D integration packaging technology, as covered in our September issue cover story.

 

Our first speaker, will be Dr. Mahadevan “Devan” Iyer. As Director of TI’s Worldwide Semiconductor Packaging operations, Dr. Iyer oversees a global team that drives a process to determine the packaging design and technologies that best meet the requirements of our customers in measures of miniaturization, performance cycle time, and cost. Dr. Iyer joined TI in 2008 to lead the global SC Packaging team. He has more than 25 years of experience in the microelectronics industry. Dr. Iyer is a recognized authority in semiconductor packaging technologies.  He has more than 150 technical publications and 28 patents to his credit.

Our second speaker will be Aron Lunde, a Product Program Manager for Micron’s Hybrid Memory Cube.  His responsibilities include coordinating Micron’s internal departments to develop, construct, and deliver the HMC to meet the demands of multiple business engagements. Mr. Lunde joined Micron in 1994 and worked as a Test Engineer for Micron’s Boise, Lehi and Singapore facilities.  He later worked as a Mobile DRAM Designer, implementing repair and test modes on original Micron designs, integrating repair schemes into DRAM and mobile device architectures, and developing tools to evaluate the efficiency of repair schemes. Mr. Lunde has a BS in Electrical Engineering from the University of Idaho and has issued 15 patents.

Thanks to our webcast provider, TalkPoint, you’ll be able to tune in using any mobile device including iPads, tablets and phones!

The webcast will be archived after the event and can be accessed for 12 months. Register now at https://event.webcasts.com/starthere.jsp?ei=1021830

The next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. According to Veeco’s Tim Pratt, Senior Director, Marketing, the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV. “Based on the yield today, the mask blank manufacturing capacity can’t produce enough mask blanks to support the ASML scanners that they’re planning to ship,” Pratt said. “ASML is going to be delivering some light source upgrades in the field and when those start happening, the effective total wafer throughput of EUV scanners in the field is going to multiply and there’s just not the supply of usable mask blanks to be able to support those.”

The requirement for 2015 is to have zero blank defects larger than 62nm. SEMATECH in 2012 reported work showing eight defects larger than 50nm. “A lot of progress being made but the elusive zero defects has not yet been hit,” Pratt said. Veeco, which is the sole supplier of EUV multilayer deposition tools, has plans to upgrade the existing Odyssey tool and launch a new platform in the 2017/2018 timeframe.

Figure 1 shows an EUV mask, which is considerably more complicated than conventional photomasks. The EUV mask begins with a substrate. On the back of the substrate you have some material that’s used for chucking (an electrostatic chuck is used to hold the mask to a stage in the ASML tool and in the Veeco ion beam deposition tool). On top of the substrate is a multilayer sandwich made up of 40-50 moly silicon pairs that creates a mirror. A ruthenium capping layer helps protect the mask. The top layer is an absorber, and that’s what gets patterned.

The photo at the bottom right of Fig. 1 shows a small pit on the substrate. “As the multilayer gets deposited on top of it, you take what in the beginning might have been a small pit and at the top it becomes 1.5X or so larger,” Pratt said. “This a common problem with EUV. These very small pits and bumps on the substrate, because of the deposition angles, the way that the multilayer is put down, as small non-killer defect on the substrate suddenly becomes a killer after deposition.”

The left photo is a larger particle that fell on the blank during deposition. Pratt said that even if you could mill that down and make it level, you would just never get the reflectivity out of the section that you need.

Where is EUV today? Billions have already been invested to build the EUV infrastructure with particular emphasis on the light source. Chipmakers have invested in ASML, and ASML acquired light-source provider Cymer. There has also been a very large Industry investment in Zeiss to build the AIMS tool, which is a defect detection and repair system at EUV wavelengths.

In July, ASML said NXE:3300 scanner imaging and overlay performance reached levels where they are engaging with customers on a strategy for the 10nm logic node insertion (23nm half pitch). Good imaging performance was shown down to 13nm half pitch, and overlay between the NXE:3300 and NXT systems, had been demonstrated at less than 3.5nm. Good performance, stability and reliability of the pre-pulse source concept was demonstrated with a rate of around 40 wafers per hour, and ASML expressed confidence in reaching the goal of 70 wafers per hour productivity in 2014.

What could derail the EUV ramp, according to Pratt, is a supply of defect-free mask blanks. “EUV is, despite many years and many dollars of investment, not yet in production. The two main gaps are the EUV light sources and the defects on the mask. As they start to make progress, people start to look more seriously at the list of things to worry about for EUV going to production. Number one on that list is the mask defects. Mask defects can come from all different sources during the entire process, from the substrate all the way through to usage in the fab,” Pratt said. “The most dangerous (un-repairable) defects come from the ML (multilayer) coating process during mask blank manufacturing. You can’t clean them and you can’t repair them and if you have more than some very small amount, there’s really nothing you can do about it. You just have to throw that mask blank away and try again, which creates a very large selling price for the mask blanks. Not just because they are difficult to make but you’re throwing away a substantial amount of what you’re trying to sell,” Pratt said.

Figure 2 illustrates the process flow for a EUV mask blank. After a substrate polishing process, the substrates goes from the substrate supplier to the mask blank supplier. At the mask blank supplier, they will deposit the multilayer, the fiducial mark and the deposition. The blank gets sold to the mask shop, which could be either captive or a merchant. That blank, which is basically a mirror at the point, gets patterned and inspected and sent off to the fab. Pratt said that once the mask hits the mask shop, there is a little more leeway in terms of the defects because the defects that occur in the mask show are usually on top. “It’s usually absorber type defects or patterning type defects and those are a lot more easily repairable,” he said.

Figure 3 shows the timeline of Veeco’s system developed, starting with a research system developed in 1996 that went to Lawrence Berkeley. The was optimized in the 2003-2010 timeframe, which included work with SEMATECH in a joint development program. That basically turned it into what Pratt describes as an R&D system. “We have a system that is being used for all the mask blanks in the world. But those mask blanks are really R&D blanks that people use for print checks and reflectivity checking, but certainly nothing they would use in a fab yet, or expect to get yield off of,” he said. “A lot of the time, you don’t know if it’s yielding or not until the very end of the process.”

Pratt said they have seen some improvements when it comes to defects. “We’re not yet where we need to be for logic high volume manufacturing, but we’re getting close to where we need to be for memory.” The real issue is the low yield. “At the current yields, that mask blank makers would need to spend a whole lot of money, probably on the order of $3 billion or so, on capital to meet what the mask blank demand would be over the next five years. That’s just not feasible. EUV clearly can’t ramp in that scenario,” Pratt said.

Veeco is addressing the defect challenge in two ways. The short-term solution is an Odyssey upgrade. The longterm solution is a new platform. “The Odyssey upgrade improves the yield of the tool. But then longer term we think the next gen is needed, especially as you get out to years 4 and 5 where high volume manufacturing starts to occur,” Pratt said.

The ion beam deposition system in shown in Figure 4. The target assembly rotates, so the process might start off with silicon, the assembly is then rotated to deposit molybdenum and rotated again to deposit ruthenium. The problem is that the ion beam doesn’t always direct hit the target. “You might have some of these high energy ion missing the target and hitting the chamber. The chamber has shields on it, but that ion can bounce around and when it hits the shields, there’s a chance that it can knock off particles,” Pratt said.

The Odyssey upgrade will: reduce source to target ion overspray and reduce high energy reflected neutrals. New ion source optics are planned as well as a larger target size. Lower beam energy operation and lower pressure operation are also planned. Those should have two benefits.

Longer term, the next generation EUV ML system will focus on particles and CWL (center wavelength) process repeatability (CWL is a measure of how reflective the mask is). The new platform will minimize particle proximity, and accommodate new source technology. A larger chamber, out-of-plane deposition geometry, low-defect clamping and integrated endpoint control are also planned. Figure 5 shows progress in defect reduction from 2004 to 2012.

If you have some news to share, send me an e-mail at [email protected],